Rainbow-electronics DS26504 User Manual

1 of 128 REV: 070105 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple

DS26504 T1/E1/J1/64KCC BITS Element 10 of 128 Table 2-2. E1-Related Telecommunications Specifications ITUT G.703 Physical/Electrical Characteristics

DS26504 T1/E1/J1/64KCC BITS Element 100 of 128 15.2 Transmit 64kHz Synchronization Interface Operation In the transmit path, the framer generateS t

DS26504 T1/E1/J1/64KCC BITS Element 101 of 128 16. 6312kHz SYNCHRONIZATION INTERFACE The DS26504 has a 6312kHz Synchronization Interface mode of op

DS26504 T1/E1/J1/64KCC BITS Element 102 of 128 17. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT The DS26504 supports the standard IEEE 1149

DS26504 T1/E1/J1/64KCC BITS Element 103 of 128 TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic

DS26504 T1/E1/J1/64KCC BITS Element 104 of 128 Select-IR-Scan All test registers retain their previous state. The instruction register remains uncha

DS26504 T1/E1/J1/64KCC BITS Element 105 of 128 Figure 17-2. TAP Controller State Diagram 1001111111111110000010000

DS26504 T1/E1/J1/64KCC BITS Element 106 of 128 17.1 Instruction Register The instruction register contains a shift register as well as a latched par

DS26504 T1/E1/J1/64KCC BITS Element 107 of 128 IDCODE When the IDCODE instruction is latched into the parallel instruction register, the identificat

DS26504 T1/E1/J1/64KCC BITS Element 108 of 128 Table 17-4. Boundary Scan Control Bits CELL # NAME TYPE CONTROL CELL 0 AD1 Output3 1 1 AD1_7_CTRL C

DS26504 T1/E1/J1/64KCC BITS Element 109 of 128 CELL # NAME TYPE CONTROL CELL 29 TNEGO observe_only 30 TCLKO observe_only 31 TCLK observe_only 3

DS26504 T1/E1/J1/64KCC BITS Element 11 of 128 3. BLOCK DIAGRAMS Figure 3-1. Block Diagram RX LIURX LIUT1/E1 SSM FRAMER64KCC DECODERCLOCK- DATATX L

DS26504 T1/E1/J1/64KCC BITS Element 110 of 128 18. FUNCTIONAL TIMING DIAGRAMS 18.1 Processor Interface 18.1.1 Parallel Port Mode See the AC Timing

DS26504 T1/E1/J1/64KCC BITS Element 111 of 128 Figure 18-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1 Figure 18-5. SPI Seria

DS26504 T1/E1/J1/64KCC BITS Element 112 of 128 Figure 18-7. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 1 Figure 18-8. SPI Ser

DS26504 T1/E1/J1/64KCC BITS Element 113 of 128 19. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………

DS26504 T1/E1/J1/64KCC BITS Element 114 of 128 Table 19-5. DC Characteristics (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS26504L; VDD = 3.3V ±5%, TA =

DS26504 T1/E1/J1/64KCC BITS Element 115 of 128 20. AC TIMING PARAMETERS AND DIAGRAMS Capacitive test loads are 40pF for bus signals and 20pF for al

DS26504 T1/E1/J1/64KCC BITS Element 116 of 128 Figure 20-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00) Figure 20-2. Intel Bu

DS26504 T1/E1/J1/64KCC BITS Element 117 of 128 Figure 20-3. Motorola Bus Timing (BTS = 1 / BIS[1:0] = 00) t ASD ASHPW t t ASL AHLtCSt ASL ttt DSWDH

DS26504 T1/E1/J1/64KCC BITS Element 118 of 128 20.2 Nonmultiplexed Bus Table 20-2. AC Characteristics, Nonmultiplexed Parallel Port (VDD = 3.3V ±5%

DS26504 T1/E1/J1/64KCC BITS Element 119 of 128 Figure 20-4. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 01) Figure 20-5. Intel Bus

DS26504 T1/E1/J1/64KCC BITS Element 12 of 128 Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only) Figure 3-3. Transmit PLL C

DS26504 T1/E1/J1/64KCC BITS Element 120 of 128 Figure 20-6. Motorola Bus Read Timing (BTS = 1 / BIS[1:0] = 01) Figure 20-7. Moto

DS26504 T1/E1/J1/64KCC BITS Element 121 of 128 20.3 Serial Bus Table 20-3. AC Characteristics, Serial Bus (VDD = 3.3V ±5%, TA = 0°C to +70°C for D

DS26504 T1/E1/J1/64KCC BITS Element 122 of 128 Figure 20-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1:0] = 10 Figure 20-9.

DS26504 T1/E1/J1/64KCC BITS Element 123 of 128 20.4 Receive Side AC Characteristics Table 20-4. Receive Side AC Characteristics (VDD = 3.3V ±5%, T

DS26504 T1/E1/J1/64KCC BITS Element 124 of 128 Figure 20-10. Receive Timing—T1, E1, 64KCC Mode tD1tD2RSERRS_8K1RCLKE1 = MSB of Channel 1T1 = F-BittD

DS26504 T1/E1/J1/64KCC BITS Element 125 of 128 20.5 Transmit Side AC Characteristics Table 20-5. Transmit Side AC Characteristics (VDD = 3.3V ±5%,

DS26504 T1/E1/J1/64KCC BITS Element 126 of 128 Figure 20-11. Transmit Timing—T1, E1, 64KCC Mode TSERTS_8K_41tD2tHDtSUTS_8K_42tSUtFtRTCLKttCLtCHCPT

DS26504 T1/E1/J1/64KCC BITS Element 127 of 128 21. REVISION HISTORY REVISION DESCRIPTION 070105 New product release.

DS26504 T1/E1/J1/64KCC BITS Element 128 of 128 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry

DS26504 T1/E1/J1/64KCC BITS Element 13 of 128 Figure 3-4. Master Clock PLL Diagram PRE-SCALERDIVIDE BY 1, 2, 4,OR 8MCLK PIN2.048MHz to1.544MHz PLL

DS26504 T1/E1/J1/64KCC BITS Element 14 of 128 4. PIN FUNCTION DESCRIPTION 4.1 Transmit PLL NAME TYPE FUNCTION PLL_OUT O Transmit PLL Output. This

DS26504 T1/E1/J1/64KCC BITS Element 15 of 128 4.3 Receive Side NAME TYPE FUNCTION RCLK O Receive Clock. Recovered 1.544MHz (T1), 2.048MHz (E1), 631

DS26504 T1/E1/J1/64KCC BITS Element 16 of 128 NAME TYPE FUNCTION RAIS O Receive Alarm Indication Signal T1 Mode: Toggles high when the receive Blue

DS26504 T1/E1/J1/64KCC BITS Element 17 of 128 NAME TYPE FUNCTION AD[6]/ TITD I/O Data Bus D[6] or Address/Data Bus AD[6]/Transmit Internal Terminat

DS26504 T1/E1/J1/64KCC BITS Element 18 of 128 NAME TYPE FUNCTION AD[1]/ RMODE3/MOSI I/O Data Bus D[1] or Address/Data Bus AD[1]/Receive Mode Select

DS26504 T1/E1/J1/64KCC BITS Element 19 of 128 NAME TYPE FUNCTION A4/CPHA/ L2 I Address Bus Bit A[4]/Serial Port Clock Phase Select/Line Build-Out

DS26502 T1/E1/J1/64KCC BITS Element 2 of 128 TABLE OF CONTENTS 1. FEATURES ...

DS26504 T1/E1/J1/64KCC BITS Element 20 of 128 NAME TYPE FUNCTION RD(DS)/ RMODE2 I Active-Low Read Input-Data Strobe/Receive Mode Select Bit 2 RD (D

DS26504 T1/E1/J1/64KCC BITS Element 21 of 128 4.6 Line Interface NAME TYPE FUNCTION MCLK I Master Clock Input. A (50ppm) clock source. This clock i

DS26504 T1/E1/J1/64KCC BITS Element 22 of 128 5. PINOUT Table 5-1. LQFP Pinout MODE PIN TYPE PARALLEL PORT SERIAL PORT HARDWARE FUNCTION 1 I/O AD

DS26504 T1/E1/J1/64KCC BITS Element 23 of 128 MODE PIN TYPE PARALLEL PORT SERIAL PORT HARDWARE FUNCTION 18 O TCLKO TCLKO TCLKO Transmit Clock Outpu

DS26504 T1/E1/J1/64KCC BITS Element 24 of 128 MODE PIN TYPE PARALLEL PORT SERIAL PORT HARDWARE FUNCTION 59 I BIS1 BIS1 BIS1 Bus Interface Sele

DS26504 T1/E1/J1/64KCC BITS Element 25 of 128 6. HARDWARE CONTROLLER INTERFACE In Hardware Controller mode, the parallel and serial port pins are

DS26504 T1/E1/J1/64KCC BITS Element 26 of 128 6.3 Line Build-Out Table 6-3. E1 Line Build-Out L2 PIN 13 L1 PIN 12 L0 PIN 11 APPLICATION N (Note 1)

DS26504 T1/E1/J1/64KCC BITS Element 27 of 128 6.4 Receiver Operating Modes Table 6-5. Receive Path Operating Mode RMODE3 PIN 64 RMODE2 PIN 61 RMODE1

DS26504 T1/E1/J1/64KCC BITS Element 28 of 128 6.6 MCLK Pre-Scaler Table 6-7. MCLK Pre-Scaler for T1 Mode MPS1 PIN 16 MPS0 PIN 15 JACKS PIN 46 MCLK (

DS26504 T1/E1/J1/64KCC BITS Element 29 of 128 6.8 Other Hardware Controller Mode Features Table 6-9. Other Operational Modes PIN DESCRIPTION RSM

DS26504 T1/E1/J1/64KCC BITS Element 3 of 128 8. T1 FRAMER/FORMATTER CONTROL REGISTERS... 39 8.1 T1 CONTROL R

DS26504 T1/E1/J1/64KCC BITS Element 30 of 128 7. PROCESSOR INTERFACE The DS26504 is controlled via a nonmultiplexed (BIS[1:0] = 01) or a multiplexed

DS26504 T1/E1/J1/64KCC BITS Element 31 of 128 are terminated when CS is removed. If CS is removed before all 8 bits of the data are read, the remain

DS26504 T1/E1/J1/64KCC BITS Element 32 of 128 7.3 Register Map Table 7-2. Register Map Sorted By Address ADDRESS TYPE REGISTER NAME REGISTER ABBREV

DS26504 T1/E1/J1/64KCC BITS Element 33 of 128 ADDRESS TYPE REGISTER NAME REGISTER ABBREVIATION 42 R/W Transmit Si Align Frame TSiAF 43 R/W Tra

DS26504 T1/E1/J1/64KCC BITS Element 34 of 128 7.3.1 Power-Up Sequence The DS26504 contains an on-chip power-up reset function that automatically cl

DS26504 T1/E1/J1/64KCC BITS Element 35 of 128 7.3.3 Mode Configuration Register Register Name: MCREG Register Description: Mode Configuration Regi

DS26504 T1/E1/J1/64KCC BITS Element 36 of 128 Register Name: TPCR1 Register Description: Transmit PLL Control Register 1 Register Address: 09h Bit

DS26504 T1/E1/J1/64KCC BITS Element 37 of 128 Register Name: TPCR2 Register Description: Transmit PLL Control Register 2 Register Address: 0Ah Bit

DS26504 T1/E1/J1/64KCC BITS Element 38 of 128 individually poll certain bits without disturbing the other bits in the register. This operation is ke

DS26504 T1/E1/J1/64KCC BITS Element 39 of 128 8. T1 FRAMER/FORMATTER CONTROL REGISTERS The T1 framer portion of the DS26504 is configured via a set

DS26504 T1/E1/J1/64KCC BITS Element 4 of 128 17.5 IDENTIFICATION REGISTER ...

DS26504 T1/E1/J1/64KCC BITS Element 40 of 128 Register Name: T1RCR2 Register Description: T1 Receive Control Register 2 Register Address: 04h Bit

DS26504 T1/E1/J1/64KCC BITS Element 41 of 128 Register Name: T1TCR1 Register Description: T1 Transmit Control Register 1 Register Address: 05h Bit

DS26504 T1/E1/J1/64KCC BITS Element 42 of 128 Register Name: T1TCR2 Register Description: T1 Transmit Control Register 2 Register Address: 06h Bit

DS26504 T1/E1/J1/64KCC BITS Element 43 of 128 Register Name: T1CCR Register Description: T1 Common Control Register Register Address: 07h Bit # 7

DS26504 T1/E1/J1/64KCC BITS Element 44 of 128 Table 8-1. T1 Alarm Criterion ALARM SET CRITERION CLEAR CRITERION Blue Alarm (AIS) (Note 1) Over a 3

DS26504 T1/E1/J1/64KCC BITS Element 45 of 128 9. E1 FRAMER/FORMATTER CONTROL REGISTERS The E1 framer portion of the DS26504 is configured via a set

DS26504 T1/E1/J1/64KCC BITS Element 46 of 128 Table 9-1. E1 Sync/Resync Criterion FRAME OR MULTIFRAME LEVEL SYNC CRITERION RESYNC CRITERION ITU S

DS26504 T1/E1/J1/64KCC BITS Element 47 of 128 Register Name: E1TCR Register Description: E1 Transmit Control Register Register Address: 1Eh Bit #

DS26504 T1/E1/J1/64KCC BITS Element 48 of 128 9.2 E1 Information Registers Register Name: INFO2 Register Description: Information Register 2 Regis

DS26504 T1/E1/J1/64KCC BITS Element 49 of 128 Table 9-2. E1 Alarm Criterion ALARM SET CRITERION CLEAR CRITERION ITU SPEC. RLOF An RLOF condition e

DS26504 T1/E1/J1/64KCC BITS Element 5 of 128 LIST OF FIGURES Figure 3-1. Block Diagram ...

DS26504 T1/E1/J1/64KCC BITS Element 50 of 128 Register Name: SR2 Register Description: Status Register 2 Register Address: 16h Bit # 7 6 5 4 3 2

DS26504 T1/E1/J1/64KCC BITS Element 51 of 128 Register Name: IMR2 Register Description: Interrupt Mask Register 2 Register Address: 17h Bit # 7 6

DS26504 T1/E1/J1/64KCC BITS Element 52 of 128 10. I/O PIN CONFIGURATION OPTIONS Register Name: IOCR1 Register Description: I/O Configuration Regis

DS26504 T1/E1/J1/64KCC BITS Element 53 of 128 Table 10-1. TS_8K_4 Pin Functions TRANSMIT MODE IOCR1.3 IOCR1.2 IOCR1.1 TS_8K_4 FUNCTION T1/E1 0 0

DS26504 T1/E1/J1/64KCC BITS Element 54 of 128 Register Name: IOCR2 Register Description: I/O Configuration Register 2 Register Address: 02h Bit #

DS26502 T1/E1/J1/64KCC BITS Element 55 of 128 11. T1 SYNCHRONIZATION STATUS MESSAGE The DS26504 has a BOC controller to handle SSM services in T1 m

DS26504 T1/E1/J1/64KCC BITS Element 56 of 128 11.3 Receive BOC The receive BOC function is enabled by setting BOCC.4 = 1. The RFDL register will now

DS26504 T1/E1/J1/64KCC BITS Element 57 of 128 Register Name: BOCC Register Description: BOC Control Register Register Address: 1Fh Bit # 7 6 5 4

DS26504 T1/E1/J1/64KCC BITS Element 58 of 128 Register Name: RFDL (RFDL register bit usage when BOCC.4 = 1) Register Description: Receive FDL Regi

DS26504 T1/E1/J1/64KCC BITS Element 59 of 128 Register Name: SR3 Register Description: Status Register 3 Register Address: 18h Bit # 7 6 5 4 3

DS26504 T1/E1/J1/64KCC BITS Element 6 of 128 LIST OF TABLES Table 2-1. T1-Related Telecommunications Specifications ...

DS26504 T1/E1/J1/64KCC BITS Element 60 of 128 Register Name: IMR3 Register Description: Interrupt Mask Register 3 Register Address: 19h Bit # 7 6

DS26504 T1/E1/J1/64KCC BITS Element 61 of 128 Register Name: SR4 Register Description: Status Register 4 Register Address: 1Ah Bit # 7 6 5 4 3 2

DS26504 T1/E1/J1/64KCC BITS Element 62 of 128 Register Name: IMR4 Register Description: Interrupt Mask Register 4 Register Address: 1Bh Bit # 7 6

DS26504 T1/E1/J1/64KCC BITS Element 63 of 128 Register Name: TFDL Register Description: Transmit FDL Register Register Address: 51h Bit # 7 6 5 4

DS26504 T1/E1/J1/64KCC BITS Element 64 of 128 12. E1 SYNCHRONIZATION STATUS MESSAGE The DS26504 provides access to both the transmit and receive S

DS26504 T1/E1/J1/64KCC BITS Element 65 of 128 12.1.1 Sa Bit Change of State The DS26504 can provide an interrupt whenever one of the multiframe bas

DS26504 T1/E1/J1/64KCC BITS Element 66 of 128 Register Name: IMR5 Register Description: Interrupt Mask Register 5 Register Address: 22h Bit # 7 6

DS26504 T1/E1/J1/64KCC BITS Element 67 of 128 Register Name: RSiAF Register Description: Receive Si Bits of the Align Frame Register Address: 58h

DS26504 T1/E1/J1/64KCC BITS Element 68 of 128 Register Name: RRA Register Description: Receive Remote Alarm Register Address: 5Ah Bit # 7 6 5 4 3

DS26504 T1/E1/J1/64KCC BITS Element 69 of 128 Register Name: RSa5 Register Description: Receive Sa5 Bits Register Address: 5Ch Bit # 7 6 5 4 3 2

DS26504 T1/E1/J1/64KCC BITS Element 7 of 128 1. FEATURES 1.1 General § 64-pin, 10mm x 10mm LQFP package § 3.3V supply with 5V tolerant inputs and

DS26504 T1/E1/J1/64KCC BITS Element 70 of 128 Register Name: RSa7 Register Description: Receive Sa7 Bits Register Address: 5Eh Bit # 7 6 5 4 3 2

DS26504 T1/E1/J1/64KCC BITS Element 71 of 128 Register Name: TSiAF Register Description: Transmit Si Bits of the Align Frame Register Address: 42h

DS26504 T1/E1/J1/64KCC BITS Element 72 of 128 Register Name: TRA Register Description: Transmit Remote Alarm Register Address: 44h Bit # 7 6 5 4

DS26504 T1/E1/J1/64KCC BITS Element 73 of 128 Register Name: TSa5 Register Description: Transmit Sa5 Bits Register Address: 46h Bit # 7 6 5 4 3 2

DS26504 T1/E1/J1/64KCC BITS Element 74 of 128 Register Name: TSa7 Register Description: Transmit Sa7 Bits Register Address: 48h Bit # 7 6 5 4 3 2

DS26504 T1/E1/J1/64KCC BITS Element 75 of 128 Register Name: TSACR Register Description: Transmit Sa Bit Control Register Register Address: 4Ah Bi

DS26504 T1/E1/J1/64KCC BITS Element 76 of 128 12.2 Alternate Sa/Si Bit Access Based on Double-Frame On the receive side, the RAF and RNAF registers

DS26504 T1/E1/J1/64KCC BITS Element 77 of 128 Register Name: RNAF Register Description: Receive Non-Align Frame Register Register Address: 57h Bit

DS26504 T1/E1/J1/64KCC BITS Element 78 of 128 Register Name: TNAF Register Description: Transmit Non-Align Frame Register Register Address: 41h Bi

DS26504 T1/E1/J1/64KCC BITS Element 79 of 128 13. LINE INTERFACE UNIT (LIU) The LIU in the DS26504 contains three sections: the receiver, which han

DS26504 T1/E1/J1/64KCC BITS Element 8 of 128 1.4 Framer/Formatter § Fully independent transmit and receive functionality § Full receive and transm

DS26504 T1/E1/J1/64KCC BITS Element 80 of 128 13.1 LIU Operation The LIU interfaces the T1, E1, 64KCC, and 6312kHz signals to the various types of n

DS26504 T1/E1/J1/64KCC BITS Element 81 of 128 13.2.2 Receive G.703 Section 10 Synchronization Signal The DS26504 can receive a 2.048MHz square-wave

DS26504 T1/E1/J1/64KCC BITS Element 82 of 128 The transmit line drive has two modes of operation: fixed gain or automatic gain. In the fixed gain m

DS26504 T1/E1/J1/64KCC BITS Element 83 of 128 DS26504 will divide the internal nominal 32.768MHz (E1) or 24.704MHz (T1) clock by either 15 or 17 ins

DS26504 T1/E1/J1/64KCC BITS Element 84 of 128 13.7 LIU Control Registers Register Name: LIC1 Register Description: Line Interface Control 1 Regist

DS26504 T1/E1/J1/64KCC BITS Element 85 of 128 T1 Mode L2 L1 L0 APPLICATION N (Note 1) RETURN LOSS Rt (Note 1) 0 0 0 DSX-1 (0 to 133 feet)/0

DS26504 T1/E1/J1/64KCC BITS Element 86 of 128 Register Name: LIC2 Register Description: Line Interface Control 2 Register Address: 31h Bit # 7 6

DS26504 T1/E1/J1/64KCC BITS Element 87 of 128 Register Name: LIC3 Register Description: Line Interface Control 3 Register Address: 32h Bit # 7 6 5

DS26504 T1/E1/J1/64KCC BITS Element 88 of 128 Register Name: LIC4 Register Description: Line Interface Control 4 Register Address: 33h Bit # 7 6

DS26504 T1/E1/J1/64KCC BITS Element 89 of 128 Bits 6 and 7: MCLK Prescaler (MPS0 and MPS1) (E1 Mode) MCLK (MHz) MPS1 MPS0 JACKS0 (LIC2.3) JACKS1 (LI

DS26504 T1/E1/J1/64KCC BITS Element 9 of 128 2. SPECIFICATIONS COMPLIANCE The DS26504 meets all applicable sections of the latest telecommunications

DS26504 T1/E1/J1/64KCC BITS Element 90 of 128 Register Name: SR1 Register Description: Status Register 1 Register Address: 14h Bit # 7 6 5 4 3 2

DS26504 T1/E1/J1/64KCC BITS Element 91 of 128 Register Name: IMR1 Register Description: Interrupt Mask Register 1 Register Address: 15h Bit # 7 6

DS26504 T1/E1/J1/64KCC BITS Element 92 of 128 13.8 Recommended Circuits Figure 13-4. Basic Interface TTIPTRINGRTIPRRINGDVDD

DS26504 T1/E1/J1/64KCC BITS Element 93 of 128 Figure 13-5. Protected Interface Using Internal Receive Termination TTIPTRINGRTIPRRINGDV

DS26504 T1/E1/J1/64KCC BITS Element 94 of 128 13.9 Component Specifications Table 13-1. Transformer Specifications SPECIFICATION RECOMMENDED VALUE

DS26504 T1/E1/J1/64KCC BITS Element 95 of 128 Figure 13-6. E1 Transmit Pulse Template Figure 13-7. T1 Transmit Pulse Template

DS26504 T1/E1/J1/64KCC BITS Element 96 of 128 Figure 13-8. Jitter Tolerance (T1 Mode) Figure 13-9. Jitter Tolerance (E1 Mode)

DS26504 T1/E1/J1/64KCC BITS Element 97 of 128 Figure 13-10. Jitter Attenuation (T1 Mode) Figure 13-11. Jitter Attenuation (E

DS26504 T1/E1/J1/64KCC BITS Element 98 of 128 14. LOOPBACK CONFIGURATION Register Name: LBCR Register Description: Loopback Control Register Regis

DS26504 T1/E1/J1/64KCC BITS Element 99 of 128 15. 64kHz SYNCHRONIZATION INTERFACE The 64kHz synchronization interface conforms to Appendix II of G.