1 of 19 043001 FEATURES • Unique 1-wire interface requires only one port pin for communication • Derives power from data line (“parasite
DS18B20-PAR 10 of 19 transmitted least significant bit first. All three bytes MUST be written before the master issues a reset, or the data may be
DS18B20-PAR 11 of 19 ROM COMMANDS FLOW CHART Figure 10 CCh SKIP ROM COMMAND MASTER TX RES
DS18B20-PAR 12 of 19 DS18B20-PAR FUNCTION COMMANDS FLOW CHART Figure 11 MASTER TX FUNCTION COMMAND YN44h CONVERT TEMPERATURE ? MASTER ENABLES STRO
DS18B20-PAR 13 of 19 1-WIRE SIGNALING The DS18B20-PAR uses a strict 1-wire communication protocol to insure data integrity. Several signal types are
DS18B20-PAR 14 of 19 The DS18B20-PAR samples the 1-wire bus during a window that lasts from 15 µs to 60 µs after the master initiates the write time
DS18B20-PAR 15 of 19 the read time slot. Therefore, the master must release the bus and then sample the bus state within 15 µs from the start of th
DS18B20-PAR 16 of 19 DS18B20-PAR OPERATION EXAMPLE 1 In this example there are multiple DS18B20-PARs on the bus. The bus master initiates a tempera
DS18B20-PAR 17 of 19 ABSOLUTE MAXIMUM RATINGS* Voltage on any pin relative to ground –0.5V to +6.0V Operating temperature –55°C to +100°C Storage
DS18B20-PAR 18 of 19 AC ELECTRICAL CHARACTERISTICS (-55°C to +100°C; VPU=3.0V to 5.5V) PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS NOTESTempe
DS18B20-PAR 19 of 19 TIMING DIAGRAMS Figure 17
DS18B20-PAR 2 of 19 DETAILED PIN DESCRIPTIONS Table 1 PIN SYMBOL DESCRIPTION 1 GND Ground. 2 DQ Data Input/Output pin. Open-drain 1-wire interface
DS18B20-PAR 3 of 19 PARASITE POWER The DS18B20-PAR’s parasite power circuit allows the DS18B20-PAR to operate without a local external power supply.
DS18B20-PAR 4 of 19 resolution, bits 1 and 0 are undefined, and for 9-bit resolution bits 2, 1 and 0 are undefined. Table 2 gives examples of digit
DS18B20-PAR 5 of 19 The master device can check the alarm flag status of all DS DS18B20-PARs on the bus by issuing an Alarm Search [ECh] command. A
DS18B20-PAR 6 of 19 DS18B20-PAR MEMORY MAP cáÖìêÉ=S SCRATCHPAD (Power-up State) byte 0 Temperature LSB (50h) byte 1 Temperature MSB (05
DS18B20-PAR 7 of 19 verify that data has been read correctly, the bus master must re-calculate the CRC from the received data and then compare this
DS18B20-PAR 8 of 19 HARDWARE CONFIGURATION cáÖìêÉ=V= TRANSACTION SEQUENCE The transaction sequence for accessing the DS18B20-PAR
DS18B20-PAR 9 of 19 cycle (i.e., Search ROM command followed by data exchange) as many times as necessary to identify all of the slave devices. If
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