Rainbow-electronics ATmega64L User Manual

1Features• High-performance, Low-power AVR® 8-bit Microcontroller• Advanced RISC Architecture– 130 Powerful Instructions – Most Single-clock Cycle Exe

10ATmega16(L)2466B–09/01Stack Pointer The stack is mainly used for storing temporary data, for storing local variables and forstoring return addresses

100ATmega16(L)2466B–09/01for the output when using phase correct PWM can be calculated by the followingequation:The N variable represents the prescale

101ATmega16(L)2466B–09/01Figure 48. Phase and Frequency Correct PWM Mode, Timing DiagramThe Timer/Counter overflow flag (TOV1) is set at the same tim

102ATmega16(L)2466B–09/01The extreme values for the OCR1x register represents special cases when generating aPWM waveform output in the phase correct

103ATmega16(L)2466B–09/01Figure 51 shows the count sequence close to TOP in various modes. When using phaseand frequency correct PWM mode the OCR1x re

104ATmega16(L)2466B–09/0116-bit Timer/Counter Register DescriptionTimer/Counter 1 Control Register A – TCCR1A• Bit 7:6 - COM1A1:0: Compare Output Mode

105ATmega16(L)2466B–09/01Table 46 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to thephase correct or the phase and frequency co

106ATmega16(L)2466B–09/01Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality andl

107ATmega16(L)2466B–09/01Timer/Counter 1 Control Register B – TCCR1B• Bit 7 - ICNC1: Input Capture Noise CancelerSetting this bit (to one) activates t

108ATmega16(L)2466B–09/01If external pin modes are used for the Timer/Counter1, transitions on the T1 pin willclock the counter even if the pin is con

109ATmega16(L)2466B–09/01The input capture is updated with the counter (TCNT1) value each time an event occurson the ICP1 pin (or optionally on the an

11ATmega16(L)2466B–09/01Figure 7. Single Cycle ALU OperationReset and Interrupt HandlingThe AVR provides several different interrupt sources. These i

110ATmega16(L)2466B–09/01• Bit 5 - ICF1: Timer/Counter1, Input Capture FlagThis flag is set when a capture event occurs on the ICP1 pin. When the Inpu

111ATmega16(L)2466B–09/018-bit Timer/Counter2 with PWM and Asynchronous OperationTimer/Counter2 is a general purpose, single channel, 8-bit Timer/Coun

112ATmega16(L)2466B–09/01The double buffered Output Compare Register (OCR2) is compared with theTimer/Counter value at all times. The result of the co

113ATmega16(L)2466B–09/01top Signalizes that TCNT2 has reached maximum value.bottom Signalizes that TCNT2 has reached minimum value (zero).Depending o

114ATmega16(L)2466B–09/01OCR2 compare register to either top or bottom of the counting sequence. The synchro-nization prevents the occurrence of odd-l

115ATmega16(L)2466B–09/01Figure 56. Compare Match Output Unit, SchematicThe general I/O port function is overridden by the output compare (OC2) from

116ATmega16(L)2466B–09/01restarts from the bottom (0x00). In normal operation the Timer/Counter overflow flag(TOV2) will be set in the same timer cloc

117ATmega16(L)2466B–09/01The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).As for the normal mode of operation, the TOV2

118ATmega16(L)2466B–09/01The PWM frequency for the output can be calculated by the following equation:The N variable represents the prescale factor (1

119ATmega16(L)2466B–09/01Figure 59. Phase Correct PWM Mode, Timing DiagramThe Timer/Counter overflow flag (TOV2) is set each time the counter reaches

12ATmega16(L)2466B–09/01Note that the status register is not automatically stored when entering an interrupt rou-tine, nor restored when returning fro

120ATmega16(L)2466B–09/01Figure 60. Timer/Counter Timing Diagram, no PrescalingFigure 61 shows the same timing data, but with the prescaler enabled.F

121ATmega16(L)2466B–09/01Figure 63 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode.Figure 63. Timer/Counter Timing Diagram, Clear Tim

122ATmega16(L)2466B–09/01Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 def-initions. However, the functionality an

123ATmega16(L)2466B–09/01.Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, thecompare match is ignored, but the set

124ATmega16(L)2466B–09/01Asynchronous Operation of the Timer/CounterAsynchronous Status Register – ASSR• Bit 3 - AS2: Asynchronous Timer/Counter2When

125ATmega16(L)2466B–09/01The CPU main clock frequency must be more than four times the oscillator frequency.• When writing to one of the registers TCN

126ATmega16(L)2466B–09/01unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: 1. Write an

127ATmega16(L)2466B–09/01Timer/Counter Prescaler Figure 64. Prescaler for Timer/Counter2The clock source for Timer/Counter2 is named clkT2S. clkT2S i

128ATmega16(L)2466B–09/01Serial Peripheral Interface – SPIThe Serial Peripheral Interface (SPI) allows high-speed synchronous data transferbetween the

129ATmega16(L)2466B–09/01When configured as a Master, the SPI interface has no automatic control of the SS line.This must be handled by user software

13ATmega16(L)2466B–09/01AVR ATmega16 MemoriesThis section describes the different memories in the ATmega16. The AVR architecturehas two main memory sp

130ATmega16(L)2466B–09/01The following code examples show how to initialize the SPI as a master and how to per-form a simple transmission. DDR_SPI in

131ATmega16(L)2466B–09/01The following code examples show how to initialize the SPI as a slave and how to per-form a simple reception.Note: 1. The exa

132ATmega16(L)2466B–09/01will immediately reset the send and receive logic, and drop any partially received data inthe shift register.Master Mode When

133ATmega16(L)2466B–09/01• Bit 3 - CPOL: Clock PolarityWhen this bit is written to one, SCK is high when idle. When CPOL is written to zero,SCK is low

134ATmega16(L)2466B–09/01SPIF bit is cleared by first reading the SPI status register with SPIF set, then accessingthe SPI Data Register (SPDR).• Bit

135ATmega16(L)2466B–09/01Figure 67. SPI Transfer Format with CPHA = 0Figure 68. SPI Transfer Format with CPHA = 1Bit 1Bit 6LSBMSBSCK (CPOL = 0)mode

136ATmega16(L)2466B–09/01USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter(USART) is a highly flexible serial communica

137ATmega16(L)2466B–09/01The dashed boxes in the block diagram separate the three main parts of the USART(listed from the top): clock generator, trans

138ATmega16(L)2466B–09/01Figure 70. Clock Generation Logic, Block DiagramSignal description:txclk Transmitter clock. (Internal Signal)rxclk Receiver

139ATmega16(L)2466B–09/01Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps).BAUD Baud rate (in bits per second, bps)fOS

14ATmega16(L)2466B–09/01SRAM Data Memory Figure 9 shows how the ATmega16 SRAM Memory is organized.The lower 1120 Data Memory locations address the Reg

140ATmega16(L)2466B–09/01Figure 71. Synchronous Mode XCK Timing.The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling andwhich i

141ATmega16(L)2466B–09/01The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame.The USART Parity Mode (UPM1:0) bits enabl

142ATmega16(L)2466B–09/01USART Initialization The USART has to be initialized before any communication can take place. The initial-ization process nor

143ATmega16(L)2466B–09/01Data Transmission – The USART TransmitterThe USART transmitter is enabled by setting the Transmit Enable (TXEN) bit in theUCS

144ATmega16(L)2466B–09/01Sending Frames with 9 Data BitIf 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit inUCSRB

145ATmega16(L)2466B–09/01either write new data to UDR in order to clear UDRE or disable the data register emptyinterrupt, otherwise a new interrupt wi

146ATmega16(L)2466B–09/01Data Reception – The USART ReceiverThe USART receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRBregiste

147ATmega16(L)2466B–09/01Receiving Frames with 9 DatabitsIf 9 bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit inUCSRB be

148ATmega16(L)2466B–09/01The receive function example reads all the I/O registers into the register file before anycomputation is done. This gives an

149ATmega16(L)2466B–09/01The PE bit is set if the next character that can be read from the receive buffer had a par-ity error when received and the pa

15ATmega16(L)2466B–09/01Data Memory Access Times This section describes the general access timing concepts for internal memory access.The internal dat

150ATmega16(L)2466B–09/01Asynchronous Data ReceptionThe USART includes a clock recovery and a data recovery unit for handling asynchro-nous data recep

151ATmega16(L)2466B–09/01The decision of the logic level of the received bit is taken by doing a majority voting ofthe logic value to the three sample

152ATmega16(L)2466B–09/01SMMiddle sample number used for majority voting. SM = 9 for normal speed and SM =5 for double speed mode.Rslow is the ratio o

153ATmega16(L)2466B–09/01Multi-processor Communication ModeSetting the Multi-processor Communication Mode (MPCM) bit in UCSRA enables a fil-tering fun

154ATmega16(L)2466B–09/01Accessing UBRRH/ UCSRC RegistersThe UBRRH register shares the same I/O location as the UCSRC register. Thereforesome special

155ATmega16(L)2466B–09/01Read Access Doing a read access to the UBRRH or the UCSRC register is a more complex operation.However, in most applications,

156ATmega16(L)2466B–09/01The transmit buffer can only be written when the UDRE flag in the UCSRA register isset. Data written to UDR when the UDRE fla

157ATmega16(L)2466B–09/01• Bit 1 - U2X: Double the USART tranSmission SpeedThis bit only has effect for the asynchronous operation. Write this bit to

158ATmega16(L)2466B–09/01• Bit 0 - TXB8: Transmit Data Bit 8TXB8 is the 9th data bit in the character to be transmitted when operating with serialfram

159ATmega16(L)2466B–09/01• Bit 2:1 - UCSZ1:0: Character SizeThe UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits(charact

16ATmega16(L)2466B–09/01EEPROM Data Memory The ATmega16 contains 512 bytes of data EEPROM memory. It is organized as a sep-arate data space, in which

160ATmega16(L)2466B–09/01• Bit 11:0 - UBRR11:0: USART Baud Rate RegisterThis is a 12-bit register which contains the USART baud rate. The UBRRH contai

161ATmega16(L)2466B–09/01Table 69. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)Baud Rate (bps)fosc = 3.6864 MHz fos

162ATmega16(L)2466B–09/010.5M 0 0.0% 1 0.0% - - 2 -7.8% 1 -7.8% 3 -7.8%1M--00.0%----0-7.8%1-7.8%Max (1)0.5Mbps 1Mbps 691.2kbps 1.3824Mbps 921.6kbps 1.

163ATmega16(L)2466B–09/01Two-wire Serial InterfaceFeatures • Simple Yet Powerful and Flexible Communication Interface, Only two Bus Lines Needed• Both

164ATmega16(L)2466B–09/01Electrical Interconnection As depicted in Figure 76, both bus lines are connected to the positive supply voltagethrough pull-

165ATmega16(L)2466B–09/01Figure 78. START, REPEATED START and STOP ConditionsAddress Packet Format All address packets transmitted on the TWI bus are

166ATmega16(L)2466B–09/01more bytes, it should inform the transmitter by sending a NACK after the final byte. TheMSB of the data byte is transmitted f

167ATmega16(L)2466B–09/01• Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial clocks from all mas

168ATmega16(L)2466B–09/01Figure 83. Arbitration between Two MastersNote that arbitration is not allowed between:• A REPEATED START condition and a da

169ATmega16(L)2466B–09/01Overview of the TWI ModuleThe TWI module is comprised of several submodules, as shown in Figure 84. All regis-ters drawn in a

17ATmega16(L)2466B–09/01tion, the EEDR contains the data read out from the EEPROM at the address given byEEAR.The EEPROM Control Register – EECR• Bits

170ATmega16(L)2466B–09/01Bus Interface Unit This unit contains the Data and Address Shift register (TWDR), a START/STOP Con-troller and Arbitration de

171ATmega16(L)2466B–09/01TWI register descriptionTWI Bit Rate Register – TWBR• Bits 7..0 - TWI Bit Rate RegisterTWBR selects the division factor for t

172ATmega16(L)2466B–09/01• Bit 4 - TWSTO: TWI STOP Condition BitWriting the TWSTO bit to one in master mode will generate a STOP condition on the 2-wi

173ATmega16(L)2466B–09/01shifting a byte. This occurs when the TWI interrupt flag (TWINT) is set by hardware.Note that the data register cannot be ini

174ATmega16(L)2466B–09/01Figure 85. Interfacing the Application to the TWI in a Typical Transmission1. The first step in a TWI transmission is to tra

175ATmega16(L)2466B–09/01written. Writing a one to TWINT clears the flag. The TWI will not start any opera-tion as long as the TWINT bit in TWCR is se

176ATmega16(L)2466B–09/01Assembly code example C example Comments1ldi r16, (1<<TWINT)|(1<<TWSTA)|(1<<TWEN)out TWCR, r16TWCR = (1<

177ATmega16(L)2466B–09/01Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter(MT), Master Receiver (M

178ATmega16(L)2466B–09/01Figure 86. Data Transfer in Master Transmitter ModeA START condition is sent by writing the following value to TWCR:TWEN mus

179ATmega16(L)2466B–09/01After a repeated START condition (state $10) the 2-wire Serial Interface can access thesame slave again, or a new slave witho

18ATmega16(L)2466B–09/01EEWE has been set, the CPU is halted for two cycles before the next instruction isexecuted.• Bit 0 - EERE: EEPROM Read EnableT

180ATmega16(L)2466B–09/01Figure 87. Formats and States in the Master Transmitter ModeMaster Receiver Mode In the master receiver mode, a number of da

181ATmega16(L)2466B–09/01Figure 88. Data Transfer in Master Receiver ModeA START condition is sent by writing the following value to TWCR:TWEN must b

182ATmega16(L)2466B–09/01Table 74. Status Codes for Master Receiver Mode Status Code(TWSR)Prescaler Bitsare 0Status of the 2-wire Serial Busand 2-wir

183ATmega16(L)2466B–09/01Figure 89. Formats and States in the Master Receiver ModeSlave Receiver Mode In the slave receiver mode, a number of data by

184ATmega16(L)2466B–09/01The upper 7 bits are the address to which the 2-wire Serial Interface will respond whenaddressed by a master. If the LSB is s

185ATmega16(L)2466B–09/01Table 75. Status Codes for Slave Receiver Mode Status Code(TWSR)Prescaler Bitsare 0Status of the 2-wire Serial Bus and2-wire

186ATmega16(L)2466B–09/01Figure 91. Formats and States in the Slave Receiver ModeSlave Transmitter Mode In the slave transmitter mode, a number of da

187ATmega16(L)2466B–09/01The upper 7 bits are the address to which the 2-wire Serial Interface will respond whenaddressed by a master. If the LSB is s

188ATmega16(L)2466B–09/01Table 76. Status Codes for Slave Transmitter ModeStatus Code(TWSR)Prescaler Bitsare 0Status of the 2-wire Serial Bus and2-wi

189ATmega16(L)2466B–09/01Figure 93. Formats and States in the Slave Transmitter ModeMiscellaneous States There are two status codes that do not corre

19ATmega16(L)2466B–09/01The following code examples show one assembly and one C function for writing to theEEPROM. The examples assume that interrupts

190ATmega16(L)2466B–09/01Combining Several TWI ModesIn some cases, several TWI modes must be combined in order to complete the desiredaction. Consider

191ATmega16(L)2466B–09/01Several different scenarios may arise during arbitration, as described below:• Two or more masters are performing identical c

192ATmega16(L)2466B–09/01Analog Comparator The analog comparator compares the input values on the positive pin AIN0 and nega-tive pin AIN1. When the v

193ATmega16(L)2466B–09/01• Bit 7 - ACD: Analog Comparator DisableWhen this bit is written logic one, the power to the analog comparator is switched of

194ATmega16(L)2466B–09/01Analog Comparator Multiplexed InputIt is possible to select any of the ADC7..0 pins to replace the negative input to the ana-

195ATmega16(L)2466B–09/01Analog to Digital ConverterFeatures • 10-bit Resolution• 0.5 LSB Integral Non-Linearity• ±2 LSB Absolute Accuracy• TBD - 260

196ATmega16(L)2466B–09/01Figure 98. Analog to Digital Converter Block SchematicOperation The ADC converts an analog input voltage to a 10-bit digital

197ATmega16(L)2466B–09/01amplified value then becomes the analog input to the ADC. If single ended channels areused, the gain amplifier is bypassed al

198ATmega16(L)2466B–09/01Figure 99. ADC Auto Trigger LogicUsing the ADC Interrupt Flag as a trigger source makes the ADC start a new conversionas soo

199ATmega16(L)2466B–09/01setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADENbit is set, and is continuously reset when

2ATmega16(L)2466B–09/01Pin Configurations Figure 1. Pinouts ATmega16(XCK/T0) PB0(T1) PB1(INT2/AIN0) PB2(OC0/AIN1) PB3(SS) PB4(MOSI) PB5(MISO)

20ATmega16(L)2466B–09/01The next code examples show assembly and C functions for reading the EEPROM. Theexamples assume that interrupts are controlled

200ATmega16(L)2466B–09/01Figure 102. ADC Timing Diagram, Single ConversionFigure 103. ADC Timing Diagram, Auto Triggered ConversionFigure 104. ADC

201ATmega16(L)2466B–09/01Differential Gain Channels When using differential gain channels, certain aspects of the conversion need to betaken into cons

202ATmega16(L)2466B–09/01If Auto Triggering is used, the exact time of the triggering event can be indeterministic.Special care must be taken when upd

203ATmega16(L)2466B–09/01If the user has a fixed voltage source connected to the AREF pin, the user may not usethe other reference voltage options in

204ATmega16(L)2466B–09/01Figure 105. Analog Input CircuitryAnalog Noise Canceling TechniquesDigital circuitry inside and outside the device generates

205ATmega16(L)2466B–09/01Figure 106. ADC Power ConnectionsOffset Compensation SchemesThe gain stage has a built-in offset cancellation circuitry that

206ATmega16(L)2466B–09/01Figure 107. Offset Error• Gain error: After adjusting for offset, the gain error is found as the deviation of the last trans

207ATmega16(L)2466B–09/01Figure 109. Integral non-Linearity (INL)• Differential Non-Linearity (DNL): The maximum deviation of the actual code width (

208ATmega16(L)2466B–09/01ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found inthe ADC Result re

209ATmega16(L)2466B–09/01Example: ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result) Voltage on ADC3 is 300 mV, voltage on AD

21ATmega16(L)2466B–09/01I/O Memory The I/O space definition of the ATmega16 is shown in “Register Summary” on page 290.All ATmega16 I/Os and periphera

210ATmega16(L)2466B–09/01• Bits 4:0 - MUX4:0: Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs

211ATmega16(L)2466B–09/01ADC Control and Status Register A – ADCSRA• Bit 7 - ADEN: ADC EnableWriting this bit to one enables the ADC. By writing it to

212ATmega16(L)2466B–09/01The ADC Data Register – ADCL and ADCHADLAR = 0:ADLAR = 1:When an ADC conversion is complete, the result is found in these two

213ATmega16(L)2466B–09/01Special FunctionIO Register – SFIOR• Bit 7:5 - ADTS2:0: ADC Auto Trigger SourceIf ADATE in ADCSRA is written to one, the valu

214ATmega16(L)2466B–09/01JTAG Interface and On-chip Debug SystemFeatures • JTAG (IEEE std. 1149.1 Compliant) Interface• Boundary-scan Capabilities Acc

215ATmega16(L)2466B–09/01The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT –which is not provided.When the JTAGEN fuse is

216ATmega16(L)2466B–09/01Figure 113. TAP Controller State DiagramTAP Controller The TAP controller is a 16-state finite state machine that controls t

217ATmega16(L)2466B–09/01is left by setting TMS high. While the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out

218ATmega16(L)2466B–09/01• 2 single Program Memory break-points + 1 Program Memory break point with mask (“range break point”)• 2 single Program Memor

219ATmega16(L)2466B–09/01On-chip Debug Related Register in I/O MemoryOn-chip Debug Register – OCDRThe OCDR register provides a communication channel f

22ATmega16(L)2466B–09/01System Clock and Clock OptionsClock Systems and their DistributionFigure 11 presents the principal clock systems in the AVR an

220ATmega16(L)2466B–09/01IEEE 1149.1 (JTAG) Boundary-scanFeatures • JTAG (IEEE std. 1149.1 Compliant) Interface• Boundary-scan Capabilities According

221ATmega16(L)2466B–09/01Bypass Register The Bypass register consists of a single shift-register stage. When the Bypass registeris selected as path be

222ATmega16(L)2466B–09/01Figure 115. Reset RegisterBoundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic

223ATmega16(L)2466B–09/01SAMPLE_PRELOAD; $2 Mandatory JTAG instruction for pre-loading the output latches and talking a snap-shot ofthe input/output p

224ATmega16(L)2466B–09/01Boundary-scan Chain The Boundary-scan chain has the capability of driving and observing the logic levels onthe digital I/O pi

225ATmega16(L)2466B–09/01Figure 117. General Port Pin Schematic Diagram(1)Note: 1. See Boundary-scan descriptin for details.Boundary-scan and the Two

226ATmega16(L)2466B–09/01Figure 118. Additional Scan Signal for the Two-wire InterfaceScanning the RESET Pin The RESET pin accepts 5V active low logi

227ATmega16(L)2466B–09/01Figure 120. Boundary-scan Cells for Oscillators and Clock OptionsTable 89 summaries the scan registers for the external cloc

228ATmega16(L)2466B–09/01Figure 121. Analog ComparatorFigure 122. General Boundary-scan Cell used for Signals for Comparator and ADCACBGBANDGAPREFER

229ATmega16(L)2466B–09/01Scanning the ADCFigure 123 shows a block diagram of the ADC with all relevant control and observe signals. The Boundary-scan

23ATmega16(L)2466B–09/01Asynchronous Timer Clock – clkASYThe Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clockeddirectly from

230ATmega16(L)2466B–09/01Table 91. Boundary-scan Signals for the ADC Signal NameDirection as Seenfrom the ADC DescriptionRecommended Input when not i

231ATmega16(L)2466B–09/01Note: Incorrect setting of the switches in Figure 123 will make signal contention and may damage the part. There are several

232ATmega16(L)2466B–09/01If the ADC is not to be used during scan, the recommended input values from Table 91should be used. The user is recommended n

233ATmega16(L)2466B–09/01Figure 124. ADC Timing Diagram and Timing ConstraintsAs an example, consider the task of verifying a 1.5V ± 5% input signal

234ATmega16(L)2466B–09/01Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clockfrequency. As the algorithm keeps HOLD

235ATmega16(L)2466B–09/01ATmega16 Boundary-scan OrderTable 94 shows the Scan order between TDI and TDO when the Boundary-scan chainis selected as data

236ATmega16(L)2466B–09/01112 MUXEN_7 ADC111 MUXEN_6110 MUXEN_5109 MUXEN_4108 MUXEN_3107 MUXEN_2106 MUXEN_1105 MUXEN_0104 NEGSEL_2103 NEGSEL_1102 NEGSE

237ATmega16(L)2466B–09/0181 PB5.Data Port B80 PB5.Control79 PB5.Pullup_Enable78 PB6.Data77 PB6.Control76 PB6.Pullup_Enable75 PB7.Data74 PB7.Control73

238ATmega16(L)2466B–09/0146 PD5.Data Port D45 PD5.Control44 PD5.Pullup_Enable43 PD6.Data42 PD6.Control41 PD6.Pullup_Enable40 PD7.Data39 PD7.Control38

239ATmega16(L)2466B–09/01Note: PRIVATE_SIGNAL1 should always be scanned in as zero.Boundary-scan Description Language FilesBoundary-scan Description L

24ATmega16(L)2466B–09/01For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and16 MHz with CKOPT programmed. C1 and C2 should alway

240ATmega16(L)2466B–09/01Boot Loader Support – Read-While-Write Self-ProgrammingThe Boot Loader Support provides a real Read-While-Write self-programm

241ATmega16(L)2466B–09/01Note that the user software can never read any code that is located inside the RWWsection during a Boot Loader software opera

242ATmega16(L)2466B–09/01Figure 125. Read-While-Write vs. No Read-While-WriteRead While Write(RWW) SectionNo Read While Write (NRWW) SectionZ-pointer

243ATmega16(L)2466B–09/01Figure 126. Memory SectionsNote: The parameters in the figure above are given in Table 100 on page 252.Boot Loader Lock Bits

244ATmega16(L)2466B–09/01Note: 1. "1" means unprogrammed, "0´means programmedNote: 1. "1" means unprogrammed, "0´means p

245ATmega16(L)2466B–09/01Note: 1. "1" means unprogrammed, "0´means programmedStore Program Memory Control Register – SPMCRThe Store Pro

246ATmega16(L)2466B–09/01page address is taken from the high part of the Z pointer. The data in R1 and R0 areignored. The PGWRT bit will auto-clear up

247ATmega16(L)2466B–09/01Figure 127. Addressing the Flash during SPM(1)Note: 1. The different variables used in Figure 127 are listed in Table 102 on

248ATmega16(L)2466B–09/01Performing Page Erase by SPMTo execute page erase, set up the address in the Z pointer, write "X0000011" toSPMCR an

249ATmega16(L)2466B–09/01See Table 96 and Table 97 for how the different settings of the Boot Loader Bits affectthe Flash access.If bits 5..2 in R0 ar

25ATmega16(L)2466B–09/01The CKSEL0 fuse together with the SUT1..0 fuses select the start-up times as shown inTable 5.Notes: 1. These options should on

250ATmega16(L)2466B–09/01correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supplyvoltage for executing instructions is

251ATmega16(L)2466B–09/01call Do_spmadiw ZH:ZL, 2sbiw loophi:looplo, 2 ;use subi for PAGESIZEB<=256brne Wrloop; execute page writesubi ZL, low(PAGE

252ATmega16(L)2466B–09/01Note: 1. The different BOOTSZ fuse configurations are shown in Figure 126Note: 1. For details about these two section, see “N

253ATmega16(L)2466B–09/01Memory ProgrammingProgram And Data Memory Lock BitsThe ATmega16 provides six Lock bits which can be left unprogrammed ("

254ATmega16(L)2466B–09/01Notes: 1. Program the fuse bits before programming the Lock bits.2. "1" means unprogrammed, "0´means programme

255ATmega16(L)2466B–09/01Notes: 1. The default value of SUT1..0 results in maximum start-up time. SeeTable 10 on page27 for details.2. The default set

256ATmega16(L)2466B–09/01The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a posi-tive pulse. The bit coding is shown in Tabl

257ATmega16(L)2466B–09/01Table 108. Pin Values used to Enter Programming ModePin Symbol ValuePAGEL Prog_enable[3] 0XA1 Prog_enable[2] 0XA0 Prog_enabl

258ATmega16(L)2466B–09/01Parallel ProgrammingEnter Programming Mode The following algorithm puts the device in parallel programming mode:1. Apply 4.5

259ATmega16(L)2466B–09/014. Give XTAL1 a positive pulse. This loads the address low byte.C. Load Data Low Byte1. Set XA1, XA0 to '01'. This

26ATmega16(L)2466B–09/01When this oscillator is selected, start-up times are determined by the SUT fuses asshown in Table 6.Note: 1. These options sho

260ATmega16(L)2466B–09/01Figure 129. Addressing the Flash which is Organized in PagesNote: 1. PCPAGE and PCWORD are listed in Table 111 on page 257.F

261ATmega16(L)2466B–09/01Programming the EEPROM The EEPROM is organized in pages, see Table 112 on page 257. When programmingthe EEPROM, the program d

262ATmega16(L)2466B–09/015. Set BS1 to "1". The Flash word high byte can now be read at DATA.6. Set OE to "1".Reading the EEPROM T

263ATmega16(L)2466B–09/01Figure 132. Mapping between BS1, BS2 and the Fuse- and Lock Bits during ReadReading the Signature Bytes The algorithm for re

264ATmega16(L)2466B–09/01Figure 134. Parallel Programming Timing, Loading Sequence with TimingRequirements(1)Note: 1. The timing requirements shown i

265ATmega16(L)2466B–09/01Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse Bits and Write LockBits commands.2. tWLRH_CE is vali

266ATmega16(L)2466B–09/01Serial Programming Pin MappingFigure 136. Serial Programming and VerifyNote: If the device is clocked by the internal oscill

267ATmega16(L)2466B–09/01power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set

268ATmega16(L)2466B–09/01least tWD_EEPROM before programming the next byte. See Table 115 for tWD_EEPROMvalue.Figure 137. Serial Programming Waveform

269ATmega16(L)2466B–09/01Note: a = address high bitsb = address low bitsH = 0 - Low byte, 1 - High Byteo = data outi = data inx = don"t careTable

27ATmega16(L)2466B–09/01Note: 1. This option should not be used when operating close to the maximum frequency ofthe device.Calibrated Internal RC Osci

270ATmega16(L)2466B–09/01Serial Programming CharacteristicsFigure 138. Serial Programming TimingNote: 1. 2 tCLCL for fck < 12 MHz, 3 tCLCL for fck

271ATmega16(L)2466B–09/01Figure 139. State Machine Sequence for Changing the Instruction WordAVR_RESET ($C) The AVR specific public JTAG instruction

272ATmega16(L)2466B–09/01PROG_COMMANDS ($5) The AVR specific public JTAG instruction for entering programming commands via theJTAG port. The 15-bit Pr

273ATmega16(L)2466B–09/01When the contents of the register is equal to the programming enable signature, pro-gramming via the JTAG port is enabled. Th

274ATmega16(L)2466B–09/01Table 118. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o

275ATmega16(L)2466B–09/015c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx5d. Read Data Byte 0110011_bbbbbbbb0110010_000000000110011_0000000

276ATmega16(L)2466B–09/01Notes: 1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is

277ATmega16(L)2466B–09/01Figure 142. State Machine Sequence for Changing/Reading the Data WordVirtual Flash Page Load RegisterThe Virtual Flash Page

278ATmega16(L)2466B–09/01Figure 143. Virtual Flash Page Load RegisterVirtual Flash Page Read RegisterThe Virtual Flash Page Read register is a virtua

279ATmega16(L)2466B–09/01Programming Algorithm All references below of type “1a”, “1b”, and so on, refer to Table 118.Entering Programming Mode 1. Ent

28ATmega16(L)2466B–09/01Oscillator Calibration Register – OSCCAL• Bits 7..0 - CAL7..0: Oscillator Calibration ValueWriting the calibration byte to thi

280ATmega16(L)2466B–09/016. Enter JTAG instruction PROG_COMMANDS.7. Write the page using programming instruction 2g.8. Poll for Flash write complete u

281ATmega16(L)2466B–09/01Programming the Fuses 1. Enter JTAG instruction PROG_COMMANDS.2. Enable Fuse write using programming instruction 6a.3. Load d

282ATmega16(L)2466B–09/01Electrical CharacteristicsAbsolute Maximum Ratings*Operating Temperature... -55°C to +125°C*NO

283ATmega16(L)2466B–09/01Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low2. “Min” means the lowest value where th

284ATmega16(L)2466B–09/018] The sum of all IOH, for ports D4-D7, should not exceed 100 mAIf IOH exceeds the test condition, VOH may exceed the related

285ATmega16(L)2466B–09/012-wire Serial Interface CharacteristicsTable 121 describes the requirements for devices connected to the 2-wire Serial Bus. T

286ATmega16(L)2466B–09/015. This requirement applies to all ATmega16 2-wire Serial Interface operation. Otherdevices connected to the 2-wire Serial Bu

287ATmega16(L)2466B–09/01Figure 147. SPI Interface Timing Requirements (Master Mode)Figure 148. SPI Interface Timing Requirements (Slave Mode)MOSI(D

288ATmega16(L)2466B–09/01ADC Characteristics – Preliminary DataNotes: 1. Values aren guidelines only. Actual values are TBD.2. Minimum for AVCC is 2.7

289ATmega16(L)2466B–09/01ATmega16 Typical Characteristics – Preliminary DataThe following charts show typical behavior. These figures are not tested d

29ATmega16(L)2466B–09/01When this clock source is selected, start-up times are determined by the SUT fuses asshown in Table 12.Timer/Counter Oscillato

290ATmega16(L)2466B–09/01Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page$3F ($5F) SREG I T H S V N Z C 7$3E ($5E) S

291ATmega16(L)2466B–09/01Notes: 1. When the OCDEN fuse is unprogrammed, the OSCCAL register is always accessed on this address. Refer to the debuggers

292ATmega16(L)2466B–09/01Instruction Set Summary Mnemonics Operands Description Operation Flags #ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add

293ATmega16(L)2466B–09/01BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1 / 2BRID k Branch if Interrupt Disabled if ( I =

294ATmega16(L)2466B–09/01CLH Clear Half Carry Flag in SREG H ← 0 H 1MCU CONTROL INSTRUCTIONSNOP No Operation None 1SLEEP Sleep (see specific descr. f

295ATmega16(L)2466B–09/01Ordering InformationSpeed (MHz) Power Supply Ordering Code Package Operation Range8 2.7 - 5.5V ATmega16L-8ACATmega16L-8PC44A4

296ATmega16(L)2466B–09/01Packaging Information44A1.20(0.047) MAX10.10(0.394) 9.90(0.386)SQ12.25(0.482)11.75(0.462)SQ0.75(0.030)0.45(0.018)0.15(0.006)

297ATmega16(L)2466B–09/0140P652.71(2.075)51.94(2.045)PIN113.97(0.550)13.46(0.530)0.38(0.015)MIN0.56(0.022)0.38(0.015)REF15.88(0.625)15.24(0.600)1.65(0

© Atmel Corporation 2001.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa

3ATmega16(L)2466B–09/01Overview The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhancedRISC architecture. By executing powerf

30ATmega16(L)2466B–09/01Power Management and Sleep ModesSleep modes enable the application to shut down unused modules in the MCU, therebysaving power

31ATmega16(L)2466B–09/01Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enterIdle Mode, stopping the CPU but al

32ATmega16(L)2466B–09/01asynchronous timer should be considered undefined after wake-up in Power-save modeif AS2 is 0.This sleep mode basically halts

33ATmega16(L)2466B–09/01Analog Comparator When entering Idle Mode, the Analog Comparator should be disabled if not used. Whenentering ADC Noise Reduct

34ATmega16(L)2466B–09/01System Control and ResetResetting the AVR During reset, all I/O registers are set to their initial values, and the program sta

35ATmega16(L)2466B–09/01Figure 15. Reset LogicNotes: 1. Values are guidelines only. Actual values are TBD.2. The Power-on Reset will not work unless

36ATmega16(L)2466B–09/01Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-tion level is defined in T

37ATmega16(L)2466B–09/01Figure 18. External Reset During OperationBrown-out Detection ATmega16 has an On-chip Brown-out Detection (BOD) circuit for m

38ATmega16(L)2466B–09/01Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 CK cycle dura-tion. On the falling edge

39ATmega16(L)2466B–09/01Internal Voltage ReferenceATmega16 features an internal bandgap reference. This reference is used for Brown-out Detection, and

4ATmega16(L)2466B–09/01The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are directly connec

40ATmega16(L)2466B–09/01Figure 21. Watchdog TimerWatchdog Timer Control Register – WDTCR• Bits 7..5 - Res: Reserved BitsThese bits are reserved bits

41ATmega16(L)2466B–09/01Note: 1. Values are guidelines only. Actual values are TBD.The following code example shows one assembly and one C function fo

42ATmega16(L)2466B–09/01Interrupts This section describes the specifics of the interrupt handling as performed inATmega16. For a general explanation o

43ATmega16(L)2466B–09/01Note: 1. The Boot Reset Address is shown in Table 100 on page 252. For the BOOTRST fuse“1” means unprogrammed while “0” means

44ATmega16(L)2466B–09/01When the BOOTRST fuse is unprogrammed, the boot section size set to 2K bytes andthe IVSEL bit in the GICR register is set befo

45ATmega16(L)2466B–09/01Moving Interrupts Between Application and Boot SpaceThe General Interrupt Control Register controls the placement of the inter

46ATmega16(L)2466B–09/01Assembly Code ExampleMove_interrupts:; Enable change of interrupt vectorsldi r16, (1<<IVCE)out GICR, r16; Move interrupt

47ATmega16(L)2466B–09/01I/O PortsIntroduction All AVR ports have true Read-Modify-Write functionality when used as general digitalI/O ports. This mean

48ATmega16(L)2466B–09/01Ports as General Digital I/OThe ports are bi-directional I/O ports with optional internal pull-ups. Figure 23 shows afunctiona

49ATmega16(L)2466B–09/01enabled state is fully acceptable, as a high-impedant environment will not notice the dif-ference between a strong high driver

5ATmega16(L)2466B–09/01Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port B

50ATmega16(L)2466B–09/01ceeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a singlesignal transition on the pin will be

51ATmega16(L)2466B–09/01Note: 1. For the assembly program, two temporary registers are used to minimize the timefrom pull-ups are set on pins 0, 1, 6,

52ATmega16(L)2466B–09/01Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure26 shows how

53ATmega16(L)2466B–09/01The following subsections shortly describe the alternate functions for each port, andrelate the overriding signals to the alte

54ATmega16(L)2466B–09/01Alternate Functions of Port A Port A has an alternate function as analog input for the ADC as shown in Table 22. Ifsome Port A

55ATmega16(L)2466B–09/01Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 25.The alternate pin configuration i

56ATmega16(L)2466B–09/01• MOSI - Port B, Bit 5MOSI: SPI Master data output, slave data input for SPI channel. When the SPI isenabled as a slave, this

57ATmega16(L)2466B–09/01 Table 26. Overriding Signals for Alternate Functions in PB7..PB4SignalName PB7/SCK PB6/MISO PB5/MOSI PB4/SSPUOE SPE • MSTR S

58ATmega16(L)2466B–09/01Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 28. If the JTAG interface isenabled,

59ATmega16(L)2466B–09/01an open drain driver with slew-rate limitation. When this pin is used by the 2-wire SerialInterface, the pull-up can still be

6ATmega16(L)2466B–09/01AVR CPU CoreIntroduction This section discusses the AVR core architecture in general. The main function of theCPU core is to en

60ATmega16(L)2466B–09/01Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 31.The alternate pin configuration i

61ATmega16(L)2466B–09/01USART forces this pin to be an input, the pull-up can still be controlled by the PORTD0bit.Table 32 and Table 33 relate the al

62ATmega16(L)2466B–09/01Register Description for I/O PortsPort A Data Register – PORTAPort A Data Direction Register – DDRAPort A Input Pins Address –

63ATmega16(L)2466B–09/01Port C Input Pins Address – PINCPort D Data Register – PORTDPort D Data Direction Register – DDRDPort D Input Pins Address – P

64ATmega16(L)2466B–09/01External Interrupts The external interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, ifenabled, the inter

65ATmega16(L)2466B–09/01• Bit 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0The External Interrupt 0 is activated by the external pin

66ATmega16(L)2466B–09/01interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activityon the pin will cause an interru

67ATmega16(L)2466B–09/018-bit Timer/Counter0 with PWMTimer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. Themain features

68ATmega16(L)2466B–09/01The double buffered Output Compare Register (OCR0) is compared with theTimer/Counter value at all times. The result of the com

69ATmega16(L)2466B–09/01Depending of the mode of operation used, the counter is cleared, incremented, or dec-remented at each timer clock (clkT0). clk

7ATmega16(L)2466B–09/01an arithmetic operation, the Status Register is updated to reflect information about theresult of the operation.Program flow is

70ATmega16(L)2466B–09/01OCR0 compare register to either top or bottom of the counting sequence. The synchro-nization prevents the occurrence of odd-le

71ATmega16(L)2466B–09/01Figure 30. Compare Match Output Unit, SchematicThe general I/O port function is overridden by the output compare (OC0) from t

72ATmega16(L)2466B–09/01Normal Mode The simplest mode of operation is the normal mode (WGM01:0 = 0). In this mode thecounting direction is always up (

73ATmega16(L)2466B–09/01quency of fOC0 = fclk_I/O/2 when OCR0 is set to zero (0x00). The waveform frequency isdefined by the following equation:The N

74ATmega16(L)2466B–09/01pin is set as output. The PWM waveform is generated by setting (or clearing) the OC0register at the compare match between OCR0

75ATmega16(L)2466B–09/01Figure 33. Phase Correct PWM Mode, Timing DiagramThe Timer/Counter overflow flag (TOV0) is set each time the counter reaches

76ATmega16(L)2466B–09/01Figure 34. Timer/Counter Timing Diagram, no PrescalingFigure 35 shows the same timing data, but with the prescaler enabled.Fi

77ATmega16(L)2466B–09/01Figure 37 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode.Figure 37. Timer/Counter Timing Diagram, Clear Time

78ATmega16(L)2466B–09/01Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def-initions. However, the functionality and

79ATmega16(L)2466B–09/01Note: 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, thecompare match is ignored, but the set o

8ATmega16(L)2466B–09/01• Bit 7 - I: Global Interrupt EnableThe global interrupt enable bit must be set for the interrupts to be enabled. The individ-u

80ATmega16(L)2466B–09/01Output Compare Register – OCR0The Output Compare Register contains an 8-bit value that is continuously comparedwith the counte

81ATmega16(L)2466B–09/01Timer/Counter0 and Timer/Counter1 PrescalersTimer/Counter1 and Timer/Counter0 share the same prescaler module, but thetimer/co

82ATmega16(L)2466B–09/01than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Sincethe edge detector uses sampling

83ATmega16(L)2466B–09/0116-bit Timer/Counter1The 16-bit Timer/Counter unit allows accurate program execution timing (event man-agement), wave generati

84ATmega16(L)2466B–09/01Figure 40. 16-bit Timer/Counter Block Diagram(1)Note: 1. Refer to Figure 1 on page 2, Table 25 on page 55, and Table 31 on pa

85ATmega16(L)2466B–09/01(OC1A/B). See “Output Compare Units” on page 91. The compare match event will alsoset the compare match flag (OCF1A/B) which c

86ATmega16(L)2466B–09/01Accessing 16-bit RegistersThe TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVRCPU via the 8-bit d

87ATmega16(L)2466B–09/01The following code examples show how to do an atomic read of the TCNT1 register con-tents. Reading any of the OCR1A/B or ICR1

88ATmega16(L)2466B–09/01The following code examples show how to do an atomic write of the TCNT1 registercontents. Writing any of the OCR1A/B or ICR1 r

89ATmega16(L)2466B–09/01Figure 41. Counter Unit Block DiagramSignal description (internal signals):Count Increment or decrement TCNT1 by 1.Direction

9ATmega16(L)2466B–09/01Figure 4. AVR CPU General Purpose Working RegistersMost of the instructions operating on the Register file have direct access

90ATmega16(L)2466B–09/01Input Capture Unit The Timer/Counter incorporates an input capture unit that can capture external eventsand give them a time-s

91ATmega16(L)2466B–09/01For more information on how to access the 16-bit registers refer to “Accessing 16-bitRegisters” on page 86.Input Capture Trigg

92ATmega16(L)2466B–09/01cleared by software by writing a logical one to its I/O bit location. The waveform genera-tor uses the match signal to generat

93ATmega16(L)2466B–09/01I/O location is written by the CPU, the TEMP register will be updated by the value writ-ten. Then when the low byte (OCR1xL) i

94ATmega16(L)2466B–09/01Figure 44. Compare Match Output Unit, SchematicThe general I/O port function is overridden by the output compare (OC1x) from

95ATmega16(L)2466B–09/01Normal Mode The simplest mode of operation is the normal mode (WGM13:0 = 0). In this mode thecounting direction is always up (

96ATmega16(L)2466B–09/01this feature is not desirable. An alternative will then be to use the fast PWM mode usingOCR1A for defining TOP (WGM13:0 = 15)

97ATmega16(L)2466B–09/01Figure 46. Fast PWM Mode, Timing DiagramThe Timer/Counter overflow flag (TOV1) is set each time the counter reaches TOP. Inad

98ATmega16(L)2466B–09/01seting (or clearing) the OC1x register at the compare match between OCR1x andTCNT1, and clearing (or setting) the OC1x registe

99ATmega16(L)2466B–09/01Figure 47. Phase Correct PWM Mode, Timing DiagramThe Timer/Counter overflow flag (TOV1) is set each time the counter reaches