Rainbow-electronics ATtiny43U User Manual

Features• High Performance, Low Power AVR® 8-Bit Microcontroller• Advanced RISC Architecture– 120 Powerful Instructions – Most Single Clock Cycle Exec

108048B–AVR–03/09ATtiny43U4.5 General Purpose Register FileThe Register File is optimized for the AVR Enhanced RISC instruction set. In order to achie

1008048B–AVR–03/09ATtiny43U14. USI – Universal Serial Interface14.1 Features• Two-wire Synchronous Data Transfer (Master or Slave)• Three-wire Synchro

1018048B–AVR–03/09output to the opposite clock edge of the data input sampling. The serial input is always sampledfrom the Data Input (DI) pin indepen

1028048B–AVR–03/09ATtiny43UFigure 14-3. Three-wire Mode, Timing DiagramThe three-wire mode timing is shown in Figure 14-3 At the top of the figure is

1038048B–AVR–03/09<continued>SPITransfer_loop:out USICR,r17in r16, USISRsbrs r16, USIOIFrjmp SPITransfer_loopin r16,USIDRretThe code is size opt

1048048B–AVR–03/09ATtiny43U14.3.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave:init:ldi r16,(1

1058048B–AVR–03/09Figure 14-4. Two-wire Mode Operation, Simplified DiagramThe data direction is not given by the physical layer. A protocol, like the

1068048B–AVR–03/09ATtiny43Udetects the start condition and sets the USISIF Flag. The flag can generate an interrupt if necessary. 2. In addition, the

1078048B–AVR–03/0914.4 Alternative USI UsageThe flexible design of the USI allows it to be used for other tasks when serial communication isnot needed

1088048B–AVR–03/09ATtiny43Unally, and data input sampled, even when outputs are disabled. The relations betweenUSIWM1..0 and the USI operation is summ

1098048B–AVR–03/09Table 14-2 shows the relationship between the USICS[1:0] and USICLK setting and clocksource used for the USI Data Register and the 4

118048B–AVR–03/09Figure 4-3. The X-, Y-, and Z-registersIn the different addressing modes these address registers have functions as fixed displacement

1108048B–AVR–03/09ATtiny43UIf USISIE bit in USICR and the Global Interrupt Enable Flag are set, an interrupt will be gener-ated when this flag is set.

1118048B–AVR–03/09Note that even when no wire mode is selected (USIWM[1:0] = 0) both the external data input(DI/SDA) and the external clock input (USC

1128048B–AVR–03/09ATtiny43U15. Analog ComparatorThe Analog Comparator compares the input values on the positive pin AIN0 and negative pinAIN1. When th

1138048B–AVR–03/0915.2 Register Description15.2.1 ADCSRB – ADC Control and Status Register B• Bit 6 – ACME: Analog Comparator Multiplexer EnableWhen t

1148048B–AVR–03/09ATtiny43U• Bit 4 – ACI: Analog Comparator Interrupt FlagThis bit is set by hardware when a comparator output event triggers the inte

1158048B–AVR–03/0916. Analog to Digital Converter16.1 Features• 10-bit Resolution• 1 LSB Integral Non-linearity• ± 2 LSB Absolute Accuracy• 13µs Conve

1168048B–AVR–03/09ATtiny43UThe ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC isheld at a constant level durin

1178048B–AVR–03/09bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal,the ADC prescaler is reset and a

1188048B–AVR–03/09ATtiny43UFigure 16-3. ADC PrescalerWhen initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversionstarts

1198048B–AVR–03/09Figure 16-5. ADC Timing Diagram, Single ConversionWhen Auto Triggering is used, the prescaler is reset when the trigger event occurs

128048B–AVR–03/09ATtiny43U4.6.1 SPH and SPL — Stack Pointer Register4.7 Instruction Execution TimingThis section describes the general access timing c

1208048B–AVR–03/09ATtiny43UFigure 16-7. ADC Timing Diagram, Free Running ConversionFor a summary of conversion times, see Table 16-1.16.6 Changing Cha

1218048B–AVR–03/09If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If theADMUX Register is changed in this period,

1228048B–AVR–03/09ATtiny43Uconversion completes. The CPU will remain in active mode until a new sleep command is executed.Note that the ADC will not a

1238048B–AVR–03/09• Keep analog tracks well away from high-speed switching digital tracks.• Use the ADC noise canceler function to reduce induced nois

1248048B–AVR–03/09ATtiny43U• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF)

1258048B–AVR–03/09• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) f

1268048B–AVR–03/09ATtiny43Uperature sensor is enabled, the ADC converter can be used in single conversion mode tomeasure the voltage over the temperat

1278048B–AVR–03/09• Bits 2:0 – MUX[2:0]: Analog Channel Selection BitsThe value of these bits selects which analog input is connected to the ADC, as s

1288048B–AVR–03/09ATtiny43U• Bit 4 – ADIF: ADC Interrupt FlagThis bit is set when an ADC conversion completes and the data registers are updated. The

1298048B–AVR–03/09When an ADC conversion is complete, the result is found in these two registers.When ADCL is read, the ADC Data Register is not updat

138048B–AVR–03/094.8 Reset and Interrupt HandlingThe AVR provides several different interrupt sources. These interrupts and the separate ResetVector e

1308048B–AVR–03/09ATtiny43U16.13.5 DIDR0 – Digital Input Disable Register 0• Bits 3:0 – ADC[3:0]D: ADC[3:0] Digital Input DisableWhen this bit is writ

1318048B–AVR–03/0917. debugWIRE On-chip Debug System17.1 Features• Complete Program Flow Control• Emulates All On-chip Functions, Both Digital and Ana

1328048B–AVR–03/09ATtiny43UWhen designing a system where debugWIRE will be used, the following observations must bemade for correct operation:• Pull-U

1338048B–AVR–03/0918. Self-Programming the FlashThe device provides a Self-Programming mechanism for downloading and uploading programcode by the MCU

1348048B–AVR–03/09ATtiny43U18.3 Performing a Page WriteTo execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR andexecu

1358048B–AVR–03/0918.5 EEPROM Write Prevents Writing to SPMCSRNote that an EEPROM write operation will block all software programming to Flash. Readin

1368048B–AVR–03/09ATtiny43UTo read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 andrepeat the procedure above. If

1378048B–AVR–03/0918.7 Preventing Flash CorruptionDuring periods of low VCC, the Flash program can be corrupted because the supply voltage istoo low f

1388048B–AVR–03/09ATtiny43U• Bit 3 – RFLB: Read Fuse and Lock BitsAn LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Re

1398048B–AVR–03/0919. Memory ProgrammingThis section describes the different methods for Programming the ATtiny43U memories.19.1 Program And Data Memo

148048B–AVR–03/09ATtiny43UWhen using the SEI instruction to enable interrupts, the instruction following SEI will be exe-cuted before any pending inte

1408048B–AVR–03/09ATtiny43U19.2 Fuse BytesThe ATtiny43U has three Fuse bytes. Table 19-3, Table 19-4 and Table 19-5 briefly describe thefunctionality

1418048B–AVR–03/09Notes: 1. See “Power Management and Sleep Modes” on page 31 for details.2. The default value of SUT1..0 results in maximum start-up

1428048B–AVR–03/09ATtiny43U19.3.1 Signature BytesAll Atmel microcontrollers have a three-byte signature code which identifies the device. Thiscode can

1438048B–AVR–03/09Figure 19-1. Parallel ProgrammingTable 19-10. Pin Name Mapping Signal Name in Programming ModePin Name I/O FunctionWRPA0 I Write Pul

1448048B–AVR–03/09ATtiny43UThe XA1/XA0 pins determine the action executed when the CLKI pin is given a positive pulse.The bit coding is shown in Table

1458048B–AVR–03/09• The command needs only be loaded once when writing or reading multiple memory locations.• Skip writing the data value 0xFF, that i

1468048B–AVR–03/09ATtiny43U1. Set BS1 to “1”. This selects high data byte.2. Set XA1, XA0 to “01”. This enables data loading.3. Set DATA = Data high b

1478048B–AVR–03/09Figure 19-2. Addressing the Flash Which is Organized in Pages(1)Note: 1. PCPAGE and PCWORD are listed in Table 19-8 on page 142.Figu

1488048B–AVR–03/09ATtiny43U5. E: No action.K: Repeat 3 through 5 until the entire buffer is filled.L: Program EEPROM page1. Set BS1 to “0”.2. Give WR

1498048B–AVR–03/0919.6.8 Programming the Fuse Low BitsThe algorithm for programming the Fuse Low bits is as follows (refer to “Programming the Flash”o

158048B–AVR–03/095. Memories5.1 OverviewThis section describes the different memories in ATtiny43U. The AVR architecture has two mainmemory spaces, th

1508048B–AVR–03/09ATtiny43U1. A: Load Command “0010 0000”.2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed (LB1

1518048B–AVR–03/091. A: Load Command “0000 1000”.2. B: Load Address Low Byte, 0x00.3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be r

1528048B–AVR–03/09ATtiny43U19.7.1 Serial Programming AlgorithmWhen writing serial data to the ATtiny43U, data is clocked on the rising edge of SCK.Whe

1538048B–AVR–03/098. Power-off sequence (if needed):Set RESET to “1”.Tur n VCC power off.19.7.2 Serial Programming Instruction setTable 19-16 on page

1548048B–AVR–03/09ATtiny43UNotes: 1. Not all instructions are applicable for all parts.2. a = address3. Bits are programmed ‘0’, unprogrammed ‘1’.4. T

1558048B–AVR–03/0920. Electrical Characteristics20.1 Absolute Maximum Ratings*20.2 DC CharacteristicsNote: All DC Characteristics contained in this da

1568048B–AVR–03/09ATtiny43UNotes: 1. “Max” means the highest value where the pin is guaranteed to be read as low.2. Not tested in production.3. “Min”

1578048B–AVR–03/0920.4 Clock Characteristics20.4.1 Calibrated Internal Oscillator AccuracyIt is possible to manually calibrate the internal oscillator

1588048B–AVR–03/09ATtiny43U20.5 System and Reset CharacteristicsNote: 1. The Power-on Reset will not work unless the supply voltage has been below VPO

1598048B–AVR–03/0920.7 Boost Converter CharacteristicsTable 20-7. Characteristics of Boost Converter. T = -20°C ... +85°C, unless otherwise notedSymbo

168048B–AVR–03/09ATtiny43UThe direct addressing reaches the entire data space.The Indirect with Displacement mode reaches 63 address locations from th

1608048B–AVR–03/09ATtiny43U20.8 ADC Characteristics – Preliminary DataTable 20-8. ADC Characteristics, Single_Ended Conversion, TA = -40°C - 85°C, Boo

1618048B–AVR–03/09Table 20-9. ADC Characteristics, Single_Ended Conversion, TA = -40°C - 85°C, Boost Converter Enabled.Symbol Parameter Condition Min

1628048B–AVR–03/09ATtiny43U20.9 Parallel Programming CharacteristicsFigure 20-3. Parallel Programming Timing, Including some General Timing Requiremen

1638048B–AVR–03/09Figure 20-5. Parallel Programming Timing, Loading Sequence with Timing RequirementsNote: 1. tWLRH is valid for the Write Flash, Wri

1648048B–AVR–03/09ATtiny43U20.10 Serial Programming CharacteristicsFigure 20-6. Serial Programming TimingFigure 20-7. Serial Programming WaveformsTabl

1658048B–AVR–03/0921. Typical Characteristics – TBDThe data contained in this section is largely based on simulations and characterization of similard

1668048B–AVR–03/09ATtiny43UFigure 21-2. Boost Converter Efficiency vs. Load Current and VBAT VoltageFigure 21-3. Input Voltage Required to Maintain Re

1678048B–AVR–03/0922. Register SummaryAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page0x3F (0x5F) SREG I T H S V N Z C Page 80x3E (0x

1688048B–AVR–03/09ATtiny43UNote: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory ad

1698048B–AVR–03/0923. Instruction Set SummaryMnemonics Operands Description Operation Flags #ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add two

178048B–AVR–03/09the EEPROM Control Register. For a detailed description of Serial data downloading to theEEPROM, see “Serial Programming” on page 151

1708048B–AVR–03/09ATtiny43UROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=

1718048B–AVR–03/0924. Ordering InformationNotes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for d

1728048B–AVR–03/09ATtiny43U25. Packaging Information25.1 20M1 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 20M1, 20-pad, 4 x 4 x 0

1738048B–AVR–03/0925.2 20S2

1748048B–AVR–03/09ATtiny43U26. ErrataThe revision letter in this section refers to the revision of the ATtiny43U device.26.1 ATtiny43U26.1.1 Rev. C•In

1758048B–AVR–03/0927. Datasheet Revision History27.1 Rev. 8048B-03/0927.2 Rev. 8048A-02/091. Updated Data retention bullet in “Features” on page 1.1.

1768048B–AVR–03/09ATtiny43U

i8048B–AVR–03/09Table of ContentsFeatures... 11 Pin

ii8048B–AVR–03/09ATtiny43U7.1 Sleep Modes ...317.2 So

iii8048B–AVR–03/0911.4 Register Description ...7812 8-bit Timer/

188048B–AVR–03/09ATtiny43Udata that is stored must be considered as lost. While the device is busy with programming, it isnot possible to do any other

iv8048B–AVR–03/09ATtiny43U16.10 ADC Accuracy Definitions ...12316.11 ADC Co

v8048B–AVR–03/0920.6 External Interrupt Characteristics ...15820.7 Boost Converter Cha

8048B–AVR–03/09Headquarters InternationalAtmel Corporation2325 Orchard ParkwaySan Jose, CA 95131USATel: 1(408) 441-0311Fax: 1(408) 487-2600Atmel AsiaU

198048B–AVR–03/09The next code examples show assembly and C functions for reading the EEPROM. The exam-ples assume that interrupts are controlled so t

28048B–AVR–03/09ATtiny43U1. Pin ConfigurationsFigure 1-1. Pinout of ATtiny43U1.1 Pin Descriptions1.1.1 VCCSupply voltage.1.1.2 GNDGround.1.1.3 Port A

208048B–AVR–03/09ATtiny43U5.5 I/O MemoryThe I/O space definition of the ATtiny43U is shown in “Register Summary” on page 167.All I/Os and peripherals

218048B–AVR–03/095.6.2 EEDR – EEPROM Data Register• Bits 7:0 – EEDR[7:0]: EEPROM DataFor the EEPROM write operation the EEDR Register contains the dat

228048B–AVR–03/09ATtiny43UWhen EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at theselected address. If EEMPE is zero, s

238048B–AVR–03/096. System Clock and Clock Options6.1 Clock Systems and their DistributionFigure 6-1 presents the principal clock systems in the AVR a

248048B–AVR–03/09ATtiny43U6.1.4 ADC Clock – clkADCThe ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocksin orde

258048B–AVR–03/09When this clock source is selected, start-up times are determined by SUT Fuses as shown inTable 6-3.When applying an external clock,

268048B–AVR–03/09ATtiny43UWhen this Oscillator is selected, start-up times are determined by the SUT Fuses as shown inTable 6-5 below.Note: 1. If the

278048B–AVR–03/096.2.5 Clock Startup SequenceAny clock source needs a sufficient VCC to start oscillating and a minimum number of oscillatingcycles be

288048B–AVR–03/09ATtiny43Uit takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this inter-val, two active clock edges

298048B–AVR–03/09cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting theCLKPCE bit within this time-out peri

38048B–AVR–03/09capability except PA7 which has the RESET capability. To use pin PA7 as an I/O pin, instead ofRESET pin, program (‘0’) RSTDISBL fuse.

308048B–AVR–03/09ATtiny43UInterrupts must be disabled when changing prescaler setting to make sure the write procedure isnot interrupted.

318048B–AVR–03/097. Power Management and Sleep ModesSleep modes enable the application to shut down unused modules in the MCU, thereby savingpower. Th

328048B–AVR–03/09ATtiny43UIdle mode enables the MCU to wake up from external triggered interrupts as well as internalones like the Timer Overflow. If

338048B–AVR–03/09peripheral should in most cases be disabled before stopping the clock. Waking up a module,which is done by clearing the bit in PRR, p

348048B–AVR–03/09ATtiny43U7.4.6 Port PinsWhen entering a sleep mode, all port pins should be configured to use minimum power. Themost important thing

358048B–AVR–03/09• Bit 2 – BODSE: BOD Sleep EnableBODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disableis contr

368048B–AVR–03/09ATtiny43U8. Power Supply and On-Chip Boost ConverterIn order to work properly microcontrollers typically require a supply voltage lev

378048B–AVR–03/09Figure 8-2. Typical Connection of Boost Converter.When the boost converter is not connected the microcontroller can be powered direct

388048B–AVR–03/09ATtiny43U8.2.1 Stop ModeThe boost converter enters Stop Mode (see Figure 8-3 on page 37 for modes of operation) wheninput voltage ,VB

398048B–AVR–03/09Figure 8-4. Input and Output Voltages of Boost Converter.When input voltage VBAT falls below VSTOP the converter enters Stop Mode and

48048B–AVR–03/09ATtiny43U2. OverviewThe ATtiny43U is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISCarchitecture. By executing p

408048B–AVR–03/09ATtiny43UAs current consumption goes below IMS (see Figure 8-5) the converter goes from Active Regu-lated Mode to Active Low Current

418048B–AVR–03/09Figure 8-6. Typical Output Voltage of Boost Converter in Active Regulated Mode.8.3.2 Active Low Current ModeThe boost converter enter

428048B–AVR–03/09ATtiny43UFigure 8-7. Typical Output Voltage of Boost Converter at Constant Full Duty Cycle.See section “Software Control of Boost Con

438048B–AVR–03/09To stop the boost converter, follow the below procedure:1. Write 110x xxxx to the Power Reduction Register, PRR2. Within 3 clock cyc

448048B–AVR–03/09ATtiny43U... where D is the duty cycle and TS the switching period of the boost converter. See “Boost Con-verter Characteristics” on

458048B–AVR–03/09Too high resistor values may lead to Start Mode failures. See “Boost Converter Component Val-ues” on page 45 for component recommenda

468048B–AVR–03/09ATtiny43U8.7 Typical ApplicationsA typical use of the boost converter is illustrated in Figure 8-2 on page 37. Components can beoptim

478048B–AVR–03/09boost converter, connect pins VBAT and LSW to ground and provide the device with supplydirectly to the VCC pin.8.11 Register Descript

488048B–AVR–03/09ATtiny43U9. System Control and Reset9.1 Resetting the AVRDuring reset, all I/O Registers are set to their initial values, and the pro

498048B–AVR–03/099.2 Reset SourcesThe ATtiny43U has four sources of reset:• Power-on Reset. The MCU is reset when the supply voltage is below the Powe

58048B–AVR–03/09architecture is more code efficient while achieving throughputs up to ten times faster than con-ventional CISC microcontrollers.The AT

508048B–AVR–03/09ATtiny43U9.4 External ResetAn External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longerthan the min

518048B–AVR–03/09It is recommended to disable the BOD when using the integrated boost converter. See “PowerSupply and On-Chip Boost Converter” on page

528048B–AVR–03/09ATtiny43Uclock cycle periods can be selected to determine the reset period. If the reset period expireswithout another Watchdog Reset

538048B–AVR–03/099.8.1.2 Safety Level 2In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. Atimed sequence is

548048B–AVR–03/09ATtiny43U9.9 Register Description9.9.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source

558048B–AVR–03/09the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set aftereach interrupt.• Bit 4 – WDCE: Watchdog C

568048B–AVR–03/09ATtiny43U• Bits 5, 2:0 – WDP[3:0]: Watchdog Timer Prescaler 3, 2, 1, and 0The WDP[3:0] bits determine the Watchdog Timer prescaling w

578048B–AVR–03/0910. InterruptsThis section describes the specifics of the interrupt handling as performed in ATtiny43U. For ageneral explanation of t

588048B–AVR–03/09ATtiny43U0x0008 rjmp TIM0_COMPA ; Timer0 Compare A Handler0x0009 rjmp TIM0_COMPB ; Timer0 Compare B Handler0x000A rjmp TIM0_OVF ; Tim

598048B–AVR–03/09Figure 10-1. Timing of pin change interrupts10.3 Register Description10.3.1 MCUCR – MCU Control RegisterThe External Interrupt Contro

68048B–AVR–03/09ATtiny43U3. About3.1 ResourcesA comprehensive set of development tools, drivers and application notes, and datasheets areavailable for

608048B–AVR–03/09ATtiny43UIf low level interrupt is selected, the low level must be held until the completion of the currentlyexecuting instruction to

618048B–AVR–03/09• Bit 6 – INTF0: External Interrupt Flag 0When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes s

628048B–AVR–03/09ATtiny43U11. I/O Ports11.1 IntroductionAll AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports

638048B–AVR–03/0911.2 Ports as General Digital I/OThe ports are bi-directional I/O ports with optional internal pull-ups. Figure 11-2 shows a func-tio

648048B–AVR–03/09ATtiny43Ube configured as an output pin. The port pins are tri-stated when reset condition becomes active,even if no clocks are runni

658048B–AVR–03/09Figure 11-3. Synchronization when Reading an Externally Applied Pin valueConsider the clock period starting shortly after the first f

668048B–AVR–03/09ATtiny43UThe following code example shows how to set port A pins 0 and 1 high, 2 and 3 low, and definethe port pins from 4 to 5 as in

678048B–AVR–03/09is not enabled, the corresponding External Interrupt Flag will be set when resuming from theabove mentioned Sleep mode, as the clampi

688048B–AVR–03/09ATtiny43UFigure 11-5. Alternate Port Functions(1)Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same por

698048B–AVR–03/09Table 11-2 summarizes the function of the overriding signals. The pin and port indexes from Fig-ure 11-5 on page 68 are not shown in

78048B–AVR–03/094. AVR CPU Core4.1 IntroductionThis section discusses the AVR core architecture in general. The main function of the CPU coreis to ens

708048B–AVR–03/09ATtiny43U11.3.1 Alternate Functions of Port A The Port A pins with alternate function are shown in Table 11-3 on page 70.• Port A, Bi

718048B–AVR–03/09• Port A, Bit 4 – AIN0/PCINT4AIN0: Analog Comparator Positive Input. Configure the port pin as input with the internal pull-upswitche

728048B–AVR–03/09ATtiny43UTable 11-4 on page 72 to Table 11-6 on page 73 relate the alternate functions of Port A to theoverriding signals shown in Fi

738048B–AVR–03/09Table 11-7. Overriding Signals for Alternate Functions in PA1..PA0Table 11-6. Overriding Signals for Alternate Functions in PA3..PA2S

748048B–AVR–03/09ATtiny43U11.3.2 Alternate Functions of Port BThe Port B pins with alternate function are shown in Table 11-8 on page 74.• Port B, Bit

758048B–AVR–03/09PCINT10: Pin Change Interrupt source 10. The PB2 pin can serve as an external interruptsource for pin change interrupt 1.• Port B, Bi

768048B–AVR–03/09ATtiny43UTable 11-9 on page 76 to Table 11-12 on page 77 relate the alternate functions of Port B to theoverriding signals shown in F

778048B–AVR–03/09Table 11-11. Overriding Signals for Alternate Functions in PB3..PB2 SignalName PB3/T1/CLKO/PCINT9 PB2/OC0B/PCINT8PUOE CKOUT 0PUOV 0 0

788048B–AVR–03/09ATtiny43U11.4 Register Description11.4.1 MCUCR – MCU Control Register• Bit 6 – PUD: Pull-up DisableWhen this bit is written to one, t

798048B–AVR–03/0912. 8-bit Timer/Counter with PWM (Timer/Counter0 and Timer/Counter1)12.1 Features• Two Independent Output Compare Units• Double Buffe

88048B–AVR–03/09ATtiny43UThe fast-access Register File contains 32 x 8-bit general purpose working registers with a singleclock cycle access time. Thi

808048B–AVR–03/09ATtiny43U12.2.1 RegistersThe Timer/Counter (TCNTn) and Output Compare Registers (OCRnA and OCRnB) are 8-bitregisters. Interrupt reque

818048B–AVR–03/09Figure 12-2. Counter Unit Block DiagramSignal description (internal signals):count Increment or decrement TCNTn by 1.direction Select

828048B–AVR–03/09ATtiny43UFigure 12-3. Output Compare Unit, Block DiagramThe OCRnx Registers are double buffered when using any of the Pulse Width Mod

838048B–AVR–03/09generation. Similarly, do not write the TCNTn value equal to BOTTOM when the counter isdown-counting.The setup of the OCnx should be

848048B–AVR–03/09ATtiny43UThe design of the Output Compare pin logic allows initialization of the OCnx state before the out-put is enabled. Note that

858048B–AVR–03/09The timing diagram for the CTC mode is shown in Figure 12-5 on page 85. The counter value(TCNTn) increases until a Compare Match occu

868048B–AVR–03/09ATtiny43Ufor power regulation, rectification, and DAC applications. High frequency allows physically smallsized external components (

878048B–AVR–03/09in a constantly high or low output (depending on the polarity of the output set by the COMnA1:0bits.)A frequency (with 50% duty cycle

888048B–AVR–03/09ATtiny43UThe Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. TheInterrupt Flag can be used to generat

898048B–AVR–03/09Figure 12-8. Timer/Counter Timing Diagram, no PrescalingFigure 12-9 on page 89 shows the same timing data, but with the prescaler ena

98048B–AVR–03/094.4.1 SREG - AVR Status Register• Bit 7 – I: Global Interrupt EnableThe Global Interrupt Enable bit must be set for the interrupts to

908048B–AVR–03/09ATtiny43UFigure 12-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-caler (fclk_I/O/8)12.9 Register Des

918048B–AVR–03/09Table 12-3 on page 91 shows the COMnA[1:0] bit functionality when the WGMn[1:0] bits are setto fast PWM mode.Note: 1. A special case

928048B–AVR–03/09ATtiny43UTable 12-6 on page 92 shows the COMnB[1:0] bit functionality when the WGMn[2:0] bits are setto fast PWM mode.Note: 1. A spec

938048B–AVR–03/09Note: 1. MAX = 0xFF, BOTTOM = 0x0012.9.3 TCCR0B – Timer/Counter Control Register B12.9.4 TCCR1B – Timer/Counter Control Register B• B

948048B–AVR–03/09ATtiny43UHowever, for ensuring compatibility with future devices, this bit must be set to zero whenTCCR0B is written when operating i

958048B–AVR–03/0912.9.6 TCNT1 – Timer/Counter RegisterThe Timer/Counter Register gives direct access, both for read and write operations, to theTimer/

968048B–AVR–03/09ATtiny43U12.9.12 TIMSK1 – Timer/Counter 1 Interrupt Mask Register• Bits 7:3 – Res: Reserved BitsThese bits are reserved and will alwa

978048B–AVR–03/09• Bit 1 – OCFnA: Output Compare Flag n AThe OCFnA bit is set when a Compare Match occurs between the Timer/Countern and the datain OC

988048B–AVR–03/09ATtiny43U13. Timer/Counter PrescalerTimer/Counter0 and Timer/Counter1 share the same prescaler module, but the Timer/Counterscan have

998048B–AVR–03/09tem clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector usessampling, the maximum frequency