Rainbow-electronics DS1993 User Manual Page 7

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DS1992/DS1993/DS1994
7 of 23 102199
MEMORY
The memory map in Figure 4 shows a 32–byte page called the scratchpad and additional 32–byte pages
called memory. The DS1992 contains pages 0 though 3 which make up the 1024–bit SRAM. The
DS1993 and DS1994 contain pages 0 through 15 which make up the 4096–bit SRAM. The DS1994 also
contains page 16 which has only 30 bytes that contain the timekeeping registers.
The scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written to
the scratchpad where it can be read back. After the data has been verified, a copy scratchpad command
will transfer the data to memory. This process ensures data integrity when modifying the memory.
TIMEKEEPING (DS1994)
A 32.768 kHz crystal oscillator is used as the time base for the timekeeping functions. The oscillator can
be turned on or off by an enable bit in the control register. The oscillator must be on for the real time
clock, interval timer and cycle counter to function.
The timekeeping functions are double buffered. This feature allows the master to read time or count
without the data changing while it is being read. To accomplish this, a snapshot of the counter data is
transferred to holding registers which the user accesses. This occurs after the eighth bit of the Read
Memory Function command.
Real-Time Clock
The real-time clock is a 5-byte binary counter. It is incremented 256 times per second. The least
significant byte is a count of fractional seconds. The upper four bytes are a count of seconds. The real-
time clock can accumulate 136 years of seconds before rolling over. Time/date is represented by the
number of seconds since a reference point which is determined by the user. For example, 12:00 A.M.,
January 1, 1970 could be a reference point.
Interval Timer
The interval timer is a 5-byte binary counter. When enabled, it is incremented 256 times per second. The
least significant byte is a count of fractional seconds. The interval timer can accumulate 136 years of
seconds before rolling over. The interval timer has two modes of operation which are selected by the
AUTO/MAN bit in the control register. In the auto mode, the interval timer will begin counting after the
data line has been high for a period of time determined by the DSEL bit in the control register. Similarly,
the interval timer will stop counting after the data line has been low for a period of time determined by
the DSEL bit. In the manual mode, time accumulation is controlled by the STOP/START bit in the
control register.
NOTE: For auto mode operation, the high level on the data line must be greater than or equal to 2.1 volts.
Cycle Counter
The cycle counter is a 4-byte binary counter. It increments after the falling edge of the data line if the
appropriate data line timing has been met. This timing is selected by the DSEL bit in the control register.
(See Status/Controlsection).
NOTE: For cycle counter operation, the high level on the data line must be greater than or equal to 2.1
volts.
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