Rainbow-electronics T89C51CC02 User Manual

Rev.A- May 17, 2001 1PreliminaryT89C51CC028-bit MCU with CAN controller and Flash1. DescriptionPart of the CANaryTMfamily of microcontrollersdedicated

10 Rev.A - May 17, 2001PreliminaryT89C51CC02Table 7. PCA SFRsTable 8. Interrupt SFRsTable 9. ADC SFRsTable 10. CAN SFRsMnemonic Add Name 7 6 5 4 3 2 1

100 Rev.A - May 17, 2001PreliminaryT89C51CC02CANSTMPH (S:AFh Read Only)CAN Stamp Timer HighNo default value after resetFigure 100. CANSTMPH RegisterCA

Rev.A - May 17, 2001 101PreliminaryT89C51CC02CANTTCL (S:A4h Read Only)CAN TTC Timer LowReset Value: 0000 0000bFigure 103. CANTTCL Register7 6 5 4 3 2

102 Rev.A - May 17, 2001PreliminaryT89C51CC0216. Programmable Counter Array PCA16.1. IntroductionThe PCA provides more timing capabilities with less C

Rev.A - May 17, 2001 103PreliminaryT89C51CC02Figure 104. PCA Timer/CounterCIDLCPS1 CPS0 ECFItCH CL16 bit up/down counterTo PCAmodulesFPca/6FPca / 2T0

104 Rev.A - May 17, 2001PreliminaryT89C51CC0216.2. PCA InterruptFigure 105. PCA Timer InterruptsCF CRCCON0xD8CCF1 CCF0Module 1Module 0ECFPCA Timer/Cou

Rev.A - May 17, 2001 105PreliminaryT89C51CC0216.3. PCA Capture ModeTo use one of the PCA modules in capture mode either one or both of the CCAPM bits

106 Rev.A - May 17, 2001PreliminaryT89C51CC0216.4. 16-bit Software Timer ModeThe PCA modules can be used as software timers by setting both the ECOM a

Rev.A - May 17, 2001 107PreliminaryT89C51CC0216.5. High Speed Output ModeIn this mode the CEX output (on port 1) associated with the PCA module will t

108 Rev.A - May 17, 2001PreliminaryT89C51CC0216.6. Pulse Width Modulator ModeAll the PCA modules can be used as PWM outputs. The output frequency depe

Rev.A - May 17, 2001 109PreliminaryT89C51CC0216.7. PCA RegistersCMOD (S:D8h)PCA Counter Mode RegisterReset Value = 00XX X000bFigure 110. CMOD Register

Rev.A - May 17, 2001 11PreliminaryT89C51CC02Table 11. Other SFRsCANTIML ACh CAN Timer lowCANTIM7CANTIM6CANTIM5CANTIM4CANTIM3CANTIM2CANTIM1CANTIM0CANST

110 Rev.A - May 17, 2001PreliminaryT89C51CC02CCON (S:D8h)PCA Counter Control RegisterReset Value = 00xx xx00bFigure 111. CCON Register7 6 5 4 3 2 1 0C

Rev.A - May 17, 2001 111PreliminaryT89C51CC02CCAP0H (S:FAh)CCAP1H (S:FBh )PCA High Byte Compare/Capture Module n Register (n=0..1)Reset Value = 0000 0

112 Rev.A - May 17, 2001PreliminaryT89C51CC02CCAPM0 (S:DAh)CCAPM1 (S:DBh)PCA Compare/Capture Module n Mode registers (n=0..1)Reset Value = X000 0000bF

Rev.A - May 17, 2001 113PreliminaryT89C51CC02CH (S:F9h)PCA Counter Register High valueReset Value = 0000 00000bFigure 115. CH RegisterCL (S:E9h)PCA co

114 Rev.A - May 17, 2001PreliminaryT89C51CC0217. Analog-to-Digital Converter (ADC)17.1. IntroductionThis section describes the on-chip 10 bit analog-t

Rev.A - May 17, 2001 115PreliminaryT89C51CC02Figure 117. ADC DescriptionFigure 118 shows the timing diagram of a complete conversion. For simplicity,

116 Rev.A - May 17, 2001PreliminaryT89C51CC0217.4. ADC Converter OperationA start of single A/D conversion is triggered by setting bit ADSST (ADCON.3)

Rev.A - May 17, 2001 117PreliminaryT89C51CC0217.6. Clock SelectionThe maximum clock frequency for ADC is 700KHz. A prescaler is featured (ADCCLK) to g

118 Rev.A - May 17, 2001PreliminaryT89C51CC0217.8. IT ADC managementAn interrupt end-of-conversion will occurs when the bit ADEOC is actived and the b

Rev.A - May 17, 2001 119PreliminaryT89C51CC0217.9. RegistersADCF (S:F6h)ADC ConfigurationReset Value=0000 0000bFigure 121. ADCF RegisterADCON (S:F3h)A

12 Rev.A - May 17, 2001PreliminaryT89C51CC02Table 12. SFR’s mappingNote:2. These registers are bit-addressable.Sixteen addresses in the SFR space are

120 Rev.A - May 17, 2001PreliminaryT89C51CC02ADCLK (S:F2h)ADC Clock PrescalerReset Value: XXX0 0000bFigure 123. ADCLK RegisterADDH (S:F5h Read Only)AD

Rev.A - May 17, 2001 121PreliminaryT89C51CC0218. Interrupt System18.1. IntroductionThe CAN Controller has a total of 10 interrupt vectors: two externa

122 Rev.A - May 17, 2001PreliminaryT89C51CC02Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the

Rev.A - May 17, 2001 123PreliminaryT89C51CC0218.2. RegistersIEN0 (S:A8h)Interrupt Enable RegisterReset Value: 0000 0000bbit addressableFigure 127. IE0

124 Rev.A - May 17, 2001PreliminaryT89C51CC02IEN1 (S:E8h)Interrupt Enable RegisterReset Value: xxxx x000bbit addressableFigure 128. IE0 Register7 6 5

Rev.A - May 17, 2001 125PreliminaryT89C51CC02IPL0 (S:B8h)Interrupt Enable RegisterReset Value: X000 0000bbit addressableFigure 129. IPL0 Register7 6 5

126 Rev.A - May 17, 2001PreliminaryT89C51CC02IPL1 (S:F8h)Interrupt Priority Low Register 1Reset Value: XXXX X000bbit addressableFigure 130. IPL1 Regis

Rev.A - May 17, 2001 127PreliminaryT89C51CC02IPH0 (B7h)Interrupt High Priority RegisterReset Value: X000 0000bFigure 131. IPL0 Register7 6 5 4 3 2 1 0

128 Rev.A - May 17, 2001PreliminaryT89C51CC02IPH1 (S:F7h)Interrupt high priority Register 1Reset Value = XXXX X000bFigure 132. IPH1 Register7 6 5 4 3

Rev.A - May 17, 2001 129PreliminaryT89C51CC0219. Electrical Characteristics19.1. Absolute Maximum Ratings(1)Ambiant Temperature Under Bias:I = industr

Rev.A - May 17, 2001 13PreliminaryT89C51CC026. Clock6.1. IntroductionThe T89C51CC02 core needs only 6 clock periods per machine cycle. This feature, c

130 Rev.A - May 17, 2001PreliminaryT89C51CC0219.2. DC Parameters for Standard VoltageTA = -40°Cto+85°C; VSS=0V;VCC=5V± 10%;F=0to40MHz.Table 25. DC Par

Rev.A - May 17, 2001 131PreliminaryT89C51CC027. Lower than standart C51 product independant from Vcc supply.Figure 133. ICCTest Condition, Active Mode

132 Rev.A - May 17, 2001PreliminaryT89C51CC02Figure 136. Clock Signal Waveform for ICCTests in Active and Idle Modes19.3. DC Parameters for A/D Conver

Rev.A - May 17, 2001 133PreliminaryT89C51CC0219.4. AC Parameters19.4.1. Explanation of the AC SymbolsEach timing symbol has 5 characters. The first ch

134 Rev.A - May 17, 2001PreliminaryT89C51CC0219.4.3. Shift Register Timing Waveforms19.4.4. External Clock Drive Characteristics (XTAL1)Table 30. AC P

Rev.A - May 17, 2001 135PreliminaryT89C51CC0219.4.5. External Clock Drive Waveforms19.4.6. AC Testing Input/Output WaveformsAC inputs during testing a

136 Rev.A - May 17, 2001PreliminaryT89C51CC0220. Ordering InformationPackages:SI: PLCC28TI: SOW28TD: SOW246K: TSSOP28T-M: VCC: 5V40 MHz, X1 mode20 MH

Rev.A - May 17, 2001 137PreliminaryT89C51CC02Table 31. Possible order entriesExtension Type-SISIM Stick, PLCC28, Ind, 5V-TISIM Stick, SOIC28, Ind, 5V-

14 Rev.A - May 17, 2001PreliminaryT89C51CC02Figure 3. Clock CPU Generation DiagramXTAL1XTAL2PDPCON.1CPU Core10÷ 2PERIPHCLOCKClockPeripheral Clock Symb

Rev.A - May 17, 2001 15PreliminaryT89C51CC02Figure 4. Mode Switching WaveformsThe X2 bit in the CKCON register (See Table 5) allows switching from 12

16 Rev.A - May 17, 2001PreliminaryT89C51CC026.3. RegisterCKCON (S:8Fh)Clock Control RegisterNOTE:1. This control bit is validated when the CPU clock b

Rev.A - May 17, 2001 17PreliminaryT89C51CC027. Program/Code Memory7.1. IntroductionThe T89C51CC02 implement 16 Kbytes of on-chip program/code memory.

18 Rev.A - May 17, 2001PreliminaryT89C51CC027.2. FLASH Memory ArchitectureT89C51CC02 features two on-chip flash memories:• Flash memory FM0:containing

Rev.A - May 17, 2001 19PreliminaryT89C51CC027.2.1.3. Hardware security spaceThe Hardware security space is a part of FM0 and has a size of 1 byte.The

2 Rev.A - May 17, 2001PreliminaryT89C51CC02* At BRP = 1 sampling point will be fixed.** Ask for availability3. Block DiagramTimer 0INTRAM256x8T0T1RxDT

20 Rev.A - May 17, 2001PreliminaryT89C51CC027.3. Overview of FM0 operationsThe CPU interfaces to the flash memory through the FCON register and AUXR1

Rev.A - May 17, 2001 21PreliminaryT89C51CC02The FLASH memory enters a busy state as soon as programming is launched. In this state, the memory is nomo

22 Rev.A - May 17, 2001PreliminaryT89C51CC027.3.5. Loading the Column LatchesAny number of data from 1 byte to 128 bytes can be loaded in the column l

Rev.A - May 17, 2001 23PreliminaryT89C51CC027.3.6. Programming the FLASH SpacesUserThe following procedure is used to program the User space and is su

24 Rev.A - May 17, 2001PreliminaryT89C51CC02Figure 9. Flash and Extra row Programming ProcedureFLASH SpacesProgrammingDisable ITEA= 0Launch Programmin

Rev.A - May 17, 2001 25PreliminaryT89C51CC02Hardware SecurityThe following procedure is used to program the Hardware Security space and is summarized

26 Rev.A - May 17, 2001PreliminaryT89C51CC027.3.7. Reading the FLASH SpacesUserThe following procedure is used to read the User space and is summarize

Rev.A - May 17, 2001 27PreliminaryT89C51CC027.4. RegistersFCON (S:D1h)FLASH Control RegisterReset Value= 0000 0000bFigure 12. FCON Register7 6 5 4 3 2

28 Rev.A - May 17, 2001PreliminaryT89C51CC028. Data Memory8.1. IntroductionThe T89C51CC02 provides data memory access in two different spaces:1. The i

Rev.A - May 17, 2001 29PreliminaryT89C51CC028.2. Internal Space8.2.1. Lower 128 Bytes RAMThe lower 128 bytes of RAM (see Figure 13) are accessible fro

Rev.A - May 17, 2001 3PreliminaryT89C51CC024. Pin ConfigurationP3.4/T0P3.3/INT1P4.1/RxDC 1P3.7P3.2/INT0P1.5/AN5P1.7/AN7P1.6/AN6P2.0VAREFVAVCCVAGNDP1.0

30 Rev.A - May 17, 2001PreliminaryT89C51CC028.3. Dual Data Pointer8.3.1. DescriptionThe T89C51CC02 implements a second data pointer for speeding up co

Rev.A - May 17, 2001 31PreliminaryT89C51CC028.4. RegistersPSW (S:8Eh)Program Status Word Register.Reset Value= 0000 0000bFigure 16. PSW RegisterAUXR1

32 Rev.A - May 17, 2001PreliminaryT89C51CC029. EEPROM data memory9.1. General descriptionThe 2k byte on-chip EEPROM memory block is located at address

Rev.A - May 17, 2001 33PreliminaryT89C51CC029.4. Read DataThe following procedure is used to read the data stored in the EEPROM memory:• Set bit EEE o

34 Rev.A - May 17, 2001PreliminaryT89C51CC029.5. RegistersEECON (S:0D2h)EEPROM Control RegisterReset Value= XXXX XX00bNot bit addressableFigure 18. EE

Rev.A - May 17, 2001 35PreliminaryT89C51CC0210. In-System-Programming (ISP)10.1. IntroductionWith the implementation of the User ROM and the Boot ROM

36 Rev.A - May 17, 2001PreliminaryT89C51CC0210.2. Flash Programming and ErasureThere are three methods of programming the Flash memory:• The Atmel boo

Rev.A - May 17, 2001 37PreliminaryT89C51CC0210.2.1. Flash Parallel ProgrammingThe three lock bits in Hardware byte are programmed according to Table,

38 Rev.A - May 17, 2001PreliminaryT89C51CC0210.3 Boot Process10.3.1. Software boot process exampleMany algorithms can be used for the software boot pr

Rev.A - May 17, 2001 39PreliminaryT89C51CC02Figure 20. Hardware Boot Process AlgorithmRESETBLJB == 0?bit ENBOOT in AUXR1 registeris initialized with B

4 Rev.A - May 17, 2001PreliminaryT89C51CC02Table 1. Pin DescriptionPin Name Type DescriptionVSS GND Circuit ground potential.VCC Supply voltage during

40 Rev.A - May 17, 2001PreliminaryT89C51CC02Figure 21. Example of Software Boot processRESETBLJB == 0?bit ENBOOT in AUXR1 registeris initialized with

Rev.A - May 17, 2001 41PreliminaryT89C51CC0210.4. 2 Application-Programming-InterfaceSeveral Application Program Interface (API) calls are available f

42 Rev.A - May 17, 2001PreliminaryT89C51CC0210.5. Application remarks•After loading a new program using by the boot loader, the BLJB bit must be set t

Rev.A - May 17, 2001 43PreliminaryT89C51CC0210.6. XROW BytesTable 17. Xrow mappingSBV registerSoftware Boot VectorDefault value after erasing chip: FF

44 Rev.A - May 17, 2001PreliminaryT89C51CC0210.7. Hardware ByteDefault value after erasing chip: FFhNOTE:Only the 4 MSB bits can be access by software

Rev.A - May 17, 2001 45PreliminaryT89C51CC0211. Serial I/O PortThe T89C51CC02 I/O serial port is compatible with the I/O serial port in the 80C52.It

46 Rev.A - May 17, 2001PreliminaryT89C51CC02The software may examine the FE bit after each reception to check for data errors. Once set, only software

Rev.A - May 17, 2001 47PreliminaryT89C51CC0211.3. Given AddressEach device has an individual address that is specified in the SADDR register; the SAD

48 Rev.A - May 17, 2001PreliminaryT89C51CC0211.5. REGISTERSSCON (S:98h)Serial Control RegisterReset Value = 0000 0000bBit addressableFigure 29. SCON R

Rev.A - May 17, 2001 49PreliminaryT89C51CC02SADEN (S:B9h)Slave Address Mask RegisterReset Value = 0000 0000bNot bit addressableFigure 30. SADEN Regist

Rev.A - May 17, 2001 5PreliminaryT89C51CC02P4.0:1 I/OPort 4:Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s writ

50 Rev.A - May 17, 2001PreliminaryT89C51CC02PCON (S:87h)Power Control RegisterReset Value = 00X1 0000bNot bit addressableFigure 33. PCON Register7 6 5

Rev.A - May 17, 2001 51PreliminaryT89C51CC0212. Timers/Counters12.1. IntroductionThe T89C51CC02 implements two general-purpose, 16-bit Timers/Counters

52 Rev.A - May 17, 2001PreliminaryT89C51CC02Figure 34. Timer/Counter x (x= 0 or 1) in Mode 012.3.2. Mode 1 (16-bit Timer)Mode 1 configures Timer 0 as

Rev.A - May 17, 2001 53PreliminaryT89C51CC0212.3.4. Mode 3 (Two 8-bit Timers)Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as sepa

54 Rev.A - May 17, 2001PreliminaryT89C51CC0212.4.2. Mode 1 (16-bit Timer)Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connec

Rev.A - May 17, 2001 55PreliminaryT89C51CC0212.6. RegistersTCON (S:88h)Timer/Counter Control Register.Reset Value= 0000 0000bFigure 39. TCON Register7

56 Rev.A - May 17, 2001PreliminaryT89C51CC02TMOD (S:89h)Timer/Counter Mode Control Register.Reset Value= 0000 0000bFigure 40. TMOD RegisterTH0 (S:8Ch)

Rev.A - May 17, 2001 57PreliminaryT89C51CC02TL0 (S:8Ah)Timer 0 Low Byte Register.Reset Value= 0000 0000bFigure 42. TL0 RegisterTH1 (S:8Dh)Timer 1 High

58 Rev.A - May 17, 2001PreliminaryT89C51CC0213. Timer 213.1. IntroductionThe T89C51CC02 timer 2 is compatible with timer 2 in the 80C52.It is a 16-bi

Rev.A - May 17, 2001 59PreliminaryT89C51CC02Figure 45. Auto-Reload Mode Up/Down Counter13.3. Programmable Clock-OutputIn clock-out mode, timer 2 oper

6 Rev.A - May 17, 2001PreliminaryT89C51CC024.1. I/O ConfigurationsEach Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 an

60 Rev.A - May 17, 2001PreliminaryT89C51CC02• Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or diffe

Rev.A - May 17, 2001 61PreliminaryT89C51CC0213.4. RegistersT2CON (S:C8h)Timer 2 Control RegisterReset Value = 0000 0000bBit addressableFigure 47. T2CO

62 Rev.A - May 17, 2001PreliminaryT89C51CC02T2MOD (S:C9h)Timer 2 Mode Control RegisterReset Value = XXXX XX00bNot bit addressableFigure 48. T2MOD Regi

Rev.A - May 17, 2001 63PreliminaryT89C51CC02TL2 (S:CCh)Timer 2 Low Byte RegisterReset Value = 0000 0000bNot bit addressableFigure 50. TL2 RegisterRCAP

64 Rev.A - May 17, 2001PreliminaryT89C51CC0214. WatchDog Timer14.1. IntroductionT89C51CC02 contains a powerful programmable hardware WatchDog Timer (W

Rev.A - May 17, 2001 65PreliminaryT89C51CC0214.2. WatchDog ProgrammingThe three lower bits (S0, S1, S2) located into WDTPRG register permits to progra

66 Rev.A - May 17, 2001PreliminaryT89C51CC0214.3. WatchDog Timer during Power down mode and IdleIn Power Down mode the oscillator stops, which means t

Rev.A - May 17, 2001 67PreliminaryT89C51CC0214.4. RegisterWDTPRG (S:A7h)WatchDog Timer Duration Programming registerReset Value = XXXX X000bFigure 54.

68 Rev.A - May 17, 2001PreliminaryT89C51CC0215. Atmel CAN Controller15.1. IntroductionThe Atmel CAN Controller provides all the features required to i

Rev.A - May 17, 2001 69PreliminaryT89C51CC0215.3. CAN Controller Mailbox and Registers OrganizationA pagination allows management of the 48 registers

Rev.A - May 17, 2001 7PreliminaryT89C51CC024.3. Read-Modify-Write InstructionsSome instructions read the latch data rather than the pin data. The latc

70 Rev.A - May 17, 2001PreliminaryT89C51CC0215.3.1. Working on message objectsThe Page message object register (CANPAGE) is used to select one of the

Rev.A - May 17, 2001 71PreliminaryT89C51CC0215.3.3. Buffer modeAny message object can be used to define the buffer, including non-consecutive message

72 Rev.A - May 17, 2001PreliminaryT89C51CC0215.4. IT CAN managementThe different interrupts are:• Transmission interrupt,• Reception interrupt,• Inter

Rev.A - May 17, 2001 73PreliminaryT89C51CC02To enable a transmission interrupt:• Enable General CAN IT in the interrupt system register,• Enable inter

74 Rev.A - May 17, 2001PreliminaryT89C51CC0215.5. Bit Timing and BaudRateThe baud rate selection is made by Tbit calculation:Tbit = Tsyns + Tprs + Tph

Rev.A - May 17, 2001 75PreliminaryT89C51CC0215.6. Fault ConfinementWith respect to fault confinement, a unit may be in one of the three following stat

76 Rev.A - May 17, 2001PreliminaryT89C51CC0215.7. Acceptance filterUpon a reception hit (i.e., a good comparison between the ID+RTR+RB+IDE received an

Rev.A - May 17, 2001 77PreliminaryT89C51CC0215.8. Data and Remote frameDescription of the different steps for:• Data frame,• Remote frame, with automa

78 Rev.A - May 17, 2001PreliminaryT89C51CC0215.9. Time Trigger Communication (TTC) and Message StampingThe T89C51CC02 has a programmable 16-bit Timer

Rev.A - May 17, 2001 79PreliminaryT89C51CC0215.10. CAN Autobaud and Listening modeTo activate the Autobaud feature, the AUTOBAUD bit in the CANGCON re

8 Rev.A - May 17, 2001PreliminaryT89C51CC02Figure 2. Internal Pull-Up ConfigurationsREAD PININPUT DATAP1.xOUTPUT DATA2 Osc. PERIODSnp1p2p3VCCVCCVCCP2.

80 Rev.A - May 17, 2001PreliminaryT89C51CC0215.11. CAN SFR’sTable 21. CAN SFR’s with reset values0/8(1)1/9 2/A 3/B 4/C 5/D 6/E 7/FF8hIPL1xxxx x000CH00

Rev.A - May 17, 2001 81PreliminaryT89C51CC0215.12. RegistersCANGCON (S:ABh)CAN General Control RegisterReset Value: 0000 0x00bFigure 65. CANGCON Regis

82 Rev.A - May 17, 2001PreliminaryT89C51CC02CANGSTA (S:AAh)CAN General Status RegisterNOTE:1. These fields are Read Only.Reset Value: x0x0 0000bFigure

Rev.A - May 17, 2001 83PreliminaryT89C51CC02CANGIT (S:9Bh)CAN General InterruptReset Value: 0x00 0000bFigure 67. CANGIT Register7 6 5 4 3 2 1 0CANIT -

84 Rev.A - May 17, 2001PreliminaryT89C51CC02CANTEC (S:9Ch Read Only)CAN Transmit Error CounterReset Value: 00hFigure 68. CANTEC RegisterCANREC (S:9Dh

Rev.A - May 17, 2001 85PreliminaryT89C51CC02CANGIE (S:C1h)CAN General Interrupt EnableNOTE:see Figure 59Reset Value: xx00 000xbFigure 70. CANGIE Regis

86 Rev.A - May 17, 2001PreliminaryT89C51CC02CANSIT (S:BBh Read Only)CAN Status Interrupt message object RegistersReset Value: xxxx 0000bFigure 72. CAN

Rev.A - May 17, 2001 87PreliminaryT89C51CC02CANBT1 (S:B4h)CAN Bit Timing Registers 1Note:The CAN controller bit timing registers must be accessed only

88 Rev.A - May 17, 2001PreliminaryT89C51CC02CANBT2 (S:B5h)CAN Bit Timing Registers 2Note:The CAN controller bit timing registers must be accessed only

Rev.A - May 17, 2001 89PreliminaryT89C51CC02CANBT3 (S:B6h)CAN Bit Timing Registers 3Note:The CAN controller bit timing registers must be accessed only

Rev.A - May 17, 2001 9PreliminaryT89C51CC025. SFR MappingThe Special Function Registers (SFRs) of the T89C51CC02 fall into the following categories:Ta

90 Rev.A - May 17, 2001PreliminaryT89C51CC02CANCONCH (S:B3h)CAN message object Control and DLC RegisterNo default value after resetFigure 78. CANCONCH

Rev.A - May 17, 2001 91PreliminaryT89C51CC02CANSTCH (S:B2h)CAN message object Status RegisterNOTE:See Figure 59.No default value after reset.Figure 79

92 Rev.A - May 17, 2001PreliminaryT89C51CC02CANIDT1 for V2.0 part A (S:BCh)CAN Identifier Tag Registers 1No default value after reset.Figure 80. CANID

Rev.A - May 17, 2001 93PreliminaryT89C51CC02CANIDT4 for V2.0 part A (S:BFh)CAN Identifier Tag Registers 4No default value after reset.Figure 83. CANID

94 Rev.A - May 17, 2001PreliminaryT89C51CC02CANIDT3 for V2.0 part B (S:BEh)CAN Identifier Tag Registers 3No default value after reset.Figure 86. CANID

Rev.A - May 17, 2001 95PreliminaryT89C51CC02CANIDM2 for V2.0 part A (S:C5h)CAN Identifier Mask Registers 2No default value after reset.Figure 89. CANI

96 Rev.A - May 17, 2001PreliminaryT89C51CC02CANIDM4 for V2.0 part A (S:C7h)CAN Identifier Mask Registers 4NOTE:The ID Mask is only used for reception.

Rev.A - May 17, 2001 97PreliminaryT89C51CC02CANIDM2 for V2.0 part B (S:C5h)CAN Identifier Mask Registers 2NOTE:The ID Mask is only used for reception.

98 Rev.A - May 17, 2001PreliminaryT89C51CC02CANIDM4 for V2.0 part B (S:C7h)CAN Identifier Mask Registers 4NOTE:The ID Mask is only used for reception.

Rev.A - May 17, 2001 99PreliminaryT89C51CC02CANTCON (S:A1h)CAN Timer ClockControlReset Value: 00hFigure 97. CANTCON RegisterCANTIMH (S:ADh Read Only)C