Rainbow-electronics W90N740 User Manual

Publication Release Date: November 26, 2004 - I - Revision A4 W90N740 Data Sheet WINBOND 32-BIT ARM7TDMI-BASED MICRO-CONTROLLER

W90N740 - 6 - 4. PIN CONFIGURATION 8514050 55 60 80757065165 160 155 150 145175 170VDD18VSS18VDD33VDD33VSS33GP18/nIRQ1GP17/nIRQ0GP20/nIRQ3GP19/nIRQ2G

W90N740 - 96 - DMA Receive Frame Control Register (DMARFC_0, DMARFC_1) Register Address R/W Description Reset Value DMARFC_0 0xFFF0.30A4 R/W DMA

W90N740 Publication Release Date: November 26, 2004 - 97 - Revision A4 Transmit Start Demand Register (TSDR_0, TSDR_1) Register Address R/W Descri

W90N740 - 98 - Receive Start Demand Register (TSDR_0, TSDR_1) Register Address R/W Description Reset Value RSDR_0 0xFFF0.30AC W Receive Start Deman

W90N740 Publication Release Date: November 26, 2004 - 99 - Revision A4 FIFO Threshold Adjustment Register (FIFOTHD_0, FIFOTHD_1) Register Address R

W90N740 - 100 - setting value, Tx DMA will request the arbiter to get data from memory. RxTHD [1:0]: Receive FIFO Upper threshold Register Default va

W90N740 Publication Release Date: November 26, 2004 - 101 - Revision A4 MAC Interrupt Status Register (MISTA_0, MISTA_1) The MAC event register is

W90N740 - 102 - TXABT [21]: Transmit Abort Default value: 0 The bit is set to indicate 16 collisions occur while transmitting the same packet. NCS [2

W90N740 Publication Release Date: November 26, 2004 - 103 - Revision A4 This field will be set if there is no error during NATA do the NAT processi

W90N740 - 104 - Default value: 0 This bit is set if a packet was successfully received with no errors. PTLE [3]: Packet Too Long Error Default value:

W90N740 Publication Release Date: November 26, 2004 - 105 - Revision A4 MAC General Status Register (MGSTA_0, MGSTA_1) Register Address R/W Descr

W90N740 Publication Release Date: November 26, 2004 - 7 - Revision A4 5. PIN ASSIGNMENT Table 4 W90N740 Pins Assignment PIN NAME 176-PIN LQFP Cloc

W90N740 - 106 - RXHA [1]: Reception Halted Default value: 0 This bit is set if reception is halted by clearing RXON bit in the MAC Command Register (

W90N740 Publication Release Date: November 26, 2004 - 107 - Revision A4 MAC Received Pause Current Count Register (MRPCC_0, MRPCC_1) The received p

W90N740 - 108 - MAC Remote Pause Count Register (MREPC_0, MREPC_1) The remote pause count register, MREPC, stores the current value of the remote pa

W90N740 Publication Release Date: November 26, 2004 - 109 - Revision A4 DMA Receive Frame Status Register (DMARFS_0, DMARFS_1) Register Address R/

W90N740 - 110 - Current Transmit Descriptor Start Address Register (CTXDSA_0, CTXDSA_1) Register Address R/W Description Reset ValueCTXDSA_0 0xFFF

W90N740 Publication Release Date: November 26, 2004 - 111 - Revision A4 Current Transmit Buffer Start Address Register (CTXBSA_0, CTXBSA_1) Regist

W90N740 - 112 - Current Receive Descriptor Start Address Register (CRXDSA_0, CRXDSA_1) Register Address R/W Description Reset ValueCRXDSA_0 0xFFF0

W90N740 Publication Release Date: November 26, 2004 - 113 - Revision A4 Current Receive Buffer Start Address Register (CRXBSA_0, CRXBSA_1) Registe

W90N740 - 114 - 7.6 Network Address Translation Accelerator (NATA) The Network Address Translation Accelerator (NATA) provides hardware acceleration

W90N740 Publication Release Date: November 26, 2004 - 115 - Revision A4 7.6.1 NAT Process Flow NAT Process FlowWhile EMC port get valid MAC packe

W90N740 - 8 - Table 4 W90N740 Pins Assignment (Continued) PIN NAME 176-PIN LQFP Ethernet Interface (0) ( 17 pins ) MDC0 z 142 MDIO0 z 143 COL0 /

W90N740 - 116 - 7.6.2 NATA Registers Map This set of registers is used to convey status/control information to/from the NAT engine. These registers

W90N740 Publication Release Date: November 26, 2004 - 117 - Revision A4 REGISTER OFFSET R/W DESCRIPTION RESET VALUEAddress Lookup and Replacemen

W90N740 - 118 - NAT Command Register (NATCMD) The NAT function is enabled by software setting NATEN, and auto triggered by EMC Rx if current packet

W90N740 Publication Release Date: November 26, 2004 - 119 - Revision A4 NAT Counter x Clear Register (NATCCLRx)(x: 3 ~ 0) Register Address R/W D

W90N740 - 120 - NATCCLR2 31 30 29 28 27 26 25 24 CLREH47 CLREH46 CLREH45 CLREH44 CLREH43 CLREH42 CLREH41 CLREH4023 22 21 20 19 18 17 16

W90N740 Publication Release Date: November 26, 2004 - 121 - Revision A4 NAT Entry x Configuration Registers (NATCFGx)(x: 63 ~ 0) All NAT Configurat

W90N740 - 122 - 7.6.2.5 CNTx [10:8]: Number of Entry x Hit Packets to be processed Default value: 0x0 The register is read-only, to indicate that ho

W90N740 Publication Release Date: November 26, 2004 - 123 - Revision A4 ExEN [0]: Entry x Comparison Enable bit Default value: 0 Set the bits to se

W90N740 - 124 - NATA comparison and replacement table at different port Inverse bit is reset Inverse bit is set Comparison Replacement Comparison R

W90N740 Publication Release Date: November 26, 2004 - 125 - Revision A4 MAC Address Registers (EXMACM, EXMACL, INMACM, INMACL, LSMACxM, LSMACxL, RS

W90N740 Publication Release Date: November 26, 2004 - 9 - Revision A4 Table 4 W90N740 Pins Assignment (Continued) NAME 176-PIN LQFP USB Interface

W90N740 - 126 - NAT Masquerading IP Address Registers (MASADx) (x : 15 ~ 0) NAT Masquerading Port Number Registers (MASPNx) (x : 15 ~ 0) Local Statio

W90N740 Publication Release Date: November 26, 2004 - 127 - Revision A4 7.7 GDMA Controller The GDMA Controller of W90N740 is a two-channel general

W90N740 - 128 - 7.7.2 GDMA Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUEGDMA_CTL0 0xFFF0.4000 R/WChannel 0 Control Register 0x0000.000

W90N740 Publication Release Date: November 26, 2004 - 129 - Revision A4 Channel 0/1 Control Register (GDMA_CTL0, GDMA_CTL1) Register Address R/W D

W90N740 - 130 - RW_TC [23]: Read/Write terminal count output selection. (This is for PCMCIA application in DMA mode, will be active during the final

W90N740 Publication Release Date: November 26, 2004 - 131 - Revision A4 BLOCK [17]: Bus Lock 0 = Unlocks the bus during the period of transfer 1 =

W90N740 - 132 - However, if BME [9]=0, the GDMA_TCNT should be 0x10. SIEN [8]: Stop Interrupt Enable 0 = Do not generate an interrupt when the GDMA o

W90N740 Publication Release Date: November 26, 2004 - 133 - Revision A4 Channel 0/1 Source Base Address Register (GDMA_SRCB0, GDMA_SRCB1) The GDMA

W90N740 - 134 - Channel 0/1 Transfer Count Register (GDMA_TCNT0, GDMA_TCNT1) Register Address R/W Description Reset Value GDMA_TCNT0 0xFFF0.400C

W90N740 Publication Release Date: November 26, 2004 - 135 - Revision A4 Channel 0/1 Current Destination Register (GDMA_CDST0, GDMA_CDST1) Register

W90N740 - 10 - 6. PIN DESCRIPTION Table 6.1 W90N740 Pins Description PIN NAME IO TYPE PAD TYPE DESCRIPTION System Clock & Reset EXTAL I - Exte

W90N740 - 136 - 7.8 USB Host Controller The Universal Serial Bus (USB) is a low-cost, low-to-middle speed peripheral interface standard intended fo

W90N740 Publication Release Date: November 26, 2004 - 137 - Revision A4 7.8.1 USB Host Controller Registers Map REGISTER ADDRESS R/W DESCRIPTION

W90N740 - 138 - Host Controller Revision Register (HcRevision) Register Address R/W Description Reset ValueHcRevision 0xFFF0.5000 R Host Controller

W90N740 Publication Release Date: November 26, 2004 - 139 - Revision A4 Register: HcControl Bits Reset R/W Description 5 0b R/W BulkListEnable W

W90N740 - 140 - Host Controller Command Status Register (HcCommandStatus) Register Address R/W Description Reset ValueHcCommandStatus 0xFFF0.5008 R/

W90N740 Publication Release Date: November 26, 2004 - 141 - Revision A4 Host Controller Interrupt Status Register (HcInterruptStatus) All bits are

W90N740 - 142 - Host Controller Interrupt Enable Register (HcInterruptEnable) Writing a ‘1’ to a bit in this register sets the corresponding bit, whi

W90N740 Publication Release Date: November 26, 2004 - 143 - Revision A4 Host Controller Interrupt Disable Register (HcInterruptDisable) Writing a ‘

W90N740 - 144 - Host Controller Communication Area Register (HcHCCA) Register Address R/W Description Reset ValueHcHCCA 0xFFF0.5018 R/W Host Control

W90N740 Publication Release Date: November 26, 2004 - 145 - Revision A4 Host Controller Control Current ED Register (HcControlCurrentED) Register A

W90N740 Publication Release Date: November 26, 2004 - 11 - Revision A4 Pins Description, continued PIN NAME IO TYPE PAD TYPE DESCRIPTION Ethernet I

W90N740 - 146 - Host Controller Bulk Current ED Register (HcBulkCurrentED) Register Address R/W Description Reset ValueHcBulkCurrentED 0xFFF0.502C R

W90N740 Publication Release Date: November 26, 2004 - 147 - Revision A4 Register: HcFmInterval Bits Reset R/W Description 30-16 FSLargestData

W90N740 - 148 - Host Controller Periodic Start Register (HcPeriodicStart) Register Address R/W Description Reset ValueHcPeriodicStart 0xFFF0.5040 R

W90N740 Publication Release Date: November 26, 2004 - 149 - Revision A4 Host Controller Root Hub Descriptor A Register (HcRhDescriptorA) This regis

W90N740 - 150 - Host Controller Root Hub Descriptor B Register (HcRhDescriptorB) This register is only reset by a power-on reset. It is written duri

W90N740 Publication Release Date: November 26, 2004 - 151 - Revision A4 Host Controller Root Hub Status Register (HcRhStatus) This register is rese

W90N740 - 152 - Host Controller Root Hub Port Status (HcRhPortStatus [1:2]) This register is reset by the USBRESET state. Register Address R/W Descr

W90N740 Publication Release Date: November 26, 2004 - 153 - Revision A4 Register: HcRhPortStatus[1:2] Bits Reset R/W Description 7-5 0h - Rese

W90N740 - 154 - 7.9 UART Controller The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel conversion on data character

W90N740 Publication Release Date: November 26, 2004 - 155 - Revision A4 7.9.1 UART Control Registers Map R: read only, W: write only, R/W: both re

W90N740 - 12 - Pins Description, continued PIN NAME IO TYPE PAD TYPE DESCRIPTION Ethernet Interface (1) MDC1 O - MII Management Data Clock for Ethern

W90N740 - 156 - Transmit Holding Register (THR) Register Address R/W Description Reset Value THR 0xFFF8.0000 W Transmit Holding Register (DLAB =

W90N740 Publication Release Date: November 26, 2004 - 157 - Revision A4 RDAIE [0]: Receive Data Available Interrupt (Irpt_RDA) Enable and Time-out

W90N740 - 158 - Interrupt Identification Register (IIR) Register Address R/W Description Reset Value IIR 0xFFF8.0008 R Interrupt Identificatio

W90N740 Publication Release Date: November 26, 2004 - 159 - Revision A4 FIFO Control Register (FCR) Register Address R/W Description Reset Valu

W90N740 - 160 - Line Control Register (LCR) Register Address R/W Description Reset Value LCR 0xFFF8.000C R/W Line Control Register 0x0000.0000

W90N740 Publication Release Date: November 26, 2004 - 161 - Revision A4 WLS [1:0]: Word Length Select WLS[1:0] Character length 00 5 bits 01 6 bits

W90N740 - 162 - Line Status Control Register (LSR) Register Address R/W Description Reset Value LSR 0xFFF8.0014 R Line Status Register 0x6060

W90N740 Publication Release Date: November 26, 2004 - 163 - Revision A4 PEI [2]: Parity Error Indicator This bit is set to logic 1 whenever the rec

W90N740 - 164 - TERI [2]: Tailing Edge of RI# This bit is set whenever RI# input has changed from high to low, and it will be reset if the CPU reads

W90N740 Publication Release Date: November 26, 2004 - 165 - Revision A4 7.10 TIMER Controller 7.10.1 General Timer Controller The timer module has

W90N740 Publication Release Date: November 26, 2004 - 13 - Revision A4 Pins Description, continued NAME IO TYPE PAD TYPE DESCRIPTION USB Interface

W90N740 - 166 - 7.10.3 Timer Control Registers Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Ad

W90N740 Publication Release Date: November 26, 2004 - 167 - Revision A4 0 = Disables timer interrupt 1 = Enables timer interrupt. If timer interrup

W90N740 - 168 - TIC [23:0]: Timer Initial Count This is a 24-bit value representing the initial count. Timer will reload this value whenever the coun

W90N740 Publication Release Date: November 26, 2004 - 169 - Revision A4 Timer Interrupt Status Register (TISR) Register Address R/W/C Description

W90N740 - 170 - Watchdog Timer Control Register (WTCR) Register Address R/W/C Description Reset Value WTCR 0xFFF8.101C R/W Watchdog Timer Control R

W90N740 Publication Release Date: November 26, 2004 - 171 - Revision A4 WTIS [5:4] Interrupt Time-out Reset Time-out 00 220 clocks 220 + 512 clo

W90N740 - 172 - 7.11 Advanced Interrupt Controller (AIC) An interrupt temporarily changes the sequence of program execution to react to a particular

W90N740 Publication Release Date: November 26, 2004 - 173 - Revision A4 7.11.1 Interrupt Sources The table as shown below lists all the interrupt s

W90N740 - 174 - 7.11.2 AIC Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_SCR1 0xFFF8.2004 R/W Source Control Register 1 0x0000

W90N740 Publication Release Date: November 26, 2004 - 175 - Revision A4 AIC Source Control Registers (AIC_SCR1 ~ AIC_SCR18) Register Address R/W

W90N740 - 14 - 7. FUNCTIONAL DESCRIPTION 7.1 ARM7TDMI CPU Core The ARM7TDMI CPU core is a member of the ARM family of general-purpose 32-bit micropr

W90N740 - 176 - AIC Interrupt Raw Status Register (AIC_IRSR) Register Address R/W Description Reset Value AIC_IRSR 0xFFF8.2100 R Interrupt Raw Sta

W90N740 Publication Release Date: November 26, 2004 - 177 - Revision A4 AIC Interrupt Active Status Register (AIC_IASR) Register Address R/W Desc

W90N740 - 178 - AIC Interrupt Status Register (AIC_ISR) Register Address R/W Description Reset Value AIC_ISR 0xFFF8.2108 R Interrupt Status Regist

W90N740 Publication Release Date: November 26, 2004 - 179 - Revision A4 AIC IRQ Priority Encoding Register (AIC_IPER) Register Address R/W Descri

W90N740 - 180 - AIC Interrupt Source Number Register (AIC_ISNR) Register Address R/W Description Reset Value AIC_ISNR 0xFFF8.2110 R Interrupt Sour

W90N740 Publication Release Date: November 26, 2004 - 181 - Revision A4 AIC Interrupt Mask Register (AIC_IMR) Register Address R/W Description R

W90N740 - 182 - AIC Output Interrupt Status Register (AIC_OISR) Register Address R/W Description Reset Value AIC_OISR 0xFFF8.2118 R Output Interru

W90N740 Publication Release Date: November 26, 2004 - 183 - Revision A4 AIC Mask Enable Command Register (AIC_MECR) Register Address R/W Descript

W90N740 - 184 - AIC Mask Disable Command Register (AIC_MDCR) Register Address R/W Description Reset Value AIC_MDCR 0xFFF8.2124 W Mask Disable Comm

W90N740 Publication Release Date: November 26, 2004 - 185 - Revision A4 AIC Source Set Command Register (AIC_SSCR) Register Address R/W Descripti

W90N740 Publication Release Date: November 26, 2004 - 15 - Revision A4 7.2 System Manager 7.2.1 Overview The functions of the System Manager: • Sys

W90N740 - 186 - AIC Source Clear Command Register (AIC_SCCR) Register Address R/W Description Reset Value AIC_SCCR 0xFFF8.212C W Source Clear Comma

W90N740 Publication Release Date: November 26, 2004 - 187 - Revision A4 AIC End of Service Command Register (AIC_EOSCR) Register Address R/W Desc

W90N740 - 188 - 7.12 General-Purpose Input/Output Controller (GPIO) The General-Purpose Input/Output (GPIO) module possesses 21 pins and serves mult

W90N740 Publication Release Date: November 26, 2004 - 189 - Revision A4 7.12.1 GPIO Controller Registers Map REGISTER ADDRESS R/W DESCRIPTION RES

W90N740 - 190 - GPIOCFG19 [19:18]: Operating mode for GPIO19 11 10 01 00 GPIOCFG19 Name Type Name Type Name Type Name TypeGPIO19 RESERVED I RESERVE

W90N740 Publication Release Date: November 26, 2004 - 191 - Revision A4 GPIOCFG13 [9:8]: Operating mode for GPIO13 11 10 01 00 GPIOCFG13 Name Type

W90N740 - 192 - GPIOCFG3_0 [1:0]: Operating mode for GPIO3, GPIO2, GPIO1, and GPIO0 11 10 01 00 GPIOCFG3_0 Name Type Name Type Name Type Name T

W90N740 Publication Release Date: November 26, 2004 - 193 - Revision A4 GPIO Data Output Register (GPIO_DATAOUT) Register Address R/W Description

W90N740 - 194 - Debounce Control Register (DEBNCE_CTRL) Register Address R/W Description Reset Value DEBNCE_CTRL 0xFFF8.3010 R/W De-bounce Control R

W90N740 Publication Release Date: November 26, 2004 - 195 - Revision A4 8. ELECTRICAL CHARACTERISTICS 8.1 Absolute Maximum Ratings Ambient Tempe

W90N740 - II - The information described in this document is the exclusive intellectual property of Winbond Electronics Corpor

W90N740 - 16 - ROM/FLASH256KB - 32MBSDRAM Bank 02MB - 64MBSDRAM Bank 12MB - 64MBExternal I/O Bank 0256KB - 32MBExternal I/O Bank 1256KB - 32MBExterna

W90N740 - 196 - 8.2 DC Characteristics (Normal test conditions: VDD33/USBVDD = 3.3V+/- 0.3V, VDD18/DVDD18/AVDD18 = 1.8V+/- 0.18V TA = 0 °C ~ 70 °C u

W90N740 Publication Release Date: November 26, 2004 - 197 - Revision A4 8.3 AC Characteristics 8.3.1 EBI/SDRAM Interface AC Characteristics MCLKD[

W90N740 - 198 - 8.3.3 EBI/(ROM/SRAM/External I/O) AC Characteristics Address ValidR DataWrite Data VaildMCLKTDOnECS[3:0]A[24:0]nOED[31:0]nWAITnWBE[3

W90N740 Publication Release Date: November 26, 2004 - 199 - Revision A4 8.3.4 USB Transceiver AC Characteristics Low Speed: 75ns at CL = 50pF, 30

W90N740 - 200 - 8.3.5 EMC MII AC Characteristics The signal timing characteristics conforms to the guidelines specified in IEEE Std. 802.3. TX_CLK

W90N740 Publication Release Date: November 26, 2004 - 201 - Revision A4 MDCMDIOVALIDINPUTTMDHTMDSU MDIO Read From PHY Timing MDCMDIOTMDOValid

W90N740 - 202 - 9. PACKAGE DIMENSIONS 176-Pin LQFP (note that the value in inches may have some inaccuracy as it is translated from the value in mill

W90N740 Publication Release Date: November 26, 2004 - 203 - Revision A4 10. W90N740 REGISTERS MAPPING TABLE R: read only, W: write only, R/W: both

W90N740 - 204 - EMC 0 Control registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUECAM REGISTERS CAMCMR_0 0xFFF0.3000 R/W CAM Command Register

W90N740 Publication Release Date: November 26, 2004 - 205 - Revision A4 EMC 0 Control registers Map, continued REGISTER ADDRESS R/W DESCRIPTION RE

W90N740 Publication Release Date: November 26, 2004 - 17 - Revision A4 Table 7.2.1 On-Chip Peripherals Memory Map BASE ADDRESS DESCRIPTION AHB P

W90N740 - 206 - EMC 0 Status Registers REGISTER ADDRESS R/W DESCRIPTION RESET VALUEMAC REGISTERS MISTA_0 0xFFF0.30B4 R/W MAC Interrupt Status Regi

W90N740 Publication Release Date: November 26, 2004 - 207 - Revision A4 EMC 1 Control Registers REGISTER ADDRESS R/W DESCRIPTION RESET VALUECAM RE

W90N740 - 208 - REGISTER ADDRESS R/W DESCRIPTION RESET VALUECAM REGISTERS CAM14M_1 0xFFF0.3870 R/W CAM14 Most Significant Word Register 0x0000.0

W90N740 Publication Release Date: November 26, 2004 - 209 - Revision A4 EMC 1 Status Registers REGISTER ADDRESS R/W DESCRIPTION RESET VALUEMAC REG

W90N740 - 210 - USB Host Controller Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUEOpenHCI Registers HcRevision 0xFFF0.5000 R Host Contro

W90N740 Publication Release Date: November 26, 2004 - 211 - Revision A4 NATA Registers Map REGISTER OFFSET R/W DESCRIPTION RESET VALUENATA Contro

W90N740 - 212 - REGISTER OFFSET R/W DESCRIPTION RESET VALUEAddress Lookup and Replacement Registers MASAD0 0xFFF0.6800 R/W NAT Masquerading IP A

W90N740 Publication Release Date: November 26, 2004 - 213 - Revision A4 UART Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUER

W90N740 - 214 - AIC Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUEAIC_SCR1 0xFFF8.2004 R/W Source Control Register 1 0x0000.0047 AIC_S

W90N740 Publication Release Date: November 26, 2004 - 215 - Revision A4 11. ORDERING INFORMATION PART NUMBER NAME PACKAGE DESCRIPTION W90N740CD

W90N740 - 18 - 7.2.4 Data Bus Connection with External Memory 7.2.4.1 Memory formats The internal architecture is big endian. The little endian mode

W90N740 Publication Release Date: November 26, 2004 - 19 - Revision A4 7.2.4.2 Connection of External Memory with Various Data Width The system di

W90N740 - 20 - Table 7.2.3 and Table 7.2.4 Using big-endian and word access, Program/Data path between register and external memory WA = Address whos

W90N740 Publication Release Date: November 26, 2004 - 21 - Revision A4 Table 7.2.5 and Table 7.2.6 Using big-endian and half-word access, Program/D

W90N740 - 22 - Table 7.2.7 and Table 7.2.8 Using big-endian and byte access, Program/Data path between register and external memory. BA = Address who

W90N740 Publication Release Date: November 26, 2004 - 23 - Revision A4 Table7.2.8 Byte access read operation with Big Endian Access Operation Read

W90N740 - 24 - Table 7.2.9 and Table 7.2.10 Using little-endian and word access, Program/Data path between register and external memory WA = Address

W90N740 Publication Release Date: November 26, 2004 - 25 - Revision A4 Table 7.2.11 and Table 7.2.12 Using little-endian and half-word access, Prog

W90N740 Publication Release Date: November 26, 2004 - III - Revision A4 Table of Contents- 1. GENERAL DESCRIPTION ...

W90N740 - 26 - Table 7.2.13 and Table 7.2.14 Using little-endian and byte access, Program/Data path between register and external memory. BA = Addres

W90N740 Publication Release Date: November 26, 2004 - 27 - Revision A4 7.2.5 Bus Arbitration The W90N740’s internal function blocks or external dev

W90N740 - 28 - 7.2.5.2 Rotate Priority Mode In Rotate Priority Mode (PRTMOD = 1), the IPEN and IPACT bits have no function (i.e. ignore). W90N740

W90N740 Publication Release Date: November 26, 2004 - 29 - Revision A4 7.2.7 System Manager Control Registers Map Register Address R/W Description

W90N740 - 30 - Arbitration Control Register (ARBCON) Register Address R/W Description Reset Value ARBCON 0xFFF0.0004 R/W Arbitration Control Regi

W90N740 Publication Release Date: November 26, 2004 - 31 - Revision A4 PLL Control Register （PLLCON） W90N740 provides two options for clock generat

W90N740 - 32 - INDV [4:0] ：PLL input clock divider Input Divider divides the input reference clock into the PLL. Input Divider(NR)PFDFeedbackDivide

W90N740 Publication Release Date: November 26, 2004 - 33 - Revision A4 Clock Select Register (CLKSEL) REGISTER ADDRESS R/W DESCRIPTION RESET VA

W90N740 - 34 - WDT [8] ： WDT clock enable bit 0 = Disable WDT counting clock 1 = Enable WDT counting clock USB [7] ： USB clock enable bit 0 = Disabl

W90N740 Publication Release Date: November 26, 2004 - 35 - Revision A4 RESET [0] ： Reset This is a software reset control bit. Set logic 1 to gene

W90N740 - IV - 7.8 USB Host Controller ... 136 7.8.1

W90N740 - 36 - 7.3.2.1 SDRAM Components Supported • 16M bit SDRAM − 2Mx8 with 2 banks ；RA0 ~ RA10, CA0 ~ CA8 − 1Mx16 with 2 banks；RA0 ~ RA10, CA

W90N740 Publication Release Date: November 26, 2004 - 37 - Revision A4 SDRAM Data Bus Width: 32-bit Total Type R x C R/C A14 (BS1) A13 (BS0) A12

W90N740 - 38 - SDRAM Data Bus Width: 16-bit Total Type R x C R/C A14 (BS1) A13 (BS0) A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A016M 2Mx8 11x9 R *

W90N740 Publication Release Date: November 26, 2004 - 39 - Revision A4 SDRAM Data Bus Width: 8-bit Total Type R x C R/C A14 (BS1) A13 (BS0) A12

W90N740 - 40 - SDRAM Power Up Sequence The default value of the mode register is not defined, therefore the mode register must be written after power

W90N740 Publication Release Date: November 26, 2004 - 41 - Revision A4 7.3.3 External Bus Mastership The W90N740 can receive and acknowledge bus r

W90N740 - 42 - EBI Control Register (EBICON) Register Address R/W Description Reset Value EBICON 0xFFF0.1000 R/W EBI control register 0x0001.0000

W90N740 Publication Release Date: November 26, 2004 - 43 - Revision A4 WAITVT [2:1]: Valid time of nWAIT signal W90N740 recognizes the nEWAIT sign

W90N740 - 44 - ROM/Flash Control Register （ROMCON） Register Address R/W Description Reset Value ROMCON 0xFFF0.1004 R/W ROM/FLASH control register

W90N740 Publication Release Date: November 26, 2004 - 45 - Revision A4 tPA [11:8]：Page mode access cycle time tPA [11:8] MCLK0 0 0 0 1 0 0 0 1

W90N740 Publication Release Date: November 26, 2004 - 1 - Revision A4 1. GENERAL DESCRIPTION The W90N740 micro-controller is 16/32 bit, ARM7TDMI

W90N740 - 46 - PGMODE [1:0] ：Page mode configuration PGMODE [1:0] Mode 0 0 Normal ROM 0 1 4 word page 1 0 8 word page 1 1 16 word page Fig7

W90N740 Publication Release Date: November 26, 2004 - 47 - Revision A4 Configuration Registers（SDCONF0/1） The configuration registers enable softwa

W90N740 - 48 - LATENCY [12:11] ：The CAS Latency of SDRAM bank 0/1 Defines the CAS latency of external SDRAM bank 0/1 LATENCY [12:11] MCLK 0 0 1 0

W90N740 Publication Release Date: November 26, 2004 - 49 - Revision A4 SIZE [2:0] ：Size of SDRAM bank 0/1 Indicates the memory size of external SDR

W90N740 - 50 - tRCD [10:8] ：SDRAM bank 0/1, /RAS to /CAS delay (see Fig 7.3.4) tRCD [10:8] MCLK 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1

W90N740 Publication Release Date: November 26, 2004 - 51 - Revision A4 tRP [5:3] ：SDRAM bank 0/1, Row pre-charge time (see Fig 7.3.4) tRP [5:3] MC

W90N740 - 52 - tRAS [2:0] ：SDRAM bank 0/1, Row active time (see Fig 7.3.4) tRAS [2:0] MCLK 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1

W90N740 Publication Release Date: November 26, 2004 - 53 - Revision A4 External I/O Control Registers（EXT0CON – EXT3CON） The W90N740 supports an ex

W90N740 - 54 - ADRS [15] ：Address bus alignment for external I/O bank 0~3 When ADRS is set, EBI bus is alignment to byte address format, and ignores

W90N740 Publication Release Date: November 26, 2004 - 55 - Revision A4 tACS [7:5] ：Address set-up before nECS for external I/O bank 0~3 tACS [7:5]

W90N740 - 2 - External Bus Interface (EBI) • External I/O Control with 8/16/32 bit external data bus • Cost-effective memory-to-peripheral DMA

W90N740 - 56 - Fig 7.3.6 External I/O write operation timing

W90N740 Publication Release Date: November 26, 2004 - 57 - Revision A4 Clock Skew Control Register （CKSKEW） Register Address R/W Description Rese

W90N740 - 58 - DLH_CLK_SKEW [7:4] ：Data latch clock skew adjustment DLH_CLK_SKEW [7:4] Gate Delay0 0 0 0 P-0 0 0 0 1 P-1 0 0 1 0 P-2 0 0

W90N740 Publication Release Date: November 26, 2004 - 59 - Revision A4 7.4 Cache Controller The W90N740 has an 8KB Instruction cache, 2KB Data cach

W90N740 - 60 - The cache access cycle begins with an instruction request from the instruction unit in the core. In the case of a cache hit, the instr

W90N740 Publication Release Date: November 26, 2004 - 61 - Revision A4 the ICAH bit is set. As flushing the cache line, the “V” bit of the line is

W90N740 - 62 - 7.4.4 Data Cache The W90N740 data cache (D-Cache) is a 2KB two-way set associative cache. The cache organization is 64 sets, two lines

W90N740 Publication Release Date: November 26, 2004 - 63 - Revision A4 7.4.4.3 Data Cache Flushing The W90N740 allows flushing of the data cache u

W90N740 - 64 - 7.4.5 Write Buffer The W90N740 provides a write buffer to improve system performance. The write buffer can buffer up to eight words of

W90N740 Publication Release Date: November 26, 2004 - 65 - Revision A4 Cache Configuration Register (CAHCNF) Cache controller has a configuration r

W90N740 Publication Release Date: November 26, 2004 - 3 - Revision A4 USB Host Controller • USB 1.1 compatible • Open Host Controller Interfa

W90N740 - 66 - Cache Control Register (CAHCON) Cache controller supports one Control register used to control the following operations. z Flush I-Ca

W90N740 Publication Release Date: November 26, 2004 - 67 - Revision A4 To flush the entire I-Cache/D-Cache, also flushes any locked-down code. If t

W90N740 - 68 - 7.5 Ethernet MAC Controller (EMC) The W90N740 has two Ethernet MAC Controllers (EMC) for WAN/LAN application. Each EMC has its DMA co

W90N740 Publication Release Date: November 26, 2004 - 69 - Revision A4 the ownership is granted to CPU. If NATA is enabled, NATA is also allowed to

W90N740 - 70 - 7.5.1.5 NATFSH: NAT Processing Finish The value is 1 if current packet NAT processing is finished and successful. This bit will be wr

W90N740 Publication Release Date: November 26, 2004 - 71 - Revision A4 NH_Err: No Hit Error These bits records error status if NAT processing error

W90N740 - 72 - Hit: current packet is hit with NAT entry table The value is 1 if current packet IP/port is in the entry list. If NAT is disabled, th

W90N740 Publication Release Date: November 26, 2004 - 73 - Revision A4 Tx Status (TXSTA) 31 30 29 28 27 26 25 24 CCNT SEQ PAU TXHA 23 22

W90N740 - 74 - These registers are used for loading commands generated by user, indicating transmit and receive status, buffering data to/from memory

W90N740 Publication Release Date: November 26, 2004 - 75 - Revision A4 EMC 0 Control registers, continued REGISTER ADDRESS R/W DESCRIPTION RESET

W90N740 - 4 - On-Chip PLL • One PLL for both CPU and USB host controller • The external clock can be multiplied by on-chip PLL to provide high

W90N740 - 76 - EMC 0 Status Registers Register Address R/W Description Reset ValueMAC REGISTERS MISTA_0 0xFFF0.30B4 R/W MAC Interrupt Status Regist

W90N740 Publication Release Date: November 26, 2004 - 77 - Revision A4 EMC 1 Control Registers, continued Register Address R/W Description Reset

W90N740 - 78 - EMC 1 Control Registers, continued Register Address R/W Description Reset ValueDMA REGISTERS TXDLSA_1 0xFFF0.389C R/W Transmit Descr

W90N740 Publication Release Date: November 26, 2004 - 79 - Revision A4 CAM Command Register (CAMCMR_0, CAMCMR_1) The three accept bits in the CAMCM

W90N740 - 80 - AMP [1]: Accept Multicast Packet

W90N740 Publication Release Date: November 26, 2004 - 81 - Revision A4 CAM Address Registers (CAMxx_0, CAMxx_1) There are 16 entries for the Destin

W90N740 - 82 - {CAMxM, CAMxL} : destination address (6 byte), with 2 bytes in CAMxL and 4 bytes in CAMxM, (CAM15M and CAM15L excluded). For example

W90N740 Publication Release Date: November 26, 2004 - 83 - Revision A4 MAC Interrupt Enable Register (MIEN_0, MIEN_1) Register Address R/W Descr

W90N740 - 84 - Set this bit to enable the interrupt, which is generated to indicate 16 collisions occur while transmitting the same packet. EnNCS [20

W90N740 Publication Release Date: November 26, 2004 - 85 - Revision A4 Set this bit to enable the interrupt, which is generated if there is no erro

W90N740 Publication Release Date: November 26, 2004 - 5 - Revision A4 3. BLOCK DIAGRAM ARM7TDMI CacheControllerWrapperAPBBridgeAHBArbiterAHBDecoder

W90N740 - 86 - EnRXGD [4]: Enable Receive Good interrupt Default value: 0 Set this bit to enable the interrupt, which is generated if a packet was su

W90N740 Publication Release Date: November 26, 2004 - 87 - Revision A4 MAC Command Register (MCMDR_0, MCMDR_1) The MAC command register provides gl

W90N740 - 88 - MAC 1 BIT [23:22] LPCS: ENRMII MAC 0 BIT [23:22] LPCS*1: ENRMII MAC 1 INTERFACEMAC 0 INTERFACENOTE 00 X0 MII MII 00 X1 MII RMII 01 X0

W90N740 Publication Release Date: November 26, 2004 - 89 - Revision A4 SPCRC [5]: Accept Strip CRC Value Default value: 0 Set this bit to enable MA

W90N740 - 90 - MAC MII Management Data Register (MIID_0, MIID_1) W90N740 provides MII management function to let user access the registers of the ex

W90N740 Publication Release Date: November 26, 2004 - 91 - Revision A4 MAC MII Management Data Control and Address Register (MIIDA_0, MIIDA_1) Regi

W90N740 - 92 - Users should set the MDC clock setting to meet the PHY requirement (maximum 2.5MHz). Besides, the MCLK (HCLK) frequency ranges from 10

W90N740 Publication Release Date: November 26, 2004 - 93 - Revision A4 MAC Missed Packet Count register (MPCNT_0, MPCNT_1) The value in the MAC Mis

W90N740 - 94 - DMA Transmit Descriptor Link-list Start Address Register (TXDLSA_0, TXDLSA_1) Register Address R/W Description Reset Value TXDLSA_0

W90N740 Publication Release Date: November 26, 2004 - 95 - Revision A4 DMA Receive Descriptor Link List Start Address Register (RXDLSA_0, RXDLSA_1)