Rainbow-electronics AT6010LV User Manual

1Features• High-performance– System Speeds > 100 MHz– Flip-flop Toggle Rates > 250 MHz– 1.2 ns/1.5 ns Input Delay– 3.0 ns/6.0 ns Output Delay• U

AT6000(LV) Series10memory to configure the FPGA. Addresses change afterthe rising edge of the CCLK signal.CSOUT or I/OWhen cascading devices, CSOUT is

AT6000(LV) Series11Pinout AssignmentLeft Side (Top to Bottom)AT6002 AT6003 AT6005 AT601084 PLCC100 VQFP132 PQFP144 TQFP180 CPGA208 PQFP240 PQFP---I/O5

AT6000(LV) Series12Notes: 1. PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12.2. GND = Pins connected to ground plane = L4,

AT6000(LV) Series13Pinout AssignmentBottom Side (Left to Right)AT6002 AT6003 AT6005 AT601084 PLCC100 VQFP132 PQFP144 TQFP180 CPGA208 PQFP240 PQFPCONCO

AT6000(LV) Series14Notes: 1. PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12.2. GND = Pins connected to ground plane = L4,

AT6000(LV) Series15Pinout AssignmentRight Side (Bottom to Top)AT6002 AT6003 AT6005 AT601084 PLCC100 VQFP132 PQFP144 TQFP180 CPGA208 PQFP240 PQFP- - -

AT6000(LV) Series16Notes: 1. PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12.2. GND = Pins connected to ground plane = L4,

AT6000(LV) Series17Pinout AssignmentTop Side (Right to Left)AT6002 AT6003 AT6005 AT601084 PLCC100 VQFP132 PQFP144 TQFP180 CPGA208 PQFP240 PQFPM1 M1 M1

AT6000(LV) Series18Notes: 1. PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12.2. GND = Pins connected to ground plane = L4,

AT6000(LV) Series19AC Timing Characteristics – 5V Operation Notes: 1. TTL buffer delays are measured from a VIH of 1.5V at the pad to the internal VIH

AT6000(LV) Series2Devices range in size from 4,000 to 30,000 usable gates,and 1024 to 6400 registers. Pin locations are consistentthroughout the AT600

AT6000(LV) Series20AC Timing Characteristics – 3.3V Operation Notes: 1. TTL buffer delays are measured from a VIH of 1.5V at the pad to the internal V

AT6000(LV) Series21Absolute Maximum Ratings*Supply Voltage (VCC) ...-0.5V to + 7.0V*NOTICE: Stresses beyond those

AT6000(LV) Series22DC Characteristics – 5V OperationSymbol Parameter Conditions Min Max UnitsVIHHigh-level Input Voltage CommercialCMOS 70% VCCVCCVTTL

AT6000(LV) Series23Note: 1. Parameter based on characterization and simulation; it is not tested in production.Device Timing: During OperationDC Chara

AT6000(LV) Series24Ordering Information – AT6002Usable GatesSpeedGrade (ns) Ordering Code Package Operation Range6,000 2 AT6002-2ACAT6002A-2ACAT6002-2

AT6000(LV) Series25Ordering Information – AT6003Usable GatesSpeedGrade (ns) Ordering Code Package Operation Range9,000 2 AT6003-2ACAT6003A-2ACAT6003-2

AT6000(LV) Series26Ordering Information – AT6005Usable GatesSpeedGrade (ns) Ordering Code Package Operation Range15,000 2 AT6005-2ACAT6005A-2ACAT6005-

AT6000(LV) Series27Ordering Information – AT6010Usable GatesSpeedGrade (ns) Ordering Code Package Operation Range30,000 2 AT6010-2JCAT6010A-2ACAT6010-

© Atmel Corporation 1999.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa

AT6000(LV) Series3Figure 2. Busing Network (one sector)Figure 3. Cell-to-cell and Bus-to-bus ConnectionsCELLREPEATER

AT6000(LV) Series4Each cell, in addition, provides the ability to route a signalon a 90° turn between the NS1 bus and EW1 bus andbetween the NS2 bus a

AT6000(LV) Series5In addition to the four local-bus connections, a cell receivestwo inputs and provides two outputs to each of itsNorth (N), South (S)

AT6000(LV) Series6Figure 5. Combinatorial Physical StatesFigure 6. Register StatesFigure 7. Physical ConstantsFigure 8. Two-input AND Feeding XORF

AT6000(LV) Series7Clock DistributionAlong the top edge of the array is logic for distributing clocksignals to the D flip-flop in each logic cell (Figu

AT6000(LV) Series8Figure 11. A-type I/O LogicFigure 12. B-type I/O LogicTTL/CMOS InputsA user-configurable bit determines the threshold level –TTL o

AT6000(LV) Series9The devices can be partially reconfigured while in opera-tion. Portions of the device not being modified remainoperational during re