Rainbow-electronics AT25640A User Manual

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1
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
Data Sheet Describes Mode 0 Operation
Medium-voltage and Standard-voltage Operation
5.0 (V
CC
= 4.5V to 5.5V)
2.7 (V
CC
= 2.7V to 5.5V)
5.0 MHz Clock Rate (5V)
32-byte Page Mode
Block Write Protection
Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software
Data Protection
Self-timed Write Cycle (2 ms [5V] typical)
High Reliability
Endurance: One Million Write Cycles
Data Retention: 100 Years
8-lead PDIP and 8-lead JEDEC SOIC Packages
Description
The AT25080A/160A/320A/640A provides 8192/16384/32768/65536 bits of serial
electrically-erasable programmable read-only memory (EEPROM) organized as
1024/2048/4096/8192 words of 8 bits each. The device is optimized for use in many
automotive applications where low-power and low-voltage operation are essential.
The AT25080A/160A/320A/640A is available in space saving 8-lead PDIP and 8-lead
JEDEC SOIC packages.
The AT25080A/160A/320A/640A is enabled through the Chip Select pin (CS
) and
accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data
Output (SO), and Serial Clock (SCK). All programming cycles are completely self-
timed, and no separate erase cycle is required before write.
Block write protection is enabled by programming the status register with one of four blocks
of write protection. Separate program enable and program disable instructions are provided
for additional data protection. Hardware data protection is provided via the WP
pin to protect
against inadvertent write attempts to the status register. The HOLD
pin may be used to sus-
pend any serial communication without resetting the serial sequence.
Table 1. Pin Configuration
Pin Name Function
CS
Chip Select
SCK Serial Data Clock
SI Serial Data Input
SO Serial Data Output
GND Ground
VCC Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
NC No Connect
DC Don’t Connect
SPI Serial
Automotive
EEPROMs
8K (1024 x 8)
16K (2048 x 8)
32K (4096 x 8)
64K (8192 x 8)
AT25080A
AT25160A
AT25320A
AT25640A
3401C–SEEPR–8/04
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
8-lead PDIP
8-lead SOIC
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Summary of Contents

Page 1 - Description

1Features• Serial Peripheral Interface (SPI) Compatible• Supports SPI Modes 0 (0,0) and 3 (1,1)– Data Sheet Describes Mode 0 Operation• Medium-voltage

Page 2

10AT25080A/160A/320A/640A3401C–SEEPR–8/04Timing DiagramsFigure 3. Synchronous Data Timing (for Mode 0) Figure 4. WREN Timing Figure 5. WRDI Timin

Page 3

11AT25080A/160A/320A/640A3401C–SEEPR–8/04Figure 6. RDSR Timing Figure 7. WRSR Timing CSSCK01234567891011121314SIINSTRUCTIONSO76543210DATA OUTMSBHI

Page 4

12AT25080A/160A/320A/640A3401C–SEEPR–8/04Figure 8. READ Timing Figure 9. WRITE Timing Figure 10. HOLD Timing CSSCKSISO000111222333...44556677891

Page 5

13AT25080A/160A/320A/640A3401C–SEEPR–8/04 AT25080A Ordering InformationOrdering Code Package Operation RangeAT25080A-10PA-5.0CAT25080AN-10SA-5.0C8P38S

Page 6

14AT25080A/160A/320A/640A3401C–SEEPR–8/04AT25160A Ordering InformationOrdering Code Package Operation RangeAT25160A-10PA-5.0CAT25160AN-10SA-5.0C8P38S1

Page 7

15AT25080A/160A/320A/640A3401C–SEEPR–8/04AT25320A Ordering InformationOrdering Code Package Operation RangeAT25320A-10PA-5.0CAT25320AN-10SA-5.0C8P38S1

Page 8

16AT25080A/160A/320A/640A3401C–SEEPR–8/04AT25640A Ordering InformationOrdering Code Package Operation RangeAT25640A-10PA-5.0CAT25640AN-10SA-5.0C8P38S1

Page 9

17AT25080A/160A/320A/640A3401C–SEEPR–8/04Packaging Information8P3 – PDIP 2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 8P3, 8-lead, 0.

Page 10 - AT25080A/160A/320A/640A

18AT25080A/160A/320A/640A3401C–SEEPR–8/048S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd.Colorado Springs, CO 80906TITLEDRAWING NO.RREV. Note:10/7/038S1

Page 11

Printed on recycled paper.3401C–SEEPR–8/04Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly con

Page 12

2AT25080A/160A/320A/640A3401C–SEEPR–8/04 Figure 1. Block Diagram Absolute Maximum Ratings*Operating Temperature...

Page 13

3AT25080A/160A/320A/640A3401C–SEEPR–8/04Table 2. Pin Capacitance(1) Note: 1. This parameter is characterized and is not 100% tested.Table 3. DC Cha

Page 14

4AT25080A/160A/320A/640A3401C–SEEPR–8/04Note: 1. This parameter is characterized and is not 100% tested. Table 4. AC Characteristics Applicable over

Page 15

5AT25080A/160A/320A/640A3401C–SEEPR–8/04Serial Interface DescriptionMASTER: The device that generates the serial clock.SLAVE: Because the Serial Clock

Page 16

6AT25080A/160A/320A/640A3401C–SEEPR–8/04Figure 2. SPI Serial InterfaceAT25080A/160A/320A/640A

Page 17

7AT25080A/160A/320A/640A3401C–SEEPR–8/04Functional DescriptionThe AT25080A/160A/320A/640A is designed to interface directly with the synchronous seria

Page 18

8AT25080A/160A/320A/640A3401C–SEEPR–8/04WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one offour levels of protection.

Page 19 - Regional Headquarters

9AT25080A/160A/320A/640A3401C–SEEPR–8/04READ SEQUENCE (READ): Reading the AT25080A/160A/320A/640A via the serial output(SO) pin requires the following

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