1Features• Serial Peripheral Interface (SPI) Compatible• Supports SPI Modes 0 (0,0) and 3 (1,1)– Data Sheet Describes Mode 0 Operation• Medium-voltage
10AT25080A/160A/320A/640A3401C–SEEPR–8/04Timing DiagramsFigure 3. Synchronous Data Timing (for Mode 0) Figure 4. WREN Timing Figure 5. WRDI Timin
11AT25080A/160A/320A/640A3401C–SEEPR–8/04Figure 6. RDSR Timing Figure 7. WRSR Timing CSSCK01234567891011121314SIINSTRUCTIONSO76543210DATA OUTMSBHI
12AT25080A/160A/320A/640A3401C–SEEPR–8/04Figure 8. READ Timing Figure 9. WRITE Timing Figure 10. HOLD Timing CSSCKSISO000111222333...44556677891
13AT25080A/160A/320A/640A3401C–SEEPR–8/04 AT25080A Ordering InformationOrdering Code Package Operation RangeAT25080A-10PA-5.0CAT25080AN-10SA-5.0C8P38S
14AT25080A/160A/320A/640A3401C–SEEPR–8/04AT25160A Ordering InformationOrdering Code Package Operation RangeAT25160A-10PA-5.0CAT25160AN-10SA-5.0C8P38S1
15AT25080A/160A/320A/640A3401C–SEEPR–8/04AT25320A Ordering InformationOrdering Code Package Operation RangeAT25320A-10PA-5.0CAT25320AN-10SA-5.0C8P38S1
16AT25080A/160A/320A/640A3401C–SEEPR–8/04AT25640A Ordering InformationOrdering Code Package Operation RangeAT25640A-10PA-5.0CAT25640AN-10SA-5.0C8P38S1
17AT25080A/160A/320A/640A3401C–SEEPR–8/04Packaging Information8P3 – PDIP 2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 8P3, 8-lead, 0.
18AT25080A/160A/320A/640A3401C–SEEPR–8/048S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd.Colorado Springs, CO 80906TITLEDRAWING NO.RREV. Note:10/7/038S1
Printed on recycled paper.3401C–SEEPR–8/04Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly con
2AT25080A/160A/320A/640A3401C–SEEPR–8/04 Figure 1. Block Diagram Absolute Maximum Ratings*Operating Temperature...
3AT25080A/160A/320A/640A3401C–SEEPR–8/04Table 2. Pin Capacitance(1) Note: 1. This parameter is characterized and is not 100% tested.Table 3. DC Cha
4AT25080A/160A/320A/640A3401C–SEEPR–8/04Note: 1. This parameter is characterized and is not 100% tested. Table 4. AC Characteristics Applicable over
5AT25080A/160A/320A/640A3401C–SEEPR–8/04Serial Interface DescriptionMASTER: The device that generates the serial clock.SLAVE: Because the Serial Clock
6AT25080A/160A/320A/640A3401C–SEEPR–8/04Figure 2. SPI Serial InterfaceAT25080A/160A/320A/640A
7AT25080A/160A/320A/640A3401C–SEEPR–8/04Functional DescriptionThe AT25080A/160A/320A/640A is designed to interface directly with the synchronous seria
8AT25080A/160A/320A/640A3401C–SEEPR–8/04WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one offour levels of protection.
9AT25080A/160A/320A/640A3401C–SEEPR–8/04READ SEQUENCE (READ): Reading the AT25080A/160A/320A/640A via the serial output(SO) pin requires the following
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