1Features• Integrated PLL Loop Filter• ESD Protection (4 kV HBM/ 200 V MM; Except Pin 2: 4 kV HBM/ 100 V MM) also at ANT1/ANT2• High Output Power (7.5
10T5754 4511D–RKE–08/02Package Information Ordering InformationExtended Type Number Package RemarksT5754-6AQ TSSOP8L Taped and reeled
Printed on recycled paper.© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than those expressly contai
2T5754 4511D–RKE–08/02Pin ConfigurationFigure 2. Pinning TSSOP8L 12348765CLKPA_ENABLEANT2ANT1ENABLEGNDVSXTALT5754Pin DescriptionPin Symbol Function
3T57544511D–RKE–08/02Figure 3. Block Diagram General Description This fully integrated PLL transmitter allows particularly simple, low-cost RF miniat
4T5754 4511D–RKE–08/02Functional DescriptionIf ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode consuming onlya very small amount of
5T57544511D–RKE–08/02Output Matching and Power SettingThe output power is set by the load impedance of the antenna. The maximum outputpower is achieve
6T5754 4511D–RKE–08/02Figure 6. ASK Application CircuitCLKPA_ENABLEANT2ANT1ENABLEGNDVSXTAL1234 5678VCOLFCPPFDf32XTOPLLPAf4Power up / downM4xCx9xC3VS
7T57544511D–RKE–08/02Figure 7. FSK Application CircuitCLKPA_ENABLEANT2ANT1ENABLEGNDVSXTAL1234 5678VCOLFCPPFDf32XTOPLLPAf4Power up / downM4xCx9xC3VSC1
8T5754 4511D–RKE–08/02Figure 8. ESD Protection CircuitCLK PA_ENABLEANT2ANT1XTAL ENABLEVSGNDAbsolute Maximum RatingsParameters Symbol Minimum Maximum
9T57544511D–RKE–08/02Output power variation for the full temperature rangeTamb = -40°C to +85°C,VS = 3.0 VVS = 2.0 VDPRefDPRef-1.5-4.0dBdBOutput power
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