Rainbow-electronics DS26519 User Manual Page 149
- Page / 310
- Table of contents
- BOOKMARKS
- DS26519 1
- 16-Port T1/E1/J1 Transceive 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 5
- LIST OF TABLES 7
- 1. DETAILED DESCRIPTION 9
- 2. FEATURE HIGHLIGHTS 10
- 2.5 Framer/Formatter 11
- 2.6 System Interface 11
- 2.7 HDCL Controllers 12
- 2.8 Test and Diagnostics 12
- 3. APPLICATIONS 13
- 4. SPECIFICATIONS COMPLIANCE 14
- 5. ACRONYMS AND GLOSSARY 16
- 6. MAJOR OPERATING MODES 17
- 7. BLOCK DIAGRAMS 18
- 19 of 310 19
- 8. PIN DESCRIPTIONS 20
- 21 of 310 21
- 22 of 310 22
- 23 of 310 23
- 24 of 310 24
- 25 of 310 25
- 26 of 310 26
- 27 of 310 27
- 28 of 310 28
- 29 of 310 29
- 30 of 310 30
- 31 of 310 31
- 32 of 310 32
- 9. FUNCTIONAL DESCRIPTION 33
- Table 9-2. Reset Functions 38
- 9.7 Device Interrupts 41
- 9.8.1 Elastic Stores 43
- 9.8.2 IBO Multiplexing 46
- 9.9 Framers 58
- Table 9-11. D4 Framing Mode 58
- Table 9-12. ESF Framing Mode 59
- Table 9-13. SLC-96 Framing 59
- 60 of 310 60
- 9.9.2 E1 Framing 61
- 9.9.4 Signaling 64
- 9.9.4.2.2 Change of State 66
- 9.9.5 T1 Data Link 69
- 9.9.6 E1 Data Link 71
- 9.9.7.1.1 Real-Time Bits 74
- 9.9.7.1.2 Latched Bits 74
- 9.9.7.1.3 Mask Bits 74
- 9.9.8 Alarms 75
- 9.9.9 Error Count Registers 77
- 9.9.13 Per-Channel Loopback 80
- 9.10 HDLC Controllers 84
- 86 of 310 86
- 88 of 310 88
- 9.11 Power-Supply Decoupling 89
- 9.12.1 LIU Operation 92
- 9.12.2 Transmitter 93
- T1.102/87, T1.403 94
- CB 119 (Oct. 79), & 94
- I.431 Template 94
- 95 of 310 95
- 9.12.3 Receiver 97
- SWITCHING 101
- CONTROL 101
- 9.12.5 Jitter Attenuator 102
- Figure 9-28. Analog Loopback 103
- Transmit 104
- Receive 104
- Figure 9-31. Dual Loopback 105
- 9.13.2 BERT Error Counter 107
- 10. DEVICE REGISTERS 108
- 10.1.1 Global Register List 109
- 10.1.2 Framer Register List 110
- TSSYNCIOSEL 118
- 120 of 310 120
- — — — — — — 120
- 121 of 310 121
- 122 of 310 122
- — — — — — — — — 122
- 123 of 310 123
- 124 of 310 124
- 125 of 310 125
- 126 of 310 126
- 127 of 310 127
- 10.2.3 LIU Register Bit Map 128
- Register Name 131
- Register Description: 131
- Register Address: 131
- Channels: 131
- Register Name: 133
- Description: 133
- — RSYSCLKSEL TSYSCLKSEL 139
- Note: See RIM7 for E1 Mode 203
- Note: See RIM7 for T1 Mode 203
- TSYNCINV TSSYNCINV 233
- Register Addresses: 251
- 11. FUNCTIONAL TIMING 268
- CHANNEL 1 CHANNEL 2 274
- CHANNEL 1 CHANNEL 24 274
- CHANNEL 23 274
- CHANNEL 1 CHANNEL 32 275
- CHANNEL 31 275
- LSB MSB LSB MSB 282
- LSB F MSBLSB MSB 283
- CHANNEL 26 286
- CHANNEL 25 286
- 12. OPERATING PARAMETERS 287
- ABSOLUTE MAXIMUM RATINGS 287
- 12.1 Thermal Characteristics 288
- With 100pF on all SPI pins 289
- 290 of 310 290
- T1 Mode 294
- E1 Mode 294
- RSYSCLKn = 1.544MHz 294
- RSYSCLKn = 2.048MHz 294
- Figure 13-11. BPCLKn Timing 299
- 13.2 JTAG Interface Timing 300
- 10kΩ 10kΩ 10k 302
- 305 of 310 305
- 14.2 Instruction Register 306
- 14.3 JTAG ID Codes 307
- 14.4 Test Registers 307
- 15. PIN CONFIGURATION 308
- 16. PACKAGE INFORMATION 309
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