Rainbow-electronics DS31256 User Manual

1 of 181 112102 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions

DS31256 10 of 181 Figure 2-1. Block Diagram RC2RD2TC2TD2JTDOPCLKPAD[31:0]PRSTPCBE[3:0]PPAR PFRAMEPIRDYPTRDYPSTOPPIDSELPDEVSELPREQPGNTPPERRPSERR

DS31256 100 of 181 buffers have been filled or wait until the completed packet data has been written. The DMA always writes to the done queue when it

DS31256 101 of 181 Register Name: RDQFFT Register Description: Receive Done-Queue FIFO Flush Timer Register Address: 0744h Bit # 7 6 5 4 3 2 1 0

DS31256 102 of 181 Bits 8 to 10/Receive Done-Queue Status-Bit Threshold Setting (RDQT0 to RDQT2). These bits determine when the DMA sets the receive

DS31256 103 of 181 - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD - dword 0; Bits 0 to 31/Current Data Buffer Address. The current 32-bit address

DS31256 104 of 181 - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD - dword 2; Bits 16 to 28/Byte Count. The DMA uses these 13 bits to keep track of

DS31256 105 of 181 ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the write op

DS31256 106 of 181 Table 9-G. Transmit DMA Main Operational Areas DESCRIPTORS FUNCTION SECTION Packet A dedicated area of memory that describes the

DS31256 107 of 181 1) Priority packets are transmitted as soon as the current standard packet (not packet chain) finishes transmission. 2) All prio

DS31256 108 of 181 Figure 9-10. Transmit DMA Operation 00h08hDone-Queue Descriptors(circular queue)04hFree Desc. Ptr.CH#5StatusFree Desc. Ptr.CH#1S

DS31256 109 of 181 Figure 9-11. Transmit DMA Memory Organization Free Data Buffer SpaceTransmit Pending-Queue Descriptors: Contains Index Pointers

DS31256 11 of 181 Restrictions In creating the overall system architecture, the user must balance the port, throughput, and HDLC channel restrictions

DS31256 110 of 181 Figure 9-12. Transmit DMA Packet Handling Buffer 1Packet 11st Descriptor(EOF=0/CV=0)Buffer 2Packet 12nd Descriptor(EOF=0/CV=0)B

DS31256 111 of 181 Figure 9-13. Transmit DMA Priority Packet Handling Buffer 1 Packet 1 1st Descriptor (EOF=0/CV=0) Buffer 2 Packet 1 2nd Descript

DS31256 112 of 181 DMA Updates to the Done Queue The host has two options for when the transmit DMA should write descriptors that have completed tran

DS31256 113 of 181 descriptor pointer and PV fields in the packet descriptor to 0 to ready them for transmission). The second option allows the softw

DS31256 114 of 181 9.3.2 Packet Descriptors A contiguous section of up to 65,536 quad dwords that make up the transmit packet descriptors resides in

DS31256 115 of 181 Figure 9-16. Transmit Packet Descriptors dword 0 Data Buffer Address (32) dword 1 EOF CV unused Byte Count (13) Next Descript

DS31256 116 of 181 9.3.3 Pending Queue The host writes to the transmit pending queue the location of the readied descriptor, channel number, and cont

DS31256 117 of 181 The transmit DMA reads from the transmit pending-queue descriptor circular queue which data buffers and their associated descripto

DS31256 118 of 181 Figure 9-18. Transmit Pending-Queue Structure Once the transmit DMA is activated (by setting the TDE contr

DS31256 119 of 181 read pointer, and sets the status bit for transmit DMA pending-queue read (TPQR) in the status register for DMA (SDMA). See Sectio

DS31256 12 of 181 Table 2-B. Initialization Steps INITIALIZATION STEP COMMENTS 1) Initialize the PCI configuration registers Achieved by asserting

DS31256 120 of 181 9.3.4 Done Queue The DMA writes to the transmit done queue when it has finished either transmitting a complete packet chain or a c

DS31256 121 of 181 The host reads from the transmit done queue to find which data buffers and their associated descriptors have completed transmissio

DS31256 122 of 181 Figure 9-20. Transmit Done-Queue Structure Once the transmit DMA is activated (through the TDE control bit

DS31256 123 of 181 When enabled through the transmit done-queue FIFO-enable (TDQFE) bit, the done-queue FIFO does not write to the done queue until i

DS31256 124 of 181 Register Name: TDMAQ Register Description: Transmit DMA Queues Control Register Address: 0880h Bit # 7 6 5 4 3 2 1 0 Name n/

DS31256 125 of 181 9.3.5 DMA Configuration RAM The device contains an on-board set of 1536 dwords (6 dwords per channel times 256 channels) that are

DS31256 126 of 181 - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD - dword 0; Bits 0 to 31/Current Data Buffer Address. This is the current 32-bit a

DS31256 127 of 181 - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD - dword 1; Bits 20 to 21/Priority State (PRIST). This field is used by the transm

DS31256 128 of 181 - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD - dword 5; Bits 16 to 31/Next Priority Pending Descriptor Pointer. This 16-bit va

DS31256 129 of 181 Register Name: TDMAC Register Description: Transmit DMA Configuration Register Address: 0874h Bit # 7 6 5 4 3 2 1 0 Name D7 D

DS31256 13 of 181 3. SIGNAL DESCRIPTION 3.1 Overview/Signal List This section describes the input and output signals on the DS31256. Signal names fo

DS31256 130 of 181 10. PCI BUS 10.1 General Description of Operation The PCI block interfaces the DMA block to an external high-speed bus. The PCI b

DS31256 131 of 181 10.1.1 PCI Read Cycle A read cycle on the PCI bus is shown in Figure 10-2. During clock cycle #1, the initiator asserts the PFRAM

DS31256 132 of 181 10.1.2 PCI Write Cycle A write cycle on the PCI bus is shown in Figure 10-3. During clock cycle #1, the initiator asserts the PFR

DS31256 133 of 181 10.1.3 PCI Bus Arbitration The PCI bus can be arbitrated as shown in Figure 10-4. The initiator requests bus access by asserting P

DS31256 134 of 181 10.1.5 PCI Target Retry Targets can terminate the requested bus transaction before any data is transferred because the target is

DS31256 135 of 181 10.1.7 PCI Target Abort Targets can also abort the current transaction, which means they do not wish for the initiator to attempt

DS31256 136 of 181 10.1.8 PCI Fast Back-to-Back Fast back-to-back transactions are two consecutive bus transactions without the usually required idl

DS31256 137 of 181 10.2 PCI Configuration Register Description Register Name: PVID0 Register Description: PCI Vendor ID/Device ID Register 0 Regi

DS31256 138 of 181 10.2.1 Command Bits (PCMD0) Bit 0/I/O Space Control (IOC). This read-only bit is forced to 0 by the device to indicate that it d

DS31256 139 of 181 10.2.2 Status Bits (PCMD0) The upper word in the PCMD0 register is the status portion, which reports events as they occur. As pr

DS31256 14 of 181 PIN NAME TYPE FUNCTION T20 LD4 I/O Local Bus Data Bit 4 R18 LD5 I/O Local Bus Data Bit 5 P17 LD6 I/O Local Bus Data Bit 6

DS31256 140 of 181 Register Name: PRCC0 Register Description: PCI Revision ID/Class Code Register 0 Register Address: 0x008h LSB Revision ID (Rea

DS31256 141 of 181 Register Name: PDCM Register Description: PCI Device Configuration Memory Base Address Register Register Address: 0x010h LSB B

DS31256 142 of 181 Register Name: PVID1 Register Description: PCI Vendor ID/Device ID Register 1 Register Address: 0x100h LSB Vendor ID (Read Onl

DS31256 143 of 181 10.2.3 Command Bits (PCMD1) Bit 0/I/O Space Control (IOC). This read-only bit is forced to 0 by the device to indicate that it d

DS31256 144 of 181 10.2.4 Status Bits (PCMD1) The upper word in the PCMD1 register is the status portion, which reports events as they occur. As men

DS31256 145 of 181 Register Name: PRCC1 Register Description: PCI Revision ID/Class Code Register 1 Register Address: 0x108h LSB Revision ID (Rea

DS31256 146 of 181 Register Name: PLBM Register Description: PCI Local Bus Memory Base Address Register Register Address: 0x110h LSB Base Address

DS31256 147 of 181 11. LOCAL BUS 11.1 General Description The local bus can operate in two modes, either as a PCI bridge (master mode) or as a confi

DS31256 148 of 181 Figure 11-1. Bridge Mode Figure 11-2. Bridge Mode with Arbitration Enabled T1 / E1 Framer or Transceiver Local B

DS31256 149 of 181 Figure 11-3. Configuration Mode 11.1.1 PCI Bridge Mode In PCI bridge mode, data from the PCI bus can be tra

DS31256 15 of 181 PIN NAME TYPE FUNCTION W5 PAD27 I/O PCI Multiplexed Address and Data Bit 27 V5 PAD28 I/O PCI Multiplexed Address and Data Bi

DS31256 150 of 181 Table 11-B. Local Bus 8-Bit Width Address, LBHE Setting PCBE [3:0] A1 A0 LBHE 1110 0 0 1 1101 0 1 1 1011 1 0 1 0111 1 1 1 N

DS31256 151 of 181 Bridge Mode Bus Transaction Timing When the local bus is operated in PCI bridge mode, the bus transaction time can be determined

DS31256 152 of 181 Figure 11-4. Local Bus Access Flowchart PCI Host Initiates aLocal Bus AccessIs Arbitration Enabledfor the Local Bus?Is the Loc

DS31256 153 of 181 11.2 Local Bus Bridge Mode Control Register Description Register Name: LBBMC Register Description: Local Bus Bridge Mode Cont

DS31256 154 of 181 Bit 6/Local Bus Width (LBW) 0 = 16 bits 1 = 8 bits Bits 8 to 11/Local Bus Arbitration Timer Setting (LAT0 to LAT3). These fou

DS31256 155 of 181 11.3 Examples of Bus Timing for Local Bus PCI Bridge Mode Operation Figure 11-5. 8-Bit Read Cycle Intel Mode (LIM = 0) Arbitrati

DS31256 156 of 181 Figure 11-6. 16-Bit Write Cycle Intel Mode (LIM = 0) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 4 LCLK (LRDY = 0100)

DS31256 157 of 181 Figure 11-7. 8-Bit Read Cycle Intel Mode (LIM = 0) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDY (LRDY

DS31256 158 of 181 Figure 11-8. 16-Bit Write (Only Upper 8 Bits Active) Cycle Intel Mode (LIM = 0) Arbitration Disabled (LARBE = 0) Bus Transaction

DS31256 159 of 181 Figure 11-9. 8-Bit Read Cycle Motorola Mode (LIM = 1) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 6 LCLK (LRDY = 0110)

DS31256 16 of 181 PIN NAME TYPE FUNCTION C15 RD9 I Receive Serial Data for Port 9 A14 RD10 I Receive Serial Data for Port 10 B12 RD11 I Rec

DS31256 160 of 181 Figure 11-10. 8-Bit Write Cycle Motorola Mode (LIM = 1) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 6 LCLK (LRDY = 011

DS31256 161 of 181 Figure 11-11. 16-Bit Read Cycle Motorola Mode (LIM = 1) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDY (

DS31256 162 of 181 Figure 11-12. 8-Bit Write Cycle Motorola Mode (LIM = 1) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDY (

DS31256 163 of 181 12. JTAG 12.1 JTAG Description The DS31256 supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional p

DS31256 164 of 181 12.2 TAP Controller State Machine Description This section details the operation of the TAP controller state machine. See Figure

DS31256 165 of 181 Test-Logic-Reset. The TAP controller is in the Test-Logic-Reset state upon DS31256 power-up. The instruction register contains the

DS31256 166 of 181 well as all test registers remain at their previous states. A rising edge on JTCLK with JTMS high moves the controller to the Exit

DS31256 167 of 181 BYPASS. When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the 1-bit by

DS31256 168 of 181 13. AC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Voltage on Any Lead with Respect to VSS (except VDD) -0.3V to 5.5VSupply Voltage

DS31256 169 of 181 AC CHARACTERISTICS: LAYER 1 PORTS (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS (Note 9)

DS31256 17 of 181 PIN NAME TYPE FUNCTION C7 TD13 O Transmit Serial Data for Port 13 A4 TD14 O Transmit Serial Data for Port 14 B3 TD15 O Tr

DS31256 170 of 181 AC CHARACTERISTICS: LOCAL BUS IN BRIDGE MODE (LMS = 0) (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN T

DS31256 171 of 181 AC CHARACTERISTICS: LOCAL BUS IN CONFIGURATION MODE (LMS = 1) (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITION

DS31256 172 of 181 Figure 13-3. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams t9Address ValidData Vali

DS31256 173 of 181 Figure 13-4. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams (continued) Addres

DS31256 174 of 181 AC CHARACTERISTICS: PCI BUS INTERFACE (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PCLK

DS31256 175 of 181 AC CHARACTERISTICS: JTAG TEST PORT INTERFACE (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNI

DS31256 176 of 181 14. MECHANICAL DIMENSIONS 14.1 256 PBGA Package

DS31256 177 of 181 15. APPLICATIONS This section describes some possible applications for the DS31256. There are numerous potential configurations bu

DS31256 178 of 181 Figure 15-3. Quad T1/E1 Connection 15.1 16 Port T1 or E1 with 256 HDLC Channel Support Figure 15-4 shows an application whe

DS31256 179 of 181 15.2 Dual T3 with 256 HDLC Channel Support Figure 15-5 shows an application where two T3 lines are interfaced to a single DS31256

DS31256 18 of 181 3.2 Serial Port Interface Signal Description Signal Name: RC0 to RC15 Signal Description: Receive Serial Clock Signal Type:

DS31256 180 of 181 15.3 Single T3 with 512 HDLC Channel Support Figure 15-6 shows an application where a T3 line is interfaced to two DS31256s. The

DS31256 181 of 181 15.4 Single T3 with 672 HDLC Channel Support Figure 15-7 shows an application where a fully channelized T3 line is interfaced to

DS31256 19 of 181 Signal Name: TS0 to TS15 Signal Description: Transmit Serial Data Synchronization Pulse Signal Type: Input This is a one-TC

DS31256 2 of 181 TABLE OF CONTENTS 1. MAIN FEATURES...

DS31256 20 of 181 information about the device through these signals. Only the 16-bit bus width is allowed (i.e., byte addressing is not available).

DS31256 21 of 181 Signal Name: LHLDA (LBG) Signal Description: Local Bus Hold Acknowledge (Local Bus Grant) (PCI Bridge Mode Only) Signal Type:

DS31256 22 of 181 Signal Name: JTDI Signal Description: JTAG IEEE 1149.1 Test Serial-Data Input Signal Type: Input (with internal 10kΩ pullup

DS31256 23 of 181 Signal Name: PCBE0/PCBE1/PCBE2/PCBE3 Signal Description: PCI Bus Command and Byte Enable Signal Type: Input/Output (three-st

DS31256 24 of 181 signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PSTOP is three-

DS31256 25 of 181 3.6 PCI Extension Signals These signals are not part of the normal PCI bus signal set. There are additional signals that are asser

DS31256 26 of 181 4. MEMORY MAP 4.1 Introduction All addresses within the memory map are on dword boundaries, even though all internal device config

DS31256 27 of 181 4.3 Receive Port Registers (1xx) OFFSET/ ADDRESS NAME REGISTER SECTION 0100 RP0CR Receive Port 0 Control Register 6.2 0104 RP

DS31256 28 of 181 4.5 Channelized Port Registers (3xx) OFFSET/ ADDRESS NAME REGISTER SECTION 0300 CP0RDIS Channelized Port 0 Register Data Indirect

DS31256 29 of 181 4.6 HDLC Registers (4xx) OFFSET/ ADDRESS NAME REGISTER SECTION 0400 RHCDIS Receive HDLC Channel Definition Indirect Select 7.2 0

DS31256 3 of 181 9.2.3 Free Queue ...

DS31256 30 of 181 4.9 Transmit DMA Registers (8xx) OFFSET/ ADDRESS NAME REGISTER SECTION 0800 TPQBA0 Transmit Pending-Queue Base Address 0 (lower

DS31256 31 of 181 4.11 PCI Configuration Registers for Function 0 (PIDSEL/Axx) OFFSET/ ADDRESS NAME REGISTER SECTION 0x000/0A00 PVID0 PCI Vendor I

DS31256 32 of 181 5. GENERAL DEVICE CONFIGURATION AND STATUS/INTERRUPT 5.1 Master Reset and ID Register Description The master reset and ID (MRID)

DS31256 33 of 181 Bit 0/Receive DMA Enable (RDE). This bit is used to enable the receive DMA. When it is set to 0, the receive DMA does not pass any

DS31256 34 of 181 Bits 7 to 11/BERT Port Select Bits 0 to 4 (BPS0 to BPS4). These bits select which port has the dedicated resources of the BERT. 00

DS31256 35 of 181 interrupt enable for the receive COFA (IERC) and interrupt enable for the transmit COFA (IETC) control bits in the RP[n]CR and TP[n

DS31256 36 of 181 Figure 5-1. Status Register Block Diagram for SM and SV54 Port I/F # 0#1#2#3#13#14#15#1#2#3#13#14#15OR ORReceiveORSRCOFASTCOFASB

DS31256 37 of 181 5.3.2 Status and Interrupt Register Description Register Name: SM Register Description: Status Master Register Register Address

DS31256 38 of 181 Bit 14/Status Bit for Local Bus Error (LBE). This status bit applies to the local bus when it is operated in PCI bridge mode. It is

DS31256 39 of 181 Register Name: SV54 Register Description: Status Register for the Receive V.54 Detector Register Address: 0030h Bit # 7 6 5 4

DS31256 4 of 181 LIST OF FIGURES Figure 2-1. Block Diagram...

DS31256 40 of 181 Register Name: SDMA Register Description: Status Register for DMA Register Address: 0028h Bit # 7 6 5 4 3 2 1 0 Name RLBRE

DS31256 41 of 181 Bit 8/Status Bit for Receive DMA Small Buffer Read (RSBR). This status bit is set to 1 each time the receive DMA completes a single

DS31256 42 of 181 Register Name: ISDMA Register Description: Interrupt Mask Register for SDMA Register Address: 002Ch Bit # 7 6 5 4 3 2 1 0 Nam

DS31256 43 of 181 Bit 13/Status Bit for Transmit DMA Pending-Queue Read (TPQR) 0 = interrupt masked 1 = interrupt unmasked Bit 14/Status Bit fo

DS31256 44 of 181 6. LAYER 1 6.1 General Description Figure 6-1 shows the Layer 1 block. Each of the DS31256’s 16 Layer 1 ports can be configured to

DS31256 45 of 181 The DS31256 has a set of three registers per DS0 channel for each port that determine how each DS0 channel is configured. These thr

DS31256 46 of 181 Figure 6-1. Layer 1 Block Diagram RSRCRDSLOWHDLC(OneperPort)FASTHDLCLayer OneState Machi

DS31256 47 of 181 Figure 6-2. Port Timing (Channelized and Unchannelized Applications)

DS31256 48 of 181 6.2 Port Register Descriptions Receive Side Control Bits (one each for all 16 ports) Register Name: RP[n]CR, where n = 0 to 15

DS31256 49 of 181 Bit 8/Port 0 High-Speed Mode (RP0 (1, 2) HS). If enabled, the port 0 (1, or 2) Layer 1 state machine logic is defeated, and RC0 (1,

DS31256 5 of 181 Figure 11-11. 16-Bit Read Cycle...

DS31256 50 of 181 Bit 0/Invert Clock Enable (TICE) 0 = do not invert clock (normal mode) 1 = invert clock (inverted mode) Bit 1/Invert Data Enab

DS31256 51 of 181 Bit 14/Interrupt Enable for TCOFA (IETC) 0 = interrupt masked 1 = interrupt enabled Bit 15/COFA Status Bit (TCOFA). This latc

DS31256 52 of 181 Register Name: CP[n]RDIS, where n = 0 to 15 for each port Register Description: Channelized Port [n] Register Data Indirect Sele

DS31256 53 of 181 Register Name: CP[n]RD, where n = 0 to 15 for each port Register Description: Channelized Port [n] Register Data Register Addres

DS31256 54 of 181 Bits 8 to 15/Transmit DS0 Data (TDATA). This register holds the most current DS0 byte transmitted. It is used by the receive side

DS31256 55 of 181 Bit 15/Receive DS0 Channel Enable (RCHEN). This bit must be set for each active DS0 channel in a channelized application. In a cha

DS31256 56 of 181 Bit 14/Route Data from BERT (TBERT). Setting this bit routes DS0 data to the TD pin from the BERT block instead of from the HDLC co

DS31256 57 of 181 Table 6-B. Receive V.54 Search Routine STEP DIRECTION FUNCTION 1 Set up the channel search By configuring the RV54 bit in the R[n

DS31256 58 of 181 Figure 6-5. Receive V.54 Host Algorithm Set Up theDS0 ChannelSearchToggle VRSTWait forSLBP = 1VTO = 1?Place DS0Channels intoLoopba

DS31256 59 of 181 Figure 6-6. Receive V.54 State Machine VRST = 1VLB = 0VTO = 0SLBP = 0Search forLoop UpPattern for32 VCLKsReset 4 second timer;wai

DS31256 6 of 181 1. MAIN FEATURES § Layer 1 Can simultaneously support up to 64 T1 or E1 data streams, or two T3 data streams 16 independent physic

DS31256 60 of 181 6.5 BERT The BERT block is capable of generating and detecting the following patterns: § The pseudorandom patterns 2E7, 2E11, 2E1

DS31256 61 of 181 6.6 BERT Register Description Figure 6-8. BERT Register Set BERTC0: BERT Control 0 LSBn/a TINV RINV PS2 PS1 PS0 LC RESYNC MSB

DS31256 62 of 181 Register Name: BERTC0 Register Description: BERT Control Register 0 Register Address: 0500h Bit # 7 6 5 4 3 2 1 0 Name n/a T

DS31256 63 of 181 Repetitive Pattern Length Map Length Code Length Code Length Code Length Code 17 Bits 0000 18 Bits 0001 19 Bits 0010 20

DS31256 64 of 181 EIB2 EIB1 EIB0 Error Rate Inserted 0 0 0 No errors automatically inserted 0 0 1 10E-1 0 1 0 10E-2 0 1 1 10E-3 1 0 0 10E-4 1 0 1 10

DS31256 65 of 181 Register Name: BERTBC0 Register Description: BERT 32-Bit Bit Counter (lower word) Register Address: 0510h Register Name: BER

DS31256 66 of 181 Bit 1/BERT Error Counter Overflow (BECO). A latched bit that is set when the 24-bit BERT error counter (BEC) overflows. Cleared whe

DS31256 67 of 181 7. HDLC 7.1 General Description The DS31256 contains two different types of HDLC controllers. Each port has a slow HDLC engine (ty

DS31256 68 of 181 Table 7-B. Receive HDLC Functions FUNCTION DESCRIPTION Zero Destuff This operation is disabled if the channel is set to transparent

DS31256 69 of 181 7.2 HDLC Register Description Register Name: RHCDIS Register Description: Receive HDLC Channel Definition Indirect Select Regi

DS31256 7 of 181 Table 1-A. Data Sheet Definitions The following terms are used throughout this data sheet. Note: The DS31256’s ports are numbered 0

DS31256 70 of 181 zero destuffing, and abort detection, octet length checking, or FCS checking. When in transparent mode, the device must not be conf

DS31256 71 of 181 Register Name: RHPL Register Description: Receive HDLC Maximum Packet Length Register Address: 0410h Bit # 7 6 5 4 3 2 1 0 Nam

DS31256 72 of 181 Register Name: THCD Register Description: Transmit HDLC Channel Definition Register Address: 0484h Bit # 7 6 5 4 3 2 1 0 Name

DS31256 73 of 181 Bits 8 to 11/Transmit Flag Generation Bits 0 to 3 (TFG0/TFG1/TFG2/TFG3). These four bits determine how many flags and interfill byt

DS31256 74 of 181 8. FIFO 8.1 General Description and Example The DS31256 Envoy contains one 16kB FIFO for the receive path and another 16kB FIFO f

DS31256 75 of 181 The host must set the watermarks for the receive and transmit paths. The receive path has a high watermark and the transmit path ha

DS31256 76 of 181 8.1.1 Receive High Watermark The high watermark tells the device how many blocks the HDLC engines should write into the receive FIF

DS31256 77 of 181 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to write data to set the internal receive starting block pointer, th

DS31256 78 of 181 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive block pointer RAM, the host s

DS31256 79 of 181 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive high-watermark RAM, this bit

DS31256 8 of 181 In the receive path, the following process occurs. The HDLC Engines collect the incoming data into 32-bit dwords and then signal th

DS31256 80 of 181 Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7) 00000000 (00h) = HDLC channel number 1 11111111 (FFh) = HDLC channel number 256 B

DS31256 81 of 181 Bits 0 to 9/Block ID (BLKID0 to BLKID9) 00000000000 (000h) = block number 0 01111111111 (1FFh) = block number 511 1111111111

DS31256 82 of 181 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal transmit low-watermark RAM, this bit

DS31256 83 of 181 9. DMA 9.1 Introduction The DMA block (Figure 2-1) handles the transfer of packet data from the FIFO block to the PCI block and vi

DS31256 84 of 181 Table 9-A. DMA Registers to be Configured by the Host on Power-Up ADDRESS NAME REGISTER SECTION 0700 RFQBA0 Receive Free-Queue

DS31256 85 of 181 9.2 Receive Side 9.2.1 Overview The receive DMA uses a scatter-gather technique to write packet data into main memory. The host ke

DS31256 86 of 181 On an HDLC-channel basis in the receive DMA configuration RAM, the host instructs the DMA how to use the large and small buffers fo

DS31256 87 of 181 Host Actions The host typically handles the receive DMA as follows: 1) The host is always trying to make free data buffer space av

DS31256 88 of 181 Figure 9-1. Receive DMA Operation Free Data Buffer Address00h08h10hFree Queue Descriptors(circular queue)00h04h08h

DS31256 89 of 181 Figure 9-2. Receive DMA Memory Organization Free Data Buffer SpaceReceive Free-Queue Descriptors:Contains 32-Bit Addresses for Fr

DS31256 9 of 181 When the DMA begins burst writing data into the FIFO, it will try to completely fill the FIFO with HDLC packet data even if it that

DS31256 90 of 181 9.2.2 Packet Descriptors A contiguous section of up to 65,536 quad dwords that make up the receive packet descriptors resides in ma

DS31256 91 of 181 Figure 9-4. Receive Packet Descriptors dword 0 Data Buffer Address (32) dword 1 BUFS (3) Byte Count (13) Next Descriptor Pointer

DS31256 92 of 181 9.2.3 Free Queue The host writes the 32-bit addresses of the available (free) data buffers and their associated packet descriptors

DS31256 93 of 181 Empty Case The receive free queue is considered empty when the read and write pointers are identical. Receive Free-Queue Empty Sta

DS31256 94 of 181 Figure 9-6. Receive Free-Queue Structure Once the receive DMA is activated (by setting the

DS31256 95 of 181 Status/Interrupts On each read of the free queue by the DMA, the DMA sets either the status bit for receive DMA large buffer read (

DS31256 96 of 181 Register Name: RDMAQ Register Description: Receive DMA Queues Control Register Address: 0780h Bit # 7 6 5 4 3 2 1 0 Name n/a

DS31256 97 of 181 9.2.4 Done Queue The DMA writes to the receive done queue when it has filled a free data buffer with packet data and has loaded the

DS31256 98 of 181 The host reads from the receive done queue to find which data buffers and their associated descriptors are ready for processing. T

DS31256 99 of 181 Figure 9-8. Receive Done-Queue Structure Once the receive DMA is activated (through the RDE control bit in t