Rainbow-electronics AT89C51SND1C User Manual

Rev. 4109E–8051–06/03Features• MPEG I/II-Layer 3 Hardwired Decoder– Stand-alone MP3 Decoder– 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency– Separ

10AT8xC51SND1C4109E–8051–06/03Table 13. System Signal DescriptionTable 14. Power Signal DescriptionSignal Name Type DescriptionAlternate FunctionRST

100AT8xC51SND1C4109E–8051–06/03Table 91. USBADDR RegisterUSBADDR (S:C6h) – USB Address RegisterReset Value = 0000 0000bTable 92. USBINT RegisterUSBI

101AT8xC51SND1C4109E–8051–06/03Table 93. USBIEN RegisterUSBIEN (S:BEh) – USB Global Interrupt Enable RegisterReset Value = 0001 0000bTable 94. UEPNU

102AT8xC51SND1C4109E–8051–06/03Table 95. UEPCONX RegisterUEPCONX (S:D4h) – USB Endpoint X Control Register (X = EPNUM set in UEPNUM)Reset Value = 100

103AT8xC51SND1C4109E–8051–06/03Table 96. UEPSTAX RegisterUEPSTAX (S:CEh) – USB Endpoint X Status and Control Register (X = EPNUM set in UEPNUM)765432

104AT8xC51SND1C4109E–8051–06/03Reset Value = 0000 0000b5 STALLRQStall Handshake Request BitSet to send a STALL answer to the host for the next handsha

105AT8xC51SND1C4109E–8051–06/03Table 97. UEPRST RegisterUEPRST (S:D5h) – USB Endpoint FIFO Reset RegisterReset Value = 0000 0000bTable 98. UEPINT Re

106AT8xC51SND1C4109E–8051–06/03Table 99. UEPIEN RegisterUEPIEN (S:C2h) – USB Endpoint Interrupt Enable RegisterReset Value = 0000 0000bTable 100. UE

107AT8xC51SND1C4109E–8051–06/03Table 101. UBYCTX RegisterUBYCTX (S:E2h) – USB Endpoint X Byte Count Register (X = EPNUM set in UEPNUM)Reset Value = 0

108AT8xC51SND1C4109E–8051–06/03Table 103. UFNUMH RegisterUFNUMH (S:BBh, Read-only) – USB Frame Number High RegisterReset Value = 00hTable 104. USBCL

109AT8xC51SND1C4109E–8051–06/03MultiMedia Card ControllerThe AT8xC51SND1C implements a MultiMedia Card (MMC) controller. The MMC isused to store MP3 e

11AT8xC51SND1C4109E–8051–06/03Internal Pin Structure Table 15. Detailed Internal Pin StructureNotes: 1. For information on resistors value, input/out

110AT8xC51SND1C4109E–8051–06/03Bus Lines The MultiMedia Card bus architecture requires all cards to be connected to the same setof lines. No card has

111AT8xC51SND1C4109E–8051–06/03Figure 71. (Multiple) Block Read OperationAs shown in Figure 72 and Figure 73 the data write operation uses a simple b

112AT8xC51SND1C4109E–8051–06/03Table 105. Command Token FormatResponse Token Format There are five types of response tokens (R1 to R5). As shown in F

113AT8xC51SND1C4109E–8051–06/03Table 108. R3 Response Format (OCR Register)Table 109. R4 Response Format (Fast I/O)Table 110. R5 Response FormatDat

114AT8xC51SND1C4109E–8051–06/03required, to provide 8 (eight) clock cycles for the card to complete the operation before shutting down the clock. Foll

115AT8xC51SND1C4109E–8051–06/03Figure 79. MMC Clock Generator and SymbolAs soon as MMCEN bit in MMCON2 is set, the MMC controller receives its system

116AT8xC51SND1C4109E–8051–06/03Command Line ControllerAs shown in Figure 81, the command line controller is divided in 2 channels: the com-mand transm

117AT8xC51SND1C4109E–8051–06/03User may abort command loading by setting and clearing the CTPTR bit in MMCON0register which resets the write pointer t

118AT8xC51SND1C4109E–8051–06/03Data Line Controller The data line controller is based on a 16-Byte FIFO used both by the data transmitterchannel and b

119AT8xC51SND1C4109E–8051–06/03Figure 84. Data Controller Configuration FlowsData TransmitterConfiguration For transmitting data to the card user mus

12AT8xC51SND1C4109E–8051–06/03Clock Controller The AT8xC51SND1C clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock Loop

120AT8xC51SND1C4109E–8051–06/03Figure 85. Data Stream Transmission FlowsSendSTOP CommandData Stream TransmissionStart TransmissionDATEN = 1DATEN = 0F

121AT8xC51SND1C4109E–8051–06/03Figure 86. Data Block Transmission FlowsData ReceiverConfiguration To receive data from the card you must first config

122AT8xC51SND1C4109E–8051–06/03This time-out may be disarmed after receiving 8 data (F1FI flag set) or after receivingend of frame (EOFI flag set) in

123AT8xC51SND1C4109E–8051–06/03Figure 88. Data Block Reception FlowsFlow Control To allow transfer at high speed without taking care of CPU oscillato

124AT8xC51SND1C4109E–8051–06/03InterruptDescription As shown in Figure 89, the MMC controller implements eight interrupt sources reportedin MCBI, EORI

125AT8xC51SND1C4109E–8051–06/03Registers Table 112. MMCON0 RegisterMMCON0 (S:E4h) – MMC Control Register 0Reset Value = 0000 0000b76543210DRPTR DTPTR

126AT8xC51SND1C4109E–8051–06/03Table 113. MMCON1 RegisterMMCON1 (S:E5h) – MMC Control Register 1Reset Value = 0000 0000bTable 114. MMCON2 RegisterMM

127AT8xC51SND1C4109E–8051–06/03Table 115. MMSTA RegisterMMSTA (S:DEh Read Only) – MMC Control and Status RegisterReset Value = 0000 0000b76543210- -

128AT8xC51SND1C4109E–8051–06/03Table 116. MMINT RegisterMMINT (S:E7h Read Only) – MMC Interrupt RegisterReset Value = 0000 0011b76543210MCBI EORI EOC

129AT8xC51SND1C4109E–8051–06/03Table 117. MMMSK Register MMMSK (S:DFh) – MMC Interrupt Mask RegisterReset Value = 1111 1111bTable 118. MMCMD Registe

13AT8xC51SND1C4109E–8051–06/03Figure 7. Mode Switching WaveformsNote: 1. In order to prevent any incorrect operation while operating in X2 mode, user

130AT8xC51SND1C4109E–8051–06/03Table 119. MMDAT Register MMDAT (S:DCh) – MMC Data RegisterReset Value = 1111 1111bTable 120. MMCLK RegisterMMCLK (S:

131AT8xC51SND1C4109E–8051–06/03IDE/ATAPI Interface The AT8xC51SND1C provides an IDE/ATAPI interface allowing connection of devicessuch as CD-ROM reade

132AT8xC51SND1C4109E–8051–06/03Figure 91. IDE Write WaveformsNotes: 1. WR signal may be stretched using M0 bit in AUXR register.2. When executing MOV

133AT8xC51SND1C4109E–8051–06/03Table 121. External Data Memory Interface SignalsRegisters Table 122. DAT16H RegisterDAT16H (S:F9h) – Data 16 High Or

134AT8xC51SND1C4109E–8051–06/03Serial I/O Port The serial I/O port in the AT8xC51SND1C provides both synchronous and asynchro-nous communication modes

135AT8xC51SND1C4109E–8051–06/03Internal Baud Rate Generator When using the Internal Baud Rate Generator, the Baud Rate is derived from the over-flow o

136AT8xC51SND1C4109E–8051–06/03Figure 97. Transmission Waveforms (Mode 0)Reception (Mode 0) To start a reception in mode 0, write to SCON register cl

137AT8xC51SND1C4109E–8051–06/03Asynchronous Modes (Modes 1, 2 and 3)The Serial Port has one 8-bit and 2 9-bit asynchronous modes of operation. Figure

138AT8xC51SND1C4109E–8051–06/03Framing Error Detection (Modes 1, 2 and 3)Framing error detection is provided for the three asynchronous modes. To enab

139AT8xC51SND1C4109E–8051–06/03Notes: 1. These frequencies are achieved in X1 mode, FPER = FOSC ÷ 2.2. These frequencies are achieved in X2 mode, FPER

14AT8xC51SND1C4109E–8051–06/03Figure 9. PLL Filter ConnectionPLL Programming The PLL is programmed using the flow shown in Figure 10. As soon as cloc

140AT8xC51SND1C4109E–8051–06/03Figure 108. Baud Rate Formula (Mode 2)Multiprocessor Communication (Modes 2 and 3)Modes 2 and 3 provide a ninth-bit mo

141AT8xC51SND1C4109E–8051–06/03The following is an example of how to use given addresses to address different slaves:Slave A:SADDR = 1111 0001bSADEN =

142AT8xC51SND1C4109E–8051–06/03Interrupt The Serial I/O Port handles 2 interrupt sources that are the “end of reception” (RI inSCON) and “end of trans

143AT8xC51SND1C4109E–8051–06/03Registers Table 125. SCON RegisterSCON (S:98h) – Serial Control Register Reset Value = 0000 0000b76543210FE/SM0 OVR/SM

144AT8xC51SND1C4109E–8051–06/03Table 126. SBUF RegisterSBUF (S:99h) – Serial Buffer RegisterReset value = XXXX XXXXbTable 127. SADDR RegisterSADDR (

145AT8xC51SND1C4109E–8051–06/03Table 129. BDRCON RegisterBDRCON (S:92h) – Baud Rate Generator Control RegisterReset Value = XXX0 0000bTable 130. BRL

146AT8xC51SND1C4109E–8051–06/03Synchronous Peripheral InterfaceThe AT8xC51SND1C implements a Synchronous Peripheral Interface with master andslave mod

147AT8xC51SND1C4109E–8051–06/03Description The SPI controller interfaces with the C51 core through three special function registers:SPCON, the SPI con

148AT8xC51SND1C4109E–8051–06/03Slave Mode The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data hasbeen loaded in SPDAT.Figure

149AT8xC51SND1C4109E–8051–06/03Table 131. Serial Bit RatesNotes: 1. These frequencies are achieved in X1 mode, FPER = FOSC ÷ 2.2. These frequencies a

15AT8xC51SND1C4109E–8051–06/03Registers Table 16. CKCON RegisterCKCON (S:8Fh) – Clock Control RegisterReset Value = 0000 000Xb (AT89C51SND1C) or 0000

150AT8xC51SND1C4109E–8051–06/03Figure 116. Data Transmission Format (CPHA = 1)SS Management Figure 115 shows an SPI transmission with CPHA = 0, where

151AT8xC51SND1C4109E–8051–06/03Interrupt The SPI handles 2 interrupt sources that are the “end of transfer” and the “mode fault”flags.As shown in Figu

152AT8xC51SND1C4109E–8051–06/03Configuration The SPI configuration is made through SPCON.Master Configuration The SPI operates in master mode when the

153AT8xC51SND1C4109E–8051–06/03Master Mode with Interrupt Figure 120 shows the initialization phase and the transfer phase flows using the inter-rupt

154AT8xC51SND1C4109E–8051–06/03Slave Mode with Polling PolicyFigure 121 shows the initialization phase and the transfer phase flows using the polling.

155AT8xC51SND1C4109E–8051–06/03Slave Mode with Interrupt PolicyFigure 120 shows the initialization phase and the transfer phase flows using theinterru

156AT8xC51SND1C4109E–8051–06/03Registers Table 132. SPCON RegisterSPCON (S:C3h) – SPI Control RegisterReset Value = 0001 0100bNote: 1. When the SPI i

157AT8xC51SND1C4109E–8051–06/03Table 133. SPSTA Register SPSTA (S:C4h) – SPI Status RegisterReset Value = 00000 0000bTable 134. SPDAT Register SPDAT

158AT8xC51SND1C4109E–8051–06/03Two-wire Interface (TWI) ControllerThe AT8xC51SND1C implements a TWI controller supporting the four standard masterand

159AT8xC51SND1C4109E–8051–06/03Figure 124. Complete Data Transfer on TWI BusThe four operating modes are:• Master transmitter• Master receiver• Slave

16AT8xC51SND1C4109E–8051–06/03Table 18. PLLNDIV Register PLLNDIV (S:EEh) – PLL N Divider RegisterReset Value = 0000 0000bTable 19. PLLRDIV Register

160AT8xC51SND1C4109E–8051–06/03Bit Rate The bit rate can be selected from seven predefined bit rates or from a programmable bitrate generator using th

161AT8xC51SND1C4109E–8051–06/03Master Receiver Mode In the master receiver mode, a number of data Bytes are received from a slave transmit-ter (see Fi

162AT8xC51SND1C4109E–8051–06/03Slave Transmitter Mode In the slave transmitter mode, a number of data Bytes are transmitted to a masterreceiver (see F

163AT8xC51SND1C4109E–8051–06/03Figure 125. Format and States in the Master Transmitter ModeData20hASLA08hMTMRSuccessful transmis-sion to a slave rece

164AT8xC51SND1C4109E–8051–06/03Figure 126. Format and States in the Master Receiver ModeAData48hASLA08hMRMTSuccessful receptionfrom a slave transmitt

165AT8xC51SND1C4109E–8051–06/03Figure 127. Format and States in the Slave Receiver ModeAData68hASLAReception of the own slaveaddress and one or moreL

166AT8xC51SND1C4109E–8051–06/03Figure 128. Format and States in the Slave Transmitter ModeADataB0hASLAData AFrom master to slaveFrom slave to masterA

167AT8xC51SND1C4109E–8051–06/03Table 136. Status for Master Transmitter ModeStatus Code SSSTAStatus of the TWI Bus and TWI HardwareApplication Softwa

168AT8xC51SND1C4109E–8051–06/03Table 137. Status for Master Receiver ModeStatus Code SSSTAStatus of the TWI Bus and TWI HardwareApplication Software

169AT8xC51SND1C4109E–8051–06/03Table 138. Status for Slave Receiver Mode with Own Slave AddressStatus Code SSSTAStatus of the TWI Bus and TWI Hardwar

17AT8xC51SND1C4109E–8051–06/03Program/Code MemoryThe AT8xC51SND1C implement 64K Bytes of on-chip program/code memory.Figure 11 shows the split of inte

170AT8xC51SND1C4109E–8051–06/03Table 139. Status for Slave Receiver Mode with General Call AddressStatus Code SSSTAStatus of the TWI Bus and TWI Hard

171AT8xC51SND1C4109E–8051–06/03Table 140. Status for Slave Transmitter ModeStatus Code SSSTAStatus of the TWI Bus and TWI HardwareApplication Softwar

172AT8xC51SND1C4109E–8051–06/03Registers Table 142. SSCON RegisterSSCON (S:93h) – Synchronous Serial Control RegisterReset Value = 0000 0000b76543210

173AT8xC51SND1C4109E–8051–06/03Table 143. SSSTA RegisterSSSTA (S:94h) – Synchronous Serial Status RegisterReset Value = F8hTable 144. SSDAT Register

174AT8xC51SND1C4109E–8051–06/03Analog to Digital ConverterThe AT8xC51SND1C implement a 2-channel 10-bit (8 true bits) analog to digital con-verter (AD

175AT8xC51SND1C4109E–8051–06/03Clock Generator The ADC clock is generated by division of the peripheral clock (see details insection “X2 Feature”, pag

176AT8xC51SND1C4109E–8051–06/03Figure 132. ADC Configuration FlowConversion Launching The conversion is launched by setting the ADSST bit in ADCON re

177AT8xC51SND1C4109E–8051–06/03Registers Table 147. ADCON RegisterADCON (S:F3h) – ADC Control RegisterReset Value = 0000 0000bTable 148. ADCLK Regis

178AT8xC51SND1C4109E–8051–06/03Table 149. ADDH RegisterADDH (S:F5h Read Only) – ADC Data High Byte RegisterReset Value = 0000 0000bTable 150. ADDL R

179AT8xC51SND1C4109E–8051–06/03Keyboard Interface The AT8xC51SND1C implement a keyboard interface allowing the connection of a 4 x nmatrix keyboard. I

18AT8xC51SND1C4109E–8051–06/03User Space This space is composed of a 64K Bytes ROM memory programmed during the manu-facturing process. It contains th

180AT8xC51SND1C4109E–8051–06/03Registers Table 151. KBCON RegisterKBCON (S:A3h) – Keyboard Control RegisterReset Value = 0000 1111bTable 152. KBSTA

181AT8xC51SND1C4109E–8051–06/03Electrical CharacteristicsAbsolute Maximum RatingDC CharacteristicsDigital LogicStorage Temperature ...

182AT8xC51SND1C4109E–8051–06/03Notes: 1. Typical values are obtained using VDD= 3 V and TA= 25°C. They are not tested andthere is no guarantee on thes

183AT8xC51SND1C4109E–8051–06/03IDD, IDL and IPD Test ConditionsFigure 136. IDD Test Condition, Active ModeFigure 137. IDL Test Condition, Idle ModeF

184AT8xC51SND1C4109E–8051–06/03A to D ConverterTable 155. A to D Converter DC CharacteristicsVDD = 2.7 to 3.3 V, TA = -40 to +85°COscillator & Cr

185AT8xC51SND1C4109E–8051–06/03Phase Lock LoopSchematic Figure 140. PLL Filter ConnectionParameters Table 157. PLL Filter CharacteristicsVDD = 2.7 t

186AT8xC51SND1C4109E–8051–06/03AC CharacteristicsExternal 8-bit Bus CyclesDefinition of Symbols Table 159. External 8-bit Bus Cycles Timing Symbol De

187AT8xC51SND1C4109E–8051–06/03Table 161. External 8-bit Bus Cycle - Data Write AC TimingsVDD = 2.7 to 3.3 V, TA = -40 to +85°CWaveforms Figure 142.

188AT8xC51SND1C4109E–8051–06/03Figure 143. External 8-bit Bus Cycle - Data Write WaveformsExternal IDE 16-bit Bus CyclesDefinition of Symbols Table 1

189AT8xC51SND1C4109E–8051–06/03Timings Test conditions: capacitive load on all pins= 50 pF.Table 163. External IDE 16-bit Bus Cycle - Data Read AC Ti

19AT8xC51SND1C4109E–8051–06/03Hardware Security SystemThe AT89C51SND1C implements three lock bits LB2:0 in the LSN of HSB (seeTable 22) providing thre

190AT8xC51SND1C4109E–8051–06/03Waveforms Figure 144. External IDE 16-bit Bus Cycle - Data Read WaveformsNote: 1. D15:8 is written in DAT16H SFR.Figur

191AT8xC51SND1C4109E–8051–06/03Timings Test conditions: capacitive load on all pins= 50 pF.Table 166. SPI Interface Master AC TimingVDD = 2.7 to 3.3

192AT8xC51SND1C4109E–8051–06/03Waveforms Figure 146. SPI Slave Waveforms (SSCPHA= 0)Note: 1. Not Defined but generally the MSB of the character which

193AT8xC51SND1C4109E–8051–06/03Figure 148. SPI Master Waveforms (SSCPHA= 0)Note: 1. SS handled by software using general purpose port pin.Figure 149.

194AT8xC51SND1C4109E–8051–06/03Two-wire InterfaceTimings Table 167. TWI Interface AC TimingVDD = 2.7 to 3.3 V, TA = -40 to +85°CNotes: 1. At 100 kbit

195AT8xC51SND1C4109E–8051–06/03MMC InterfaceDefinition of symbols Table 168. MMC Interface Timing Symbol DefinitionsTimings Table 169. MMC Interface

196AT8xC51SND1C4109E–8051–06/03Audio InterfaceDefinition of symbols Table 170. Audio Interface Timing Symbol DefinitionsTimings Table 171. Audio Int

197AT8xC51SND1C4109E–8051–06/03Analog to Digital ConverterDefinition of symbols Table 172. Analog to Digital Converter Timing Symbol DefinitionsChara

198AT8xC51SND1C4109E–8051–06/03Figure 154. Analog to Digital Converter CharacteristicsFlash MemoryDefinition of symbols Table 174. Flash Memory Timi

199AT8xC51SND1C4109E–8051–06/03Waveforms Figure 155. FLASH Memory - ISP WaveformsNote: 1. ISP must be driven through a pull-down resistor (see Sectio

2AT8xC51SND1C4109E–8051–06/03The AT83C51SND1C includes 64K Bytes of ROM memory.The AT8xC51SND1C include 2304 Bytes of RAM memory.The AT8xC51SND1C prov

20AT8xC51SND1C4109E–8051–06/03Figure 14. Hardware Boot Process AlgorithmThe software process (boot loader) is detailed in the “Boot Loader Datasheet”

200AT8xC51SND1C4109E–8051–06/03Figure 158. AC Testing Input/Output WaveformsNote: 1. During AC testing, all inputs are driven at VDD -0.5 V for a log

201AT8xC51SND1C4109E–8051–06/03Ordering InformationNotes: 1. Refers to ROM code.2. PLCC84 package only available for development board.Part Number Mem

202AT8xC51SND1C4109E–8051–06/03Package InformationTQFP80

203AT8xC51SND1C4109E–8051–06/03BGA81

204AT8xC51SND1C4109E–8051–06/03PLCC84

205AT8xC51SND1C4109E–8051–06/03Datasheet Change Log for AT8xC51SND1CChanges from 4109D-10/02 to 4109E-06/031. Additional information on AT83C51SND1C p

Table of ContentsiFeatures ... 1Description ...

iiAT8xC51SND1C4109E–8051–06/03Reset ...

iiiAT8xC51SND1C4109E–8051–06/03Isochronous Transactions...92Miscellan

ivAT8xC51SND1C4109E–8051–06/03Registers...180

21AT8xC51SND1C4109E–8051–06/03Registers Table 21. AUXR1 Register AUXR1 (S:A2h) – Auxiliary Register 1Reset Value = XXXX 00X0bNote: 1. ENBOOT bit is o

Printed on recycled paper.Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Co

22AT8xC51SND1C4109E–8051–06/03Hardware Bytes Table 22. HSB Byte – Hardware Security ByteReset Value = XXUU UXXX, UUUU UUUU after an hardware full chi

23AT8xC51SND1C4109E–8051–06/03Data Memory The AT8xC51SND1C provides data memory access in 2 different spaces:1. The internal space mapped in three sep

24AT8xC51SND1C4109E–8051–06/03Figure 16. Lower 128 Bytes Internal RAM OrganizationUpper 128 Bytes RAM The upper 128 Bytes of RAM are accessible from

25AT8xC51SND1C4109E–8051–06/03External SpaceMemory Interface The external memory interface comprises the external bus (port 0 and port 2) as well asth

26AT8xC51SND1C4109E–8051–06/03External Bus Cycles This section describes the bus cycles the AT8xC51SND1C executes to read (seeFigure 18), and write da

27AT8xC51SND1C4109E–8051–06/03Dual Data PointerDescription The AT8xC51SND1C implement a second data pointer for speeding up code executionand reducing

28AT8xC51SND1C4109E–8051–06/03Registers Table 28. PSW Register PSW (S:8Eh) – Program Status Word RegisterReset Value = 0000 0000b76543210CY AC F0 RS1

29AT8xC51SND1C4109E–8051–06/03Table 29. AUXR Register AUXR (S:8Eh) – Auxiliary Control RegisterReset Value = X000 1101b76543210- EXT16 M0 DPHDIS XRS1

3AT8xC51SND1C4109E–8051–06/03Pin DescriptionPinouts Figure 2. AT89C51SND1C 80-pin QFP PackageNote: 1. ISP pin is only available in AT89C51SND1C produ

30AT8xC51SND1C4109E–8051–06/03Special Function RegistersThe Special Function Registers (SFRs) of the AT8xC51SND1C derivatives fall into thecategories

31AT8xC51SND1C4109E–8051–06/03Note: 1. FCON register is only available in AT89C51SND1C product.Table 34. Port SFRsMnemonicAddName 76543210P0 80h 8-bi

32AT8xC51SND1C4109E–8051–06/03Table 37. MP3 Decoder SFRs MnemonicAddName 76543210MP3CON AAh MP3 Control MPEN MPBBST CRCEN MSKANC MSKREQ MSKLAY MSKSYN

33AT8xC51SND1C4109E–8051–06/03Table 39. USB Controller SFRsMnemonicAddName 76543210USBCON BCh USB Global Control USBE SUSPCLK SDRMWUP - UPRSM RMWUPE

34AT8xC51SND1C4109E–8051–06/03Table 42. Serial I/O Port SFRsMnemonicAddName 76543210SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RISBUF 99h

35AT8xC51SND1C4109E–8051–06/03ReservedNotes: 1. SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable.2. NVERS reset

36AT8xC51SND1C4109E–8051–06/03Interrupt System The AT8xC51SND1C, like other control-oriented computer architectures, employ a pro-gram interrupt metho

37AT8xC51SND1C4109E–8051–06/03Table 49. Priority LevelsA low-priority interrupt is always interrupted by a higher priority interrupt but not byanothe

38AT8xC51SND1C4109E–8051–06/03Figure 21. Interrupt Control SystemEI2CIEN1.1EMMCIEN1.0EUSBIEN1.6ESPIIEN1.2EX0IEN0.000011011ExternalInterrupt 0INT0EAIE

39AT8xC51SND1C4109E–8051–06/03External InterruptsINT1:0 Inputs External interrupts INT0 and INT1 (INTn, n = 0 or 1) pins may each be programmed tobe l

4AT8xC51SND1C4109E–8051–06/03Figure 3. AT8xC51SND1C 81-pin BGA PackageNote: 1. ISP pin is only available in AT89C51SND1C product.Do not connect this

40AT8xC51SND1C4109E–8051–06/03Registers Table 51. IEN0 Register IEN0 (S:A8h) – Interrupt Enable Register 0Reset Value = 0000 0000b76543210EA EAUD EMP

41AT8xC51SND1C4109E–8051–06/03Table 52. IEN1 RegisterIEN1 (S:B1h) – Interrupt Enable Register 1Reset Value = 0000 0000b76543210- EUSB - EKB EADC ESPI

42AT8xC51SND1C4109E–8051–06/03Table 53. IPH0 Register IPH0 (S:B7h) – Interrupt Priority High Register 0Reset Value = X000 0000b76543210- IPHAUD IPHMP

43AT8xC51SND1C4109E–8051–06/03Table 54. IPH1 Register IPH1 (S:B3h) – Interrupt Priority High Register 1Reset Value = 0000 0000b76543210- IPHUSB - IPH

44AT8xC51SND1C4109E–8051–06/03Table 55. IPL0 RegisterIPL0 (S:B8h) - Interrupt Priority Low Register 0Reset Value = X000 0000b76543210- IPLAUD IPLMP3

45AT8xC51SND1C4109E–8051–06/03Table 56. IPL1 Register IPL1 (S:B2h) – Interrupt Priority Low Register 1Reset Value = 0000 0000b76543210- IPLUSB - IPLK

46AT8xC51SND1C4109E–8051–06/03Power Management 2 power reduction modes are implemented in the AT8xC51SND1C: the Idle mode andthe Power-down mode. Thes

47AT8xC51SND1C4109E–8051–06/03Table 58. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor(1)Note: 1. These values assume VDD starts from 0

48AT8xC51SND1C4109E–8051–06/03Entering Idle Mode To enter Idle mode, the user must set the IDL bit in PCON register (see Table 59). TheAT8xC51SND1C en

49AT8xC51SND1C4109E–8051–06/03resumes when the input is released (see Figure 26) while using KINx input, execution resumes after counting 1024 clock e

5AT8xC51SND1C4109E–8051–06/03Figure 4. AT8xC51SND1C 84-pin PLCC PackageAT89C51SND1C-SR (FLASH)P0.3/AD3P0.4/AD4P0.5/AD5VSSVDDP0.6/AD6P0.7/AD7P2.0/A8P2

50AT8xC51SND1C4109E–8051–06/03Registers Table 59. PCON RegisterPCON (S:87h) – Power Configuration RegisterReset Value = XXXX 0000b76543210----GF1GF0P

51AT8xC51SND1C4109E–8051–06/03Timers/Counters The AT8xC51SND1C implement 2 general-purpose, 16-bit Timers/Counters. They areidentified as Timer 0 and

52AT8xC51SND1C4109E–8051–06/03Figure 28. Timer 0 and Timer 1 Clock Controller and SymbolsTimer 0 Timer 0 functions as either a Timer or event Counter

53AT8xC51SND1C4109E–8051–06/03Mode 1 (16-bit Timer) Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected incascade (see Fi

54AT8xC51SND1C4109E–8051–06/033. Figure 34 gives the autoreload period calculation formulas for both TF0 and TF1flags.Figure 35. Timer/Counter 0 in M

55AT8xC51SND1C4109E–8051–06/03Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg-ister) wit

56AT8xC51SND1C4109E–8051–06/03Registers Table 60. TCON RegisterTCON (S:88h) – Timer/Counter Control RegisterReset Value = 0000 0000b76543210TF1 TR1 T

57AT8xC51SND1C4109E–8051–06/03Notes: 1. Reloaded from TH1 at overflow.2. Reloaded from TH0 at overflow.Reset Value = 0000 0000bTable 62. TH0 Register

58AT8xC51SND1C4109E–8051–06/03Table 63. TL0 RegisterTL0 (S:8Ah) – Timer 0 Low Byte RegisterReset Value = 0000 0000bTable 64. TH1 RegisterTH1 (S:8Dh)

59AT8xC51SND1C4109E–8051–06/03Watchdog Timer The AT8xC51SND1C implement a hardware Watchdog Timer (WDT) that automaticallyresets the chip if it is all

6AT8xC51SND1C4109E–8051–06/03Signals All the AT8xC51SND1C signals are detailed by functionality in Table 1 to Table 14.Table 1. Ports Signal Descript

60AT8xC51SND1C4109E–8051–06/03Watchdog Operation After reset, the WDT is disabled. The WDT is enabled by writing the sequence 1Eh andE1h into the WDTR

61AT8xC51SND1C4109E–8051–06/03Registers Table 67. WDTRST RegisterWDTRST (S:A6h Write only) – Watchdog Timer Reset RegisterReset Value = XXXX XXXXbFig

62AT8xC51SND1C4109E–8051–06/03MP3 Decoder The AT8xC51SND1C implement a MPEG I/II audio layer 3 decoder better known asMP3 decoder.In MPEG I (ISO 11172

63AT8xC51SND1C4109E–8051–06/03MP3 Data The MP3 decoder does not start any frame decoding before having a complete frame inits input buffer(1). In orde

64AT8xC51SND1C4109E–8051–06/03Audio ControlsVolume Control The MP3 decoder implements volume control on both right and left channels. TheMP3VOR and MP

65AT8xC51SND1C4109E–8051–06/03Frame Information The MP3 frame header contains information on the audio data contained in the frame.These informations

66AT8xC51SND1C4109E–8051–06/03InterruptDescription As shown in Figure 46, the MP3 decoder implements five interrupt sources reported inERRCRC, ERRSYN,

67AT8xC51SND1C4109E–8051–06/03Figure 47. MP3 Interrupt Service Routine FlowNote: 1. Test these bits only if needed (unmasked interrupt).Data Request?

68AT8xC51SND1C4109E–8051–06/03Registers Table 72. MP3CON RegisterMP3CON (S:AAh) – MP3 Decoder Control RegisterReset Value = 0011 1111b76543210MPEN MP

69AT8xC51SND1C4109E–8051–06/03Table 73. MP3STA RegisterMP3STA (S:C8h Read Only) – MP3 Decoder Status RegisterReset Value = 0000 0001bTable 74. MP3DA

7AT8xC51SND1C4109E–8051–06/03Table 3. Timer 0 and Timer 1 Signal DescriptionTable 4. Audio Interface Signal DescriptionTable 5. USB Controller Sign

70AT8xC51SND1C4109E–8051–06/03Table 75. MP3STA1 RegisterMP3STA1 (S:AFh) – MP3 Decoder Status Register 1Reset Value = 0001 0001bTable 76. MP3ANC Regi

71AT8xC51SND1C4109E–8051–06/03Table 78. MP3VOR RegisterMP3VOR (S:9Fh) – MP3 Volume Right Control RegisterReset Value = 0000 0000bTable 79. MP3BAS Re

72AT8xC51SND1C4109E–8051–06/03Table 81. MP3TRE RegisterMP3TRE (S:B6h) – MP3 Treble Control RegisterReset Value = 0000 0000bTable 82. MP3CLK Register

73AT8xC51SND1C4109E–8051–06/03Audio Output InterfaceThe AT8xC51SND1C implement an audio output interface allowing the audio bitstreamto be output in v

74AT8xC51SND1C4109E–8051–06/03Clock Generator The audio interface clock is generated by division of the PLL clock. The division factor isgiven by AUCD

75AT8xC51SND1C4109E–8051–06/03Figure 51. Audio Output FormatThe data converter receives its audio stream from 2 sources selected by the SRC bit inAUD

76AT8xC51SND1C4109E–8051–06/03Table 83. Sample Duplication FactorMP3 Buffer In song playing mode, the audio stream comes from the MP3 decoder through

77AT8xC51SND1C4109E–8051–06/03Figure 53. MP3 Mode Audio Configuration FlowVoice or Sound Playing In voice or sound playing mode, the operations requi

78AT8xC51SND1C4109E–8051–06/03Registers Table 84. AUDCON0 RegisterAUDCON0 (S:9Ah) – Audio Interface Control Register 0Reset Value = 0000 1000bTable 8

79AT8xC51SND1C4109E–8051–06/03Table 86. AUDSTA RegisterAUDSTA (S:9Ch Read Only) – Audio Interface Status RegisterReset Value = 1100 0000bTable 87. A

8AT8xC51SND1C4109E–8051–06/03Table 6. MutiMediaCard Interface Signal DescriptionTable 7. UART Signal DescriptionTable 8. SPI Controller Signal Desc

80AT8xC51SND1C4109E–8051–06/03Universal Serial Bus The AT8xC51SND1C implements a USB device controller supporting full speed datatransfer. In addition

81AT8xC51SND1C4109E–8051–06/03Description The USB device controller provides the hardware that the AT8xC51SND1C needs tointerface a USB link to a data

82AT8xC51SND1C4109E–8051–06/03Serial Interface Engine (SIE) The SIE performs the following functions:• NRZI data encoding and decoding.• Bit stuffing

83AT8xC51SND1C4109E–8051–06/03Function Interface Unit (UFI) The Function Interface Unit provides the interface between the AT8xC51SND1C andthe SIE. It

84AT8xC51SND1C4109E–8051–06/03ConfigurationGeneral Configuration • USB controller enableBefore any USB transaction, the 48 MHz required by the USB con

85AT8xC51SND1C4109E–8051–06/03• Endpoint enableBefore using an endpoint, this must be enabled by setting the EPEN bit in the UEP-CONX register.An endp

86AT8xC51SND1C4109E–8051–06/03• Endpoint FIFO resetBefore using an endpoint, its FIFO should be reset. This action resets the FIFOpointer to its origi

87AT8xC51SND1C4109E–8051–06/03Bulk/Interrupt TransactionsBulk and Interrupt transactions are managed in the same way.Bulk/Interrupt OUT Transactions i

88AT8xC51SND1C4109E–8051–06/03Bulk/Interrupt OUT Transactions in Ping-pong ModeFigure 63. Bulk/Interrupt OUT Transactions in Ping-pong ModeAn endpoin

89AT8xC51SND1C4109E–8051–06/03If the Host sends more Bytes than supported by the endpoint FIFO, the overflow datawon’t be stored, but the USB controll

9AT8xC51SND1C4109E–8051–06/03Table 10. A/D Converter Signal DescriptionTable 11. Keypad Interface Signal DescriptionTable 12. External Access Signa

90AT8xC51SND1C4109E–8051–06/03Bulk/Interrupt IN Transactions in Ping-pong ModeFigure 65. Bulk/Interrupt IN transactions in Ping-pong modeAn endpoint

91AT8xC51SND1C4109E–8051–06/03Control TransactionsSetup Stage The DIR bit in the UEPSTAX register should be at 0.Receiving Setup packets is the same a

92AT8xC51SND1C4109E–8051–06/03Isochronous TransactionsIsochronous OUT Transactions in Standard ModeAn endpoint should be first enabled and configured

93AT8xC51SND1C4109E–8051–06/03If the Host sends more Bytes than supported by the endpoint FIFO, the overflow datawon’t be stored, but the USB controll

94AT8xC51SND1C4109E–8051–06/03MiscellaneousUSB Reset The EORINT bit in the USBINT register is set by hardware when a End Of Reset hasbeen detected on

95AT8xC51SND1C4109E–8051–06/03Suspend/Resume ManagementSuspend The Suspend state can be detected by the USB controller if all the clocks are enabledan

96AT8xC51SND1C4109E–8051–06/03Upstream Resume A USB device can be allowed by the Host to send an upstream resume for RemoteWake-up purpose.When the US

97AT8xC51SND1C4109E–8051–06/03USB Interrupt SystemInterrupt System Priorities Figure 68. USB Interrupt Control SystemTable 1. Priority LevelsUSB Int

98AT8xC51SND1C4109E–8051–06/03Figure 69. USB Interrupt Control Block DiagramTXCMPUEPSTAX.0RXOUTB0UEPSTAX.1RXSETUPUEPSTAX.2STLCRCUEPSTAX.3EPXIEUEPIEN.

99AT8xC51SND1C4109E–8051–06/03Registers Table 90. USBCON RegisterUSBCON (S:BCh) – USB Global Control RegisterReset Value = 0000 0000b76543210USBE SUS