Rainbow-electronics AT89LP214 User Manual

Features• 8-bit Microcontroller Compatible with MCS®51 Products• Enhanced 8051 Architecture– Single Clock Cycle per Byte Fetch– Up to 20 MIPS Throughp

103538A–MICRO–7/06AT89LP213/214 [Preliminary]8. Enhanced CPUThe AT89LP213/214 uses an enhanced 8051 CPU that runs at 6 to 12 times the speed of stan-d

113538A–MICRO–7/06AT89LP213/214 [Preliminary]Figure 8-3. Two-cycle ALU Operation (Example: ADD A, #data)8.1 Restrictions on Certain InstructionsThe AT

123538A–MICRO–7/06AT89LP213/214 [Preliminary]9. System ClockThe system clock is generated directly from one of three selectable clock sources. The thr

133538A–MICRO–7/06AT89LP213/214 [Preliminary] 10. ResetDuring reset, all I/O Registers are set to their initial values, the port pins are tristated, a

143538A–MICRO–7/06AT89LP213/214 [Preliminary]Figure 10-1. Power-on Reset Sequence (BOD Disabled)If the Brown-out Detector (BOD) is also enabled, the s

153538A–MICRO–7/06AT89LP213/214 [Preliminary]10.2 Brown-out ResetThe AT89LP213/214 has an on-chip Brown-out Detection (BOD) circuit for monitoring the

163538A–MICRO–7/06AT89LP213/214 [Preliminary]10.4 Watchdog ResetWhen the Watchdog times out, it will generate an internal reset pulse lasting 16 clock

173538A–MICRO–7/06AT89LP213/214 [Preliminary]begin. The time-out period is controlled by the Start-up Timer Fuses (see Table 10-1 on page15). The inte

183538A–MICRO–7/06AT89LP213/214 [Preliminary]Figure 11-3. Reset Recovery from Power-down. 12. InterruptsThe AT89LP213/214 provides 7 interrupt sources

193538A–MICRO–7/06AT89LP213/214 [Preliminary]instruction, an internal polling sequence determines which request is serviced. The pollingsequence is ba

23538A–MICRO–7/06AT89LP213/214 [Preliminary]have bytes to execute, and most of the remaining instructions require only one additional clock.The enhanc

203538A–MICRO–7/06AT89LP213/214 [Preliminary]12.1 Interrupt Response TimeThe interrupt flags may be set by their hardware in any clock cycle. The inte

213538A–MICRO–7/06AT89LP213/214 [Preliminary].Table 12-2. IE – Interrupt Enable RegisterIE = A8H Reset Value = 0000 0000BBit AddressableEA EC EGP ES E

223538A–MICRO–7/06AT89LP213/214 [Preliminary]13. I/O PortsThe AT89LP213/214 can be configured for between 9 and 12 I/O pins. The exact number of I/Opi

233538A–MICRO–7/06AT89LP213/214 [Preliminary].13.1.1 Quasi-bidirectional OutputPort pins in quasi-bidirectional output mode function similar to standa

243538A–MICRO–7/06AT89LP213/214 [Preliminary]13.1.2 Input-only ModeThe input only port configuration is shown in Figure 13-2. The output drivers are t

253538A–MICRO–7/06AT89LP213/214 [Preliminary]Figure 13-5. Push-pull Output13.2 Port 1 Analog FunctionsThe AT89LP213/214 incorporates an analog compara

263538A–MICRO–7/06AT89LP213/214 [Preliminary]13.4 Port Alternate FunctionsMost general-purpose digital I/O pins of the AT89LP213/214 share functionali

273538A–MICRO–7/06AT89LP213/214 [Preliminary]14. Enhanced Timer/CountersThe AT89LP213/214 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1.

283538A–MICRO–7/06AT89LP213/214 [Preliminary]Figure 14-1. Timer/Counter 1 Mode 0: Variable Width CounterMode 0 operation is the same for Timer 0 as fo

293538A–MICRO–7/06AT89LP213/214 [Preliminary]14.3 Mode 2 – 8-bit Auto-reload Timer/CounterMode 2 configures the Timer register as an 8-bit Counter (TL

33538A–MICRO–7/06AT89LP213/214 [Preliminary]3. Pin DescriptionTable 3-1. AT89LP213 Pin DescriptionPin Symbol Type Description1P1.5I/OI/OIP1.5: User-co

303538A–MICRO–7/06AT89LP213/214 [Preliminary].Table 14-1. TCON – Timer/Counter Control RegisterTCON = 88H Reset Value = 0000 0000BBit AddressableTF1 T

313538A–MICRO–7/06AT89LP213/214 [Preliminary]Table 14-2. TMOD: Timer/Counter Mode Control RegisterTMOD = 88H Reset Value = 0000 0000B Not Bit Addressa

323538A–MICRO–7/06AT89LP213/214 [Preliminary].14.5 Pulse Width ModulationOn the AT89LP213, Timer 0 and Timer 1 may be independently configured as 8-bi

333538A–MICRO–7/06AT89LP213/214 [Preliminary]14.5.1 Mode 0 – 8-bit PWM with 8-bit Logarithmic PrescalerIn Mode 0, TLx acts as a logarithmic prescaler

343538A–MICRO–7/06AT89LP213/214 [Preliminary]Figure 14-7. Timer/Counter 1 PWM Mode 114.5.3 Mode 2 – 8-bit Frequency GeneratorTimer 0 in PWM Mode 2 fun

353538A–MICRO–7/06AT89LP213/214 [Preliminary]14.5.4 Mode 3 – Split 8-bit PWMTimer 1 in PWM Mode 3 simply holds its count. The effect is the same as se

363538A–MICRO–7/06AT89LP213/214 [Preliminary]15. External InterruptsWhen the AT89LP213/214 is configured to use the internal RC Oscillator, XTAL1 and

373538A–MICRO–7/06AT89LP213/214 [Preliminary]..Table 16-2. GPLS – General-purpose Interrupt Level Select RegisterGPLS = 9BH Reset Value = 0000 0000BNo

383538A–MICRO–7/06AT89LP213/214 [Preliminary]17. Serial InterfaceThe serial interface on the AT89LP214 implements a Universal Asynchronous Receiver/Tr

393538A–MICRO–7/06AT89LP213/214 [Preliminary]bit and prepares to receive the data bytes that follows. The slaves that are not addressed settheir SM2 b

43538A–MICRO–7/06AT89LP213/214 [Preliminary]Table 3-2. AT89LP214 Pin DescriptionPin Symbol Type Description1P1.5I/OI/OIP1.5: User-configurable I/O Por

403538A–MICRO–7/06AT89LP213/214 [Preliminary]17.2 Baud RatesThe baud rate in Mode 0 is fixed as shown in the following equation:The baud rate in Mode

413538A–MICRO–7/06AT89LP213/214 [Preliminary]17.3 More About Mode 0Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data b

423538A–MICRO–7/06AT89LP213/214 [Preliminary]Figure 17-1. Serial Port Mode 0INTERNAL BUS1/2 foscINTERNAL BUSTXD (SHIFT CLOCK)RXD (DATA OUT)TXD (SHIFT

433538A–MICRO–7/06AT89LP213/214 [Preliminary]17.4 More About Mode 1Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0),

443538A–MICRO–7/06AT89LP213/214 [Preliminary]Figure 17-2. Serial Port Mode 1 TXCLOCKWRITE TO SBUFINTERNAL BUSREADSBUFLOADSBUFSBUFSHIFTINPUT SHIFT REG.

453538A–MICRO–7/06AT89LP213/214 [Preliminary]17.5 More About Modes 2 and 3Eleven bits are transmitted (through TXD), or received (through RXD): a star

463538A–MICRO–7/06AT89LP213/214 [Preliminary]Figure 17-3. Serial Port Mode 2SMOD1 1SMOD1 0INTERNAL BUSINTERNAL BUSCPU CLOCK

473538A–MICRO–7/06AT89LP213/214 [Preliminary]Figure 17-4. Serial Port Mode 3 TXCLOCKWRITE TO SBUFSENDDATASHIFTTXDSTOP BIT GENTID0 D1 D2 D3 D4 D5 D6 D7

483538A–MICRO–7/06AT89LP213/214 [Preliminary]17.6 Framing Error DetectionIn addition to all of its usual modes, the UART can perform framing error det

493538A–MICRO–7/06AT89LP213/214 [Preliminary]In a more complex system, the following could be used to select slaves 1 and 2 while excludingslave 0: Sl

53538A–MICRO–7/06AT89LP213/214 [Preliminary]4. Block DiagramFigure 4-1. AT89LP213 Block DiagramFigure 4-2. AT89LP214 Block Diagram

503538A–MICRO–7/06AT89LP213/214 [Preliminary]The interconnection between master and slave CPUs with SPI is shown in Figure 18-1. The fourpins in the i

513538A–MICRO–7/06AT89LP213/214 [Preliminary]Notes: 1. Set up the clock mode before enabling the SPI: set all bits needed in SPCR except the SPE bit,

523538A–MICRO–7/06AT89LP213/214 [Preliminary]Table 18-3. SPSR – SPI Status RegisterSPSR Address = E8H Reset Value = 000X X000BNot Bit AddressableSPIF

533538A–MICRO–7/06AT89LP213/214 [Preliminary]Figure 18-2. SPI Shift Register DiagramFigure 18-3. SPI Block Diagram2:1MUX2:1MUXSerial Master Serial Sla

543538A–MICRO–7/06AT89LP213/214 [Preliminary]The CPHA (Clock PHAse), CPOL (Clock POLarity), and SPR (Serial Peripheral clock Rate =baud rate) bits in

553538A–MICRO–7/06AT89LP213/214 [Preliminary]19. Analog ComparatorA single analog comparator is provided on the AT89LP213/214. The analog comparator h

563538A–MICRO–7/06AT89LP213/214 [Preliminary]Note: 1. Debouncing modes require the use of Timer 1 to generate the sampling delay.Table 19-1. ACSR – An

573538A–MICRO–7/06AT89LP213/214 [Preliminary]20. Programmable Watchdog TimerThe programmable Watchdog Timer (WDT) protects the system from incorrect e

583538A–MICRO–7/06AT89LP213/214 [Preliminary]20.1 Software ResetA Software Reset of the AT89LP213/214 is accomplished by writing the software resetseq

593538A–MICRO–7/06AT89LP213/214 [Preliminary]21. Instruction Set SummaryThe AT89LP213/214 is fully binary compatible with the MCS-51 instruction set.

63538A–MICRO–7/06AT89LP213/214 [Preliminary]5. Comparison to Standard 8051The AT89LP213/214 is part of a family of devices with enhanced features that

603538A–MICRO–7/06AT89LP213/214 [Preliminary]Arithmetic BytesClock CyclesHex Code8051 AT89LPINC DPTR 1 24 2 A3MUL AB 1 48 2 A4DIV AB 1 48 4 84DA A 1 1

613538A–MICRO–7/06AT89LP213/214 [Preliminary]Data Transfer BytesClock CyclesHex Code8051 AT89LPMOV A, Rn 1 12 1 E8-EFMOV A, direct 2 12 2 E5MOV A, @Ri

623538A–MICRO–7/06AT89LP213/214 [Preliminary]Note: 1. This escaped instruction is an extension to the instruction set.Bit Operations BytesClock Cycles

633538A–MICRO–7/06AT89LP213/214 [Preliminary]22. On-chip Debug SystemThe AT89LP213/214 On-chip Debug (OCD) System uses a two-wire serial interface to

643538A–MICRO–7/06AT89LP213/214 [Preliminary]22.2 Software BreakpointsThe AT89LP213/214 microcontroller includes a BREAK instruction for implementing

653538A–MICRO–7/06AT89LP213/214 [Preliminary]23. Programming the Flash MemoryThe Atmel AT89LP213/214 microcontroller features 2KB of on-chip In-System

663538A–MICRO–7/06AT89LP213/214 [Preliminary]The In-System Programming Interface is the only means of externally programming theAT89LP213/214 microcon

673538A–MICRO–7/06AT89LP213/214 [Preliminary]Figure 23-2. AT89LP213/214 Memory Organization23.3 Command FormatProgramming commands consist of an opcod

683538A–MICRO–7/06AT89LP213/214 [Preliminary]Figure 23-3. Command Sequence Flow ChartFigure 23-4. ISP Command PacketInput Preamble 2(55h)Input OpcodeI

693538A–MICRO–7/06AT89LP213/214 [Preliminary]Notes: 1. Program Enable must be the first command issued after entering into programming mode.2. Any num

73538A–MICRO–7/06AT89LP213/214 [Preliminary]5.6 Watchdog TimerThe Watchdog Timer in AT89LP213/214 counts at a rate of once per clock cycle. This compa

703538A–MICRO–7/06AT89LP213/214 [Preliminary]23.4 Status RegisterThe current state of the memory may be accessed by reading the status register. The s

713538A–MICRO–7/06AT89LP213/214 [Preliminary]23.7 User Configuration FusesThe AT89LP213/214 includes 19 user fuses for configuration of the device. Ea

723538A–MICRO–7/06AT89LP213/214 [Preliminary]23.8 Programming Interface TimingThis section details general system timing sequences and constraints for

733538A–MICRO–7/06AT89LP213/214 [Preliminary]23.8.3 ISP Start Sequence Execute this sequence to exit CPU execution mode and enter ISP mode when the de

743538A–MICRO–7/06AT89LP213/214 [Preliminary]23.8.5 Serial Peripheral InterfaceThe Serial Peripheral Interface (SPI) is a byte-oriented full duplex sy

753538A–MICRO–7/06AT89LP213/214 [Preliminary]23.8.6 Timing ParametersThe timing parameters for Figure 23-5, Figure 23-6, Figure 23-7, Figure 23-8, and

763538A–MICRO–7/06AT89LP213/214 [Preliminary]24. Electrical CharacteristicsNotes: 1. Under steady state (non-transient) conditions, IOL must be extern

773538A–MICRO–7/06AT89LP213/214 [Preliminary]24.3 Serial Peripheral Interface Timing Table 24-1. SPI Master CharacteristicsSymbol Parameter Min Max Un

783538A–MICRO–7/06AT89LP213/214 [Preliminary]Figure 24-1. SPI Master Timing (CPHA = 0)Figure 24-2. SPI Slave Timing (CPHA = 0)Figure 24-3. SPI Master

793538A–MICRO–7/06AT89LP213/214 [Preliminary]Figure 24-4. SPI Slave Timing (CPHA = 1)24.4 External Clock DriveFigure 24-5. External Clock Drive Wavefo

83538A–MICRO–7/06AT89LP213/214 [Preliminary]A map of the AT89LP213/214 program memory is shown in Figure 6-1. In addition to the 2Kcode space from 000

803538A–MICRO–7/06AT89LP213/214 [Preliminary] Figure 24-6. Shift Register Mode Timing Waveform24.6 Test Conditions24.6.1 AC Testing Input/Output Wavef

813538A–MICRO–7/06AT89LP213/214 [Preliminary]24.6.3 ICC Test Condition, Active Mode, All Other Pins are Disconnected24.6.4 ICC Test Condition, Idle Mo

823538A–MICRO–7/06AT89LP213/214 [Preliminary]25. Ordering Information 25.1 Standard PackageSpeed (MHz)PowerSupply Ordering Code Package Operation Rang

833538A–MICRO–7/06AT89LP213/214 [Preliminary]26. Packaging Information26.1 14P3 – PDIP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV.

843538A–MICRO–7/06AT89LP213/214 [Preliminary]26.2 14X – TSSOP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 14X (Formerly "14T

853538A–MICRO–7/06AT89LP213/214 [Preliminary]27. Revision History Revision No. HistoryRevision A – July 2006 • Initial Release

863538A–MICRO–7/06AT89LP213/214 [Preliminary]

i3538A–MICRO–7/06AT89LP213/214 [Preliminary]Table of Contents1. Description ...

ii3538A–MICRO–7/06AT89LP213/214 [Preliminary]Table of Contents (Continued)11. Power Saving Modes ...

iii3538A–MICRO–7/06AT89LP213/214 [Preliminary]Table of Contents (Continued)22. On-Chip Debug System ...

93538A–MICRO–7/06AT89LP213/214 [Preliminary]7. Special Function RegistersA map of the on-chip memory area called the Special Function Register (SFR) s

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