Rainbow-electronics AT90S1200 User Manual

1Features• Utilizes the AVR® RISC Architecture• AVR – High-performance and Low-power RISC Architecture– 89 Powerful Instructions – Most Single Clock C

10AT90S1200 0838H–AVR–03/02I/O Memory The I/O space definition of the AT90S1200 is shown in the following table.Note: Reserved and unused locations ar

11AT90S12000838H–AVR–03/02Status Register – SREG The AVR status register (SREG) at I/O space location $3F is defined as:• Bit 7 – I: Global Interrupt

12AT90S1200 0838H–AVR–03/02Reset and Interrupt HandlingThe AT90S1200 provides three different interrupt sources. These interrupts and theseparate rese

13AT90S12000838H–AVR–03/02Figure 13. Reset LogicNote: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT(falling).Powe

14AT90S1200 0838H–AVR–03/02been applied, the Power-on Reset period can be extended. Refer to Figure 15 for a tim-ing example on this.Figure 15. MCU S

15AT90S12000838H–AVR–03/02Figure 17. Watchdog Reset during OperationInterrupt Handling The AT90S1200 has two Interrupt Mask Control Registers: the GI

16AT90S1200 0838H–AVR–03/02• Bit 6 – INT0: External Interrupt Request 0 EnableWhen the INT0 bit is set (one) and the I-bit in the Status Register (SRE

17AT90S12000838H–AVR–03/02External Interrupts The External Interrupt is triggered by the INT0 pin. The interrupt can trigger on risingedge, falling ed

18AT90S1200 0838H–AVR–03/02MCU Control Register – MCUCRThe MCU Control Register contains general microcontroller control bits for general MCUcontrol f

19AT90S12000838H–AVR–03/02Sleep Modes To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc-tion must be executed. If an

2AT90S1200 0838H–AVR–03/02Description The AT90S1200 is a low-power CMOS 8-bit microcontroller based on the AVR RISCarchitecture. By executing powerfu

20AT90S1200 0838H–AVR–03/02Timer/Counter0 The AT90S1200 provides one general purpose 8-bit Timer/Counter. TheTimer/Counter0 gets the prescaled clock f

21AT90S12000838H–AVR–03/02Figure 19. Timer/Counter0 Block DiagramThe 8-bit Timer/Counter0 can select clock source from CK, prescaled CK or an externa

22AT90S1200 0838H–AVR–03/02• Bits 2, 1, 0 – CS02, CS01, CS00: Clock Select0, Bits 2, 1 and 0The Clock Select0 bits 2, 1 and 0 define the prescaling so

23AT90S12000838H–AVR–03/02Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator that runs at 1 MHz.This is the typical value

24AT90S1200 0838H–AVR–03/02Note: The frequency of the Watchdog Oscillator is voltage dependent as shown in “TypicalCharacteristics” on page 51.The WDR

25AT90S12000838H–AVR–03/02EEPROM Read/Write AccessThe EEPROM access registers are accessible in the I/O space.The write access time is in the range of

26AT90S1200 0838H–AVR–03/02• Bit 1 – EEWE: EEPROM Write EnableThe EEPROM Write Enable Signal (EEWE) is the write strobe to the EEPROM. Whenaddress and

27AT90S12000838H–AVR–03/02Analog Comparator The Analog Comparator compares the input values on the positive input PB0 (AIN0) andthe negative input PB1

28AT90S1200 0838H–AVR–03/02• Bit 3 – ACIE: Analog Comparator Interrupt EnableWhen the ACIE bit is set (one) and the I-bit in the Status Register is se

29AT90S12000838H–AVR–03/02I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digitalI/O ports. This means that the

3AT90S12000838H–AVR–03/02ing the Registers, Timer/Counter, Watchdog and Interrupt system to continuefunctioning. The Power-down mode saves the registe

30AT90S1200 0838H–AVR–03/02Port B as General Digital I/O All eight pins in Port B have equal functionality when used as digital I/O pins.PBn, General

31AT90S12000838H–AVR–03/02Port B Schematics Note that all port pins are synchronized. The synchronization latches are, however, notshown in the figure

32AT90S1200 0838H–AVR–03/02Figure 23. Port B Schematic Diagram (Pins PB2, PB3, and PB4)Figure 24. Port B Schematic Diagram (Pin PB5)2,

33AT90S12000838H–AVR–03/02Figure 25. Port B Schematic Diagram (Pin PB6)Figure 26. Port B Schematic Diagram (Pin PB7)

34AT90S1200 0838H–AVR–03/02Port D Three I/O memory address locations are allocated for Port D, one each for the DataRegister – PORTD ($12), Data Direc

35AT90S12000838H–AVR–03/02Note: n: 6…0, pin number.Alternate Functions for Port D The alternate functions of Port D are:• T0 – Port D, Bit 4T0, Timer/

36AT90S1200 0838H–AVR–03/02Figure 28. Port D Schematic Diagram (Pin PD2)Figure 29. Port D Schematic Diagram (Pin PD4)DATA BUSDDQQRESETRESETCCWDWPRDM

37AT90S12000838H–AVR–03/02Memory ProgrammingProgram and Data Memory Lock BitsThe AT90S1200 MCU provides two Lock bits that can be left unprogrammed (“

38AT90S1200 0838H–AVR–03/02the self-timed write instruction in the Serial Programming mode. During programming,the supply voltage must be in accordanc

39AT90S12000838H–AVR–03/02.Enter Programming Mode The following algorithm puts the device in Parallel Programming mode:1. Apply supply voltage accordi

4AT90S1200 0838H–AVR–03/02Figure 2. Oscillator ConnectionsNote: When using the MCU Oscillator as a clock for an external device, an HC buffer should

40AT90S1200 0838H–AVR–03/024. Give XTAL1 a positive pulse. This loads the command.B: Load Address High Byte1. Set XA1, XA0 to “00”. This enables addre

41AT90S12000838H–AVR–03/02Figure 31. Programming the Flash WaveformsFigure 32. Programming the Flash Waveforms (Continued)Reading the Flash The algo

42AT90S1200 0838H–AVR–03/02Programming the EEPROM The programming algorithm for the EEPROM data memory is as follows (refer to “Pro-gramming the Flash

43AT90S12000838H–AVR–03/02Reading the Signature Bytes The algorithm for reading the signature bytes is as follows (refer to “Programming theFlash” on

44AT90S1200 0838H–AVR–03/02Serial Downloading Both the program and data memory arrays can be programmed using the SPI bus whileRESET is pulled to GND.

45AT90S12000838H–AVR–03/023. If a Chip Erase is performed (must be done to erase the Flash), wait tWD_ERASE after the instruction, give RESET a positi

46AT90S1200 0838H–AVR–03/02Figure 35. Serial Programming WaveformsNote: a = address high bits, b = address low bits, H = 0 – Low byte, 1 – High byte,

47AT90S12000838H–AVR–03/02Serial Programming CharacteristicsFigure 36. Serial Programming TimingTable 20. Serial Programming Characteristics, TA = -

48AT90S1200 0838H–AVR–03/02Electrical CharacteristicsAbsolute Maximum Ratings*Operating Temperature... -55°C to +125°C*

49AT90S12000838H–AVR–03/02Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low.2. “Min” means the lowest value where

5AT90S12000838H–AVR–03/02Architectural OverviewThe fast-access register file concept contains 32 x 8-bit general purpose working regis-ters with a sin

50AT90S1200 0838H–AVR–03/02External Clock Drive WaveformsFigure 37. External Clock DriveExternal Clock DriveVIL1VIH1Table 23. External Clock DriveSy

51AT90S12000838H–AVR–03/02Typical CharacteristicsThe following charts show typical behavior. These figures are not tested during manu-facturing. All c

52AT90S1200 0838H–AVR–03/02Figure 39. Active Supply Current vs. VCCFigure 40. Active Supply Current vs. VCC, Device Clocked by Internal Oscillator01

53AT90S12000838H–AVR–03/02Figure 41. Idle Supply Current vs. FrequencyFigure 42. Idle Supply Current vs. VCC00.511.522.533.544.501234567891011121314

54AT90S1200 0838H–AVR–03/02Figure 43. Idle Supply Current vs. VCC, Device Clocked by Internal OscillatorFigure 44. Power-down Supply Current vs. VCC

55AT90S12000838H–AVR–03/02Figure 45. Power-down Supply Current vs. VCC, Watchdog Timer EnabledFigure 46. Internal RC Oscillator Frequency vs. VCC020

56AT90S1200 0838H–AVR–03/02Figure 47. Analog Comparator Current vs. VCCNote: Analog comparator offset voltage is measured as absolute offset.Figure 4

57AT90S12000838H–AVR–03/02Figure 49. Analog Comparator Offset Voltage vs. Common Mode VoltageFigure 50. Analog Comparator Input Leakage Current02468

58AT90S1200 0838H–AVR–03/02Note: Sink and source capabilities of I/O ports are measured on one pin at a time.Figure 51. Pull-up Resistor Current vs.

59AT90S12000838H–AVR–03/02Figure 53. I/O Pin Sink Current vs. Output VoltageFigure 54. I/O Pin Source Current vs. Output Voltage0102030405060700 0.5

6AT90S1200 0838H–AVR–03/02During interrupts and subroutine calls, the return address Program Counter (PC) isstored on the stack. The stack is a 3-leve

60AT90S1200 0838H–AVR–03/02Figure 55. I/O Pin Sink Current vs. Output VoltageFigure 56. I/O Pin Source Current vs. Output Voltage05101520250 0.5 1 1

61AT90S12000838H–AVR–03/02Note: Input threshold is measured at the center point of the hysteresis.Figure 57. I/O Pin Input Threshold Voltage vs. VCCF

62AT90S1200 0838H–AVR–03/02Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory a

63AT90S12000838H–AVR–03/02Instruction Set SummaryMnemonic Operands Description Operation Flags # ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add

64AT90S1200 0838H–AVR–03/02BIT AND BIT-TEST INSTRUCTIONSSBI P, b Set Bit in I/O Register I/O(P,b) ← 1 None 2CBI P, b Clear Bit in I/O Register I/O(P,b

65AT90S12000838H–AVR–03/02Note: 1. Order AT90S1200A-XXX for devices with the RCEN Fuse programmed.Ordering Information(1)Speed (MHz) Power Supply Orde

66AT90S1200 0838H–AVR–03/02Packaging Information20P3 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 20P3, 20-lead (0.300"/7.62

67AT90S12000838H–AVR–03/0220S7.60 (0.2992)7.40 (0.2914)0.51(0.020)0.33(0.013)10.65 (0.419)10.00 (0.394)PIN 1 ID1.27 (0.050) BSC13.00 (0.5118)12.60 (0.

68AT90S1200 0838H–AVR–03/0220Y5.38 (0.212)5.20 (0.205)7.90 (0.311)7.65 (0.301)0.65 (0.0256) BSC0.38 (0.015)0.25 (0.010)PIN 1 ID7.33 (0.289)7.07 (0.278

iAT90S12000838H–AVR–03/02Table of Contents Features...

7AT90S12000838H–AVR–03/02Program and Data Addressing ModesThe AT90S1200 AVR RISC Microcontroller supports powerful and efficient addressingmodes. This

iiAT90S1200 0838H–AVR–03/02Electrical Characteristics... 48Absolute Maximum Ratings*.

Printed on recycled paper.© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than those expressly contai

8AT90S1200 0838H–AVR–03/02Operands are contained in register r (Rr) and d (Rd). The result is stored in register d(Rd).I/O Direct Figure 9. I/O Direc

9AT90S12000838H–AVR–03/02EEPROM Data Memory The AT90S1200 contains 64 bytes of data EEPROM memory. It is organized as a sepa-rate data space, in which