Rainbow-electronics ATmega103L User Manual

1Features• Utilizes the AVR® RISC Architecture• AVR - High-performance and Low-power RISC Architecture– 120/121 Powerful Instructions - Most Single Cl

ATmega603/10310Figure 7. Memory Configurations32 Registers64 I/O Registers32 Registers64 I/O RegistersInternal SRAM(4000 x 8)Internal SRAM(4000 x 8)$

ATmega603/103100Reading the Fuse and Lock BitsThe algorithm for reading the Fuse and Lock bits is as follows (refer to Programming the Flash for detai

ATmega603/103101Table 42. Parallel Programming CharacteristicsTA = 25°C ± 10%, VCC =5V ± 10%Notes: 1. Use tWLWH_CE for Chip Erase and tWLWH_PFB for P

ATmega603/103102Serial DownloadingBoth the Flash and EEPROM memory arrays can be programmed using the serial interface while RESET is pulled to GND,or

ATmega603/1031037. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial outpu

ATmega603/103104Note: a = address high bitsb = address low bitsH = 0 - Low byte, 1 - High byteo = data outi = data inx = don’t care1 = Lock Bit 12 = L

ATmega603/103105Figure 77. Serial Programming WaveformsElectrical CharacteristicsAbsolute Maximum Ratings*Operating Temperature...

ATmega603/103106Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low2. “Min” means the lowest value where the pin is

ATmega603/103107External Data Memory TimingNotes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external cloc

ATmega603/103108Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.2. This assumes 50

ATmega603/103109Figure 78. External RAM TimingExternal Clock Drive WaveformsFigure 79. External Clock Drive WaveformsTable 50. External Clock Drive

ATmega603/10311The 4096 first Data Memory locations address both the Register file, the I/O Memory and the internal data SRAM. The first96 locations a

ATmega603/103110Typical characteristicsThe following charts show typical behavior. These data are characterized, but not tested. All current consumpti

ATmega603/103111Figure 81. Active Supply Current vs. VCCFigure 82. Idle Supply Current vs. Frequency05101520252 2.5 3 3.5 4 4.5 5 5.5 6ACTIVE SUPPLY

ATmega603/103112Figure 83. Idle Supply Current vs. VCCFigure 84. Power Down Supply Current vs. VCC012345672 2.5 3 3.5 4 4.5 5 5.5 6T = 25˚CAT = 85

ATmega603/103113Figure 85. Power Down Supply Current vs. VCCFigure 86. Power Save Supply Current vs. VCC0501001502002502 2.5 3 3.5 4 4.5 5 5.5 6T =

ATmega603/103114Figure 87. Analog Comparator Current vs. VCCAnalog comparator offset voltage is measured as absolute offsetFigure 88. Analog Compara

ATmega603/103115Figure 89. Analog Comparator Offset Voltage vs. Common Mode VoltageFigure 90. Analog Comparator Input Leakage CurrentANALOG COMPARAT

ATmega603/103116Figure 91. Watchdog Oscillator Frequency vs. VCCSink and source capabilities of I/O ports are measured on one pin at a time.Figure 92

ATmega603/103117Figure 93. Pull-Up Resistor Current vs. Input VoltageFigure 94. I/O Pin Sink Current vs. Output VoltagePULL-UP RESISTOR CURRENT vs.

ATmega603/103118Figure 95. I/O Pin Source Current vs. Output VoltageFigure 96. I/O Pin Sink Current vs. Output VoltageI/O PIN SOURCE CURRENT vs. OUT

ATmega603/103119Figure 97. I/O Pin Source Current vs. Output VoltageFigure 98. I/O Pin Input Threshold Voltage vs. VCCI/O PIN SOURCE CURRENT vs. OUT

ATmega603/10312Register Direct, Two Registers Rd and RrFigure 9. Direct Register Addressing, Two RegistersOperands are contained in register r (Rr) a

ATmega603/103120Figure 99. I/O Pin Input Hysteresis vs. VCCInput hysteresis (V)V ccI/O PIN INPUT HYSTERESIS vs. VccT = 25˚CA

ATmega603/103121Note: For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should

ATmega603/103122Instruction Set SummaryMnemonics Operands Description Operation Flags #ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add two Regis

ATmega603/103123Note: 1. Not in ATmega603.DATA TRANSFER INSTRUCTIONSELPM(1)Extended Load Program Memory R0 ← (Z+RAMPZ) None 3MOV Rd, Rr Move Between R

ATmega603/103124Ordering InformationSpeed (MHz) Power Supply Ordering Code Package Operation Range4 2.7 - 3.6V ATmega603L-4AC 64A Commercial(0°C to 70

ATmega603/103125Packaging Information*Controlling dimension: millimetersPIN 1 ID0.80(0.031) BSC16.25(0.640)SQSQ15.75(0.620)0.45(0.018)0.30(0.012)14.10

© Atmel Corporation 1999.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa

ATmega603/10313Data DirectFigure 11. Direct Data AddressingA 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify

ATmega603/10314Data IndirectFigure 13. Data Indirect Addressing Operand address is the contents of the X, Y or the Z-register.Data Indirect With Pre-

ATmega603/10315Data Indirect With Post-IncrementFigure 15. Data Indirect Addressing with Post-IncrementThe X, Y or the Z-register is incremented afte

ATmega603/10316Direct Program Address, JMP and CALLFigure 17. Direct Program Memory AddressingProgram execution continues at the address immediate in

ATmega603/10317Relative Program Addressing, RJMP and RCALLFigure 19. Relative Program Memory AddressingProgram execution continues at address PC + k

ATmega603/10318Figure 21. Single Cycle ALU OperationThe internal data SRAM access is performed in two System Clock cycles as described in Figure 22.F

ATmega603/10319I/O MemoryThe I/O space definition of the ATmega603/103 is shown in the following table:Table 3. ATmega603/103 I/O SpaceI/O Address (S

ATmega603/1032Pin ConfigurationTQFPDescriptionThe ATmega603/103 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By execu

ATmega603/10320Note: Reserved and unused locations are not shown in the tableAll the different ATmega603/103 I/Os and peripherals are placed in the I/

ATmega603/10321The different I/O and peripherals control registers are explained in the following sections.Status Register - SREGThe AVR status regist

ATmega603/10322The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stackspace in the data

ATmega603/10323•Bits 4,3 - SM1/SM0: Sleep Mode Select bits 1 and 0This bit selects between the three available sleep modes as shown in the following t

ATmega603/10324Reset and Interrupt HandlingThe ATmega603/103 provides 23 different interrupt sources. These interrupts and the separate reset vector e

ATmega603/10325The most typical program setup for the Reset and Interrupt Vector Addresses are:Address Labels Code Comments$0000 jmp RESET ; Reset Han

ATmega603/10326Figure 23. Reset LogicNote: 1. The Power-On Reset will not work unless the supply voltage has been below VPOT (falling)Table 6. Reset

ATmega603/10327Power-On ResetA Power-On Reset (POR) circuit ensures that the device is reset from power-on. As shown in Figure 23, an internal timercl

ATmega603/10328Figure 25. MCU Start-Up, RESET Controlled ExternallyExternal ResetAn external reset is generated by a low level on the RESET pin. Rese

ATmega603/10329Figure 27. Watchdog Reset During OperationMCU Status Register - MCUSRThe MCU Status Register provides information on which reset sourc

ATmega603/1033Block DiagramFigure 1. The ATmega603/103 Block DiagramPROGRAMCOUNTERINTERNALOSCILLATORWATCHDOGTIMERSTACKPOINTERPROGRAMFLASHMCU CONTROLR

ATmega603/10330Interrupt HandlingThe ATmega603/103 has two dedicated 8-bit Interrupt Mask control registers; EIMSK - External Interrupt Mask register

ATmega603/10331External Interrupt Control Register - EICR•Bits 7..0 - ISCX1, ISCX0: External Interrupt 7-4 Sense Control bitsThe External Interrupts 7

ATmega603/10332•Bit 3 - OCIE1B: Timer/Counter1 Output CompareB Match Interrupt EnableWhen the OCIE1B bit is set (one) and the I-bit in the Status Regi

ATmega603/10333•Bit 2 - TOV1: Timer/Counter1 Overflow FlagThe TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware

ATmega603/10334Power Down ModeWhen the SM1/SM0 bits are set to 10, the SLEEP instruction makes the MCU enter the Power Down Mode. In this mode,the ext

ATmega603/10335Timer/Counter PrescalersFigure 28. Prescaler for Timer/Counter 1 and Timer/Counter2For Timer/Counters 1 and 2, the four different pres

ATmega603/10336The clock source for Timer/Counter0 prescaler is named PCK0. PCK0 is by default connected to the main system clockCK. Observe that CPU

ATmega603/10337Figure 31. Timer/Counter2 Block DiagramNote: Figure 31 shows the block diagram for Timer/Counter2.The 8-bit Timer/Counter0 can select

ATmega603/10338Timer/Counter0 Control Register - TCCR0Timer/Counter2 Control Register - TCCR2•Bit 7 - Res: Reserved BitThis bit is a reserved bit in t

ATmega603/10339The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CKCPU clock. If the

ATmega603/1034Comparison Between ATmega603 and ATmega103The ATmega603 has 64K bytes of In-System Programmable Flash, 2K bytes of EEPROM, and 4K bytes

ATmega603/10340Timer/Counter0 Output Compare Register - OCR0Timer/Counter2 Output Compare Register - OCR2The output compare registers are 8-bit read/w

ATmega603/10341Figure 32. Effects on Unsynchronized OCR LatchingDuring the time between the write and the latch operation, a read from OCR0 or OCR2

ATmega603/10342•Bit 1 - OCR0UB: Output Compare Register0 Update BusyWhen Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomes

ATmega603/10343lost after a wake-up from power down, due to the unstable clock signal. The user is advised to wait for at least one second before usin

ATmega603/10344Figure 33. Timer/Counter1 Block DiagramTimer/Counter1 can also be used as a 8, 9 or 10-bit Pulse With Modulator. In this mode the coun

ATmega603/10345If the noise canceler function is enabled, the actual trigger condition for the capture event is monitored over 4 samples, andall 4 mus

ATmega603/10346Timer/Counter1 Control Register B - TCCR1B•Bit 7 - ICNC1: Input Capture1 Noise Canceler (4 CKs)When the ICNC1 bit is cleared (zero), th

ATmega603/10347Timer/Counter1 - TCNT1H and TCNT1LThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both t

ATmega603/10348Timer/Counter1 Output Compare Register - OCR1AH and OCR1ALTimer/Counter1 Output Compare Register - OCR1BH and OCR1BLThe output compare

ATmega603/10349Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read toensure that both

ATmega603/1035Port E (PE7..PE0)Port E is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port E output buffers can sink 20 mA. A

ATmega603/10350Figure 35. Effects on Unsynchronized OCR1 LatchingDuring the time between the write and the latch operation, a read from OCR1A or OCR1

ATmega603/10351Watchdog TimerThe Watchdog Timer is clocked from a separate on-chip oscillator. By controlling the Watchdog Timer prescaler, theWatchdo

ATmega603/10352Note: The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section.The WDR - Watchd

ATmega603/10353EEPROM Data Register - EEDR•Bits 7..0 - EEDR7..0: EEPROM Data:For the EEPROM write operation, the EEDR register contains the data to be

ATmega603/10354The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data oraddress is wr

ATmega603/10355Figure 37. SPI Block DiagramThe interconnection between master and slave CPUs with SPI is shown in Figure 38. The PB1(SCK) pin is the

ATmega603/10356Figure 38. SPI Master-Slave InterconnectionThe system is single buffered in the transmit direction and double buffered in the receive

ATmega603/10357Data ModesThere are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bitsCPHA a

ATmega603/10358•Bit 4 - MSTR: Master/Slave SelectThis bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is con

ATmega603/10359UARTThe ATmega603/103 features a full duplex (separate receive and transmit registers) Universal Asynchronous Receiver andTransmitter (

ATmega603/1036Clock OptionsCrystal OscillatorXTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for

ATmega603/10360Figure 41. UART TransmitterOn the Baud Rate clock following the transfer operation to the shift register, the start bit is shifted out

ATmega603/10361Data ReceptionFigure 42. UART ReceiverThe receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud

ATmega603/10362When the stop bit enters the receiver, the majority of the three samples must be one to accept the stop bit. If two or moresamples are

ATmega603/10363When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete interrupt to be executed. TXC iscleared by hardware

ATmega603/10364•Bit 0 - TXB8: Transmit Data Bit 8When CHR9 is set (one), TXB8 is the 9th data bit in the character to be transmitted.Baud Rate Generat

ATmega603/10365UART Baud Rate Register - UBRRThe UBRR is an 8-bit read/write register which specifies the UART Baud Rate according to the description

ATmega603/10366•Bit 4 - ACI: Analog Comparator Interrupt FlagThis bit is set (one) when a comparator output event triggers the interrupt mode defined

ATmega603/10367An external reference voltage must be applied to the AREF pin. This voltage must be in the range AGND - AVCC. Figure 45. Analog to Dig

ATmega603/10368PrescalingFigure 46. ADC PrescalerThe ADC contains a prescaler, which divides the system clock to an acceptable ADC clock frequency. T

ATmega603/10369Figure 48. ADC Timing DiagramADC Noise Canceler FunctionThe ADC features a noise canceler that enables conversion during idle mode to

ATmega603/1037Architectural OverviewFigure 4. The ATmega603/103 AVR RISC ArchitectureThe AVR uses a Harvard architecture concept - with separate memo

ATmega603/10370ADC Control and Status Register - ADCSR•Bit 7 - ADEN: ADC EnableWriting a logical ‘1’ to this bit enables the ADC. By clearing this bit

ATmega603/10371ADC Data Register - ADCL and ADCHWhen an ADC conversion is complete, the result is found in these two registers. It is essential that b

ATmega603/10372ADC DC CharacteristicsNotes: 1. Minimum for AVCC is 2.7V.2. Maximum for AVCC is 6.0V.Interface to external SRAMThe interface to the SRA

ATmega603/10373For details in the timing for the SRAM interface, please refer to Figure 78, Table 46, Table 47, Table 48, and Table 49 insection “DC C

ATmega603/10374Figure 52. External SRAM Access Cycle with wait stateI/O-PortsAll AVR ports have true Read-Modify-Write functionality when used as gen

ATmega603/10375Port A Data Register - PORTAPort A Data Direction Register - DDRAPort A Input Pins Address - PINAThe Port A Input Pins address - PINA -

ATmega603/10376Figure 53. Port A Schematic Diagrams (Pins PA0 - PA7)Port B Port B is an 8-bit bi-directional I/O port with internal pull-ups.Three I/

ATmega603/10377The Port B pins with alternate functions are shown in the following table:When the pins are used for the alternate function the DDRB an

ATmega603/10378Note: n: 7,6...0, pin numberAlternate Functions of Port BThe alternate pin configuration is as follows:•OC2/PWM2, Bit 7OC2/PWM2, Output

ATmega603/10379Port B SchematicsNote that all port pins are synchronized. The synchronization latches are however, not shown in the figures.Figure 54.

ATmega603/1038A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the statusregis

ATmega603/10380Figure 56. Port B Schematic Diagram (Pin PB2)Figure 57. Port B Schematic Diagram (Pin PB3)

ATmega603/10381Figure 58. Port B Schematic Diagram (Pin PB4)Figure 59. Port B Schematic Diagram (Pins PB5 and PB6)DATA BUSDDQQRESETRESETCCWDWPRDRPRL

ATmega603/10382Figure 60. Port B Schematic Diagram (Pin PB7)Port CPORT C is an 8-bit Output port.The Port C pins have alternate functions related to

ATmega603/10383Port C SchematicsFigure 61. Port C Schematic Diagram (Pins PC0 - PC7)Port DPort D is an 8 bit bi-directional I/O port with internal pu

ATmega603/10384Port D Data Direction Register - DDRDPort D Input Pins Address - PINDThe Port D Input Pins address - PIND - is not a register, and this

ATmega603/10385Port D SchematicsNote that all port pins are synchronized. The synchronization latches are however, not shown in the figures.Figure 62.

ATmega603/10386Figure 64. Port D Schematic Diagram (Pin PD5)Figure 65. Port D Schematic Diagram (Pins PD6 and PD7)DATA BUSDDQQRESETRESETCCWDWPRDMOSP

ATmega603/10387Port EPort E is an 8-bit bi-directional I/O port with internal pull-up resistors.Three I/O memory address locations are allocated for t

ATmega603/10388Port E as general digital I/OPEn, General I/O pin: The DDEn bit in the DDRE register selects the direction of this pin. If DDEn is set

ATmega603/10389Figure 66. Port E Schematic Diagram, Pin PE0Figure 67. Port E Schematic Diagram (Pin PE1)

ATmega603/1039X-register, Y-register and Z-registerThe registers R26..R31 have some added functions to their general purpose usage. These registers ar

ATmega603/10390Figure 68. Port E Schematic Diagram (Pin PE2)Figure 69. Port E Schematic Diagram (Pin PE3)DATA BUSDDQQRESETRESETCCWDWPRDMOSPULL-UPPE2

ATmega603/10391Figure 70. Port E Schematic Diagram (Pins PE4, PE5, PE6 and PE7)Port FPort F is an 8-bit input port. One I/O memory location is alloca

ATmega603/10392Figure 71. Port F Schematic Diagram (Pins PF7 - PF0)Memory ProgrammingProgram and Data Memory Lock BitsThe ATmega603/103 MCU provides

ATmega603/10393Signature BytesAll Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both s

ATmega603/10394Figure 72. Parallel Programming.Table 38. Pin Name MappingSignal Name in Programming Mode Pin Name I/O FunctionRDY/BSY PD1 O 0: Devic

ATmega603/10395Enter Programming ModeThe following algorithm puts the device in parallel programming mode:1. Apply supply voltage according to Table 3

ATmega603/10396Programming The FlashThe Flash is organized as 256/512 pages of 256 bytes each. When programming the Flash, the program data is latched

ATmega603/10397K: Repeat A through J 256/512 times or until all data have been programmed.Figure 73. Programming the Flash waveformsFigure 74. Progr

ATmega603/10398Programming The EEPROMThe programming algorithm for the EEPROM data memory is as follows (refer to Programming the Flash for details on

ATmega603/10399Reading The FlashThe algorithm for reading the Flash memory is as follows (refer to Programming the Flash for details on Command andAdd