Rainbow-electronics ATmega128RFA1 User Manual

1 8266A-MCU Wireless-12/09 ATmega128RFA1 8-bit Microcontroller with Low Power 2.4GHz Transceiv

10 8266A-MCU Wireless-12/09 ATmega128RFA1 The fast-access Register File contains 32 x 8-bit general purpose working registers with

100 8266A-MCU Wireless-12/09 ATmega128RFA1 VCO - Voltage controlled oscillator VREG - Voltage regulator XOSC - Crystal

101 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 9-28 AES_MODE Register Bits Register Bits Value Description 0 AES Mode is ECB (Ele

102 8266A-MCU Wireless-12/09 ATmega128RFA1 9.12.3 AES_STATE – AES Plain and Cipher Text Buffer Register Bit 7 6 5 4 3 2 1 0

103 8266A-MCU Wireless-12/09 ATmega128RFA1 command to the TRX_CMD bits of register TRX_STATE. The register is not accessible in SLEEP

104 8266A-MCU Wireless-12/09 ATmega128RFA1 Register Bits Value Description 0x1F STATE_TRANSITION_IN_PROGRESS 9.12.6 TRX_S

105 8266A-MCU Wireless-12/09 ATmega128RFA1 A write access to register bits TRX_CMD initiates a state transition of the ra

106 8266A-MCU Wireless-12/09 ATmega128RFA1 This register bit enables pin DIG3 and pin DIG4 to indicate the transmit st

107 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 9-37 PA_LT Register Bits Register Bits Value Description 0 2 µs 1 4 µs 2 6 µs PA

108 8266A-MCU Wireless-12/09 ATmega128RFA1 valid until the next TRX24_RX_END interrupt is issued, caused by a new frame

109 8266A-MCU Wireless-12/09 ATmega128RFA1 µs. For manually initiated ED measurements in these modes the measurement period is still 1

11 8266A-MCU Wireless-12/09 ATmega128RFA1 7.4 Status Register The Status Register contains information about the result of the most re

110 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 9-43 CHANNEL Register Bits Register Bits Value Description 11 2405 MHz 12 2410

111 8266A-MCU Wireless-12/09 ATmega128RFA1 These bits define the received power threshold of the Energy above threshold alg

112 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 9-45 SFD_VALUE Register Bits Register Bits Value Description SFD_VALUE7:0 0xA7

113 8266A-MCU Wireless-12/09 ATmega128RFA1 This register bit signals the currently selected antenna path. The selection may

114 8266A-MCU Wireless-12/09 ATmega128RFA1 Register Bits Value Description 2 Antenna 0: DIG1=L, DIG2=H 3 Default value for ANT_

115 8266A-MCU Wireless-12/09 ATmega128RFA1 • Bit 6 – TX_END - TX_END Interrupt Status • Bit 5 – AMI - Address Match Interrupt Status

116 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 9-53 DVDD_OK Register Bits Register Bits Value Description 0 Digital voltage re

117 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 9-56 BATMON_HR Register Bits Register Bits Value Description 0 Enables the low ran

118 8266A-MCU Wireless-12/09 ATmega128RFA1 Bit 3 2 1 0 NA ($152) XTAL_TRIM3 XTAL_TRIM2 XTAL_TRIM1 XTAL_TRIM0 XOSC_CTRL R

119 8266A-MCU Wireless-12/09 ATmega128RFA1 This register controls the sensitivity threshold of the receiver. • Bit 7 – RX_PDT_DIS -

12 8266A-MCU Wireless-12/09 ATmega128RFA1 stored when entering an interrupt routine and restored when returning from an interrupt r

120 8266A-MCU Wireless-12/09 ATmega128RFA1 specified in IEEE 802.15.4-2006. Reserved frame types are explained in IEEE 802.15.4 sec

121 8266A-MCU Wireless-12/09 ATmega128RFA1 Bit 3 2 1 0 NA ($158) Resx3 Resx2 Resx1 Resx0 FTN_CTRL Read/Write RW RW RW R

122 8266A-MCU Wireless-12/09 ATmega128RFA1 Bit 3 2 1 0 NA ($15B) Resx3 Resx2 Resx1 Resx0 PLL_DCU Read/Write RW RW RW

123 8266A-MCU Wireless-12/09 ATmega128RFA1 9.12.30 MAN_ID_0 – Device Identification Register (Manufacture ID Low Byte) Bit 7 6 5 4

124 8266A-MCU Wireless-12/09 ATmega128RFA1 9.12.33 SHORT_ADDR_1 – Transceiver MAC Short Address Register (High Byte) Bit 7 6 5

125 8266A-MCU Wireless-12/09 ATmega128RFA1 This register contains the bits [7:0] of the MAC IEEE address for Frame Filter address reco

126 8266A-MCU Wireless-12/09 ATmega128RFA1 9.12.40 IEEE_ADDR_4 – Transceiver MAC IEEE Address Register 4 Bit 7 6 5 4 3 2 1

127 8266A-MCU Wireless-12/09 ATmega128RFA1 • Bit 7:0 – IEEE_ADDR_77:70 - MAC IEEE Address These bits map to the bits [63:56] of the 6

128 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 9-67 MAX_CSMA_RETRIES Register Bits Register Bits Value Description 0x0 No repe

129 8266A-MCU Wireless-12/09 ATmega128RFA1 9.12.46 CSMA_SEED_1 – Transceiver Acknowledgment Frame Control Register 2 Bit 7 6 NA ($

13 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 7-2. The X-, Y-, Z-registers In the different addressing modes these address

130 8266A-MCU Wireless-12/09 ATmega128RFA1 • Bit 4 – AACK_DIS_ACK - Disable Acknowledgment Frame Transmission If this bit is s

131 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 9-71 MIN_BE Register Bits Register Bits Value Description 0 Minimum value of minim

132 8266A-MCU Wireless-12/09 ATmega128RFA1 Bit 3 2 1 0 NA ($17B) RX_LENGTH3 RX_LENGTH2 RX_LENGTH1 RX_LENGTH0 TST_RX_LENG

133 8266A-MCU Wireless-12/09 ATmega128RFA1 10 MAC Symbol Counter 10.1 Main Features The MAC symbol counter provides symbol timin

134 8266A-MCU Wireless-12/09 ATmega128RFA1 10.4 Symbol Counter (32 bit, SCCNT) The symbol counter is a 32 bit counter which

135 8266A-MCU Wireless-12/09 ATmega128RFA1 It is also possible to manually set the register in order to provide a distinct starting va

136 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 10-1. SFD and Beacon Timestamp Generation Note that Figure 10-1 contains no exac

137 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 10-2. Relative Compare Mode 326BeaconBeacon32732832932432540440540640740240348248348

138 8266A-MCU Wireless-12/09 ATmega128RFA1 10.11.2 SCCNTHL – Symbol Counter Register HL-Byte Bit 7 6 5 4 3 2 1 0 NA ($E3)

139 8266A-MCU Wireless-12/09 ATmega128RFA1 10.11.6 SCTSRHL – Symbol Counter Frame Timestamp Register HL-Byte Bit 7 6 5 4 3 2 1

14 8266A-MCU Wireless-12/09 ATmega128RFA1 7.6.2 SPL – Stack Pointer Low Bit 7 6 5 4 3 2 1 0 $3D ($5D) SP7 SP6 SP5 SP

140 8266A-MCU Wireless-12/09 ATmega128RFA1 10.11.10 SCBTSRHL – Symbol Counter Beacon Timestamp Register HL-Byte Bit 7 6 5 4 3

141 8266A-MCU Wireless-12/09 ATmega128RFA1 • Bit 7:0 – SCOCR1HH7:0 - Symbol Counter Output Compare Register 1 HH-Byte 10.11.14 SCOCR

142 8266A-MCU Wireless-12/09 ATmega128RFA1 10.11.18 SCOCR2HL – Symbol Counter Output Compare Register 2 HL-Byte Bit 7 6 5 4 3

143 8266A-MCU Wireless-12/09 ATmega128RFA1 10.11.22 SCOCR3HL – Symbol Counter Output Compare Register 3 HL-Byte Bit 7 6 5 4 3 2

144 8266A-MCU Wireless-12/09 ATmega128RFA1 feature works only if the symbol counter module operates with the 16 MHz clock from XTAL

145 8266A-MCU Wireless-12/09 ATmega128RFA1 This register is used to enable the backoff slot counter. • Bit 7:5 – Res6:4 - Reserved Bi

146 8266A-MCU Wireless-12/09 ATmega128RFA1 This interrupt indicates a compare match on compare unit 3. • Bit 1 – IRQSCP2 - Compar

147 8266A-MCU Wireless-12/09 ATmega128RFA1 11 System Clock and Clock Options This section describes the clock options for the AVR micr

148 8266A-MCU Wireless-12/09 ATmega128RFA1 11.2.2 I/O Clock – clkI/O The I/O clock is used by the majority of the I/O modules, like

149 8266A-MCU Wireless-12/09 ATmega128RFA1 To ensure sufficient startup time, the device issues an internal reset with a

15 8266A-MCU Wireless-12/09 ATmega128RFA1 7.7 Instruction Execution Timing Figure 7-4. The Parallel Instruction Fetches and Instructio

150 8266A-MCU Wireless-12/09 ATmega128RFA1 When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be us

151 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 11-2. External Clock Drive Configuration CLKIVSSexternal clock When this clock sour

152 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 11-10. Start-up Times for the Transceiver Oscillator Clock Selection Power Conditi

153 8266A-MCU Wireless-12/09 ATmega128RFA1 possible to determine the state of the prescaler - even if it were readable. Th

154 8266A-MCU Wireless-12/09 ATmega128RFA1 Register Bits Value Description 0xff Calibration value for highest oscillator frequen

155 8266A-MCU Wireless-12/09 ATmega128RFA1 Register Bits Value Description 0xB Reserved 0xC Reserved 0xD Reserved 0xE Reserved 0

156 8266A-MCU Wireless-12/09 ATmega128RFA1 12 Power Management and Sleep Modes Sleep modes enable the application to shut down unus

157 8266A-MCU Wireless-12/09 ATmega128RFA1 Active Clock Domains Oscillators Wake-up Sources Power-down X(3) X

158 8266A-MCU Wireless-12/09 ATmega128RFA1 an external level interrupt on INT7:4 or a pin change interrupt can wakeup

159 8266A-MCU Wireless-12/09 ATmega128RFA1 12.3 Power Reduction Register The Power Reduction Register (PRR), see "PRR0 –

16 8266A-MCU Wireless-12/09 ATmega128RFA1 interrupts. All enabled interrupts can then interrupt the current interrupt routine. The

160 8266A-MCU Wireless-12/09 ATmega128RFA1 used immediately. Refer to "Internal Voltage Reference" on page 179 for detail

161 8266A-MCU Wireless-12/09 ATmega128RFA1 The radio transceiver has a separate reset signal. A radio transceiver reset is initiated b

162 8266A-MCU Wireless-12/09 ATmega128RFA1 6. SRAM block #3 (upper 4k bytes), 7. Radio transceiver including AES engine, 8. Non-

163 8266A-MCU Wireless-12/09 ATmega128RFA1 AVR State Radio Transceiver State Powerchain off (2,3) DEEP SLEEP off (SLEEP or power re

164 8266A-MCU Wireless-12/09 ATmega128RFA1 • Low dropout (LDO) voltage regulator; • Configurable to use an external voltage regul

165 8266A-MCU Wireless-12/09 ATmega128RFA1 Because the calibration setting is fixed, temperature and load current variations during th

166 8266A-MCU Wireless-12/09 ATmega128RFA1 register take effect in the regulator circuit. The write access from the software must b

167 8266A-MCU Wireless-12/09 ATmega128RFA1 The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP

168 8266A-MCU Wireless-12/09 ATmega128RFA1 12.6.3 PRR1 – Power Reduction Register 1 Bit 7 6 5 4 3 2 1 0 NA ($65) Res PR

169 8266A-MCU Wireless-12/09 ATmega128RFA1 • Bit 2 – PRRAM2 - Power Reduction SRAM 2 Setting this bit to one will disable the SRAM bl

17 8266A-MCU Wireless-12/09 ATmega128RFA1 Assembly Code Example ; note: will enter sleep before any pending ; interrupt(s) C Code Exam

170 8266A-MCU Wireless-12/09 ATmega128RFA1 12.6.6 DRTRAM0 – Data Retention Configuration Register of SRAM 0 Bit 7 6 5 4 3 2

171 8266A-MCU Wireless-12/09 ATmega128RFA1 12.6.8 DRTRAM2 – Data Retention Configuration Register of SRAM 2 Bit 7 6 5 4 3 2 1

172 8266A-MCU Wireless-12/09 ATmega128RFA1 12.6.10 LLCR – Low Leakage Voltage Regulator Control Register Bit 7 6 5 4 3 2 1

173 8266A-MCU Wireless-12/09 ATmega128RFA1 12.6.11 LLDRH – Low Leakage Voltage Regulator Data Register (High-Byte) Bit 7 6 5 4 3

174 8266A-MCU Wireless-12/09 ATmega128RFA1 12.6.13 DPDS0 – Port Driver Strength Register 0 Bit 7 6 5 4 3 2 1 0 NA ($136)

175 8266A-MCU Wireless-12/09 ATmega128RFA1 12.6.14 DPDS1 – Port Driver Strength Register 1 Bit 7 6 5 4 3 2 1 0 NA ($137) Re

176 8266A-MCU Wireless-12/09 ATmega128RFA1 13 System Control and Reset 13.1 Resetting the AVR During reset, all I/O Registers

177 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 13-1. Reset Logic EVDDRSTNDelay CountersS QRMCU Status Register (MCUSR)BODLEVEL

178 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 13-3. MCU Start-up, RSTN Extended Externally VCCRSTNTIME-OUTINTERNALRESETVPOTVRST

179 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 13-5. Brown-out Reset During Operation EVDDRSTNTIME-OUTINTERNALRESETtTOUTVBOT-VBOT+

18 8266A-MCU Wireless-12/09 ATmega128RFA1 8 AVR Memories This section describes the different memories in the ATmega128RFA1

180 8266A-MCU Wireless-12/09 ATmega128RFA1 13.4 Watchdog Timer 13.4.1 Features • Clocked from separate On-chip Oscillator • 3 Op

181 8266A-MCU Wireless-12/09 ATmega128RFA1 program security, alterations to the Watchdog set-up must follow timed sequences. The seque

182 8266A-MCU Wireless-12/09 ATmega128RFA1 Note: 1. The example code assumes that the part specific header file is included. If

183 8266A-MCU Wireless-12/09 ATmega128RFA1 13.5 Register Description 13.5.1 MCUSR – MCU Status Register Bit 7 6 5 4 3 2 1 0

184 8266A-MCU Wireless-12/09 ATmega128RFA1 • Bit 6 – WDIE - Watchdog Timeout Interrupt Enable When this bit is written to one and

185 8266A-MCU Wireless-12/09 ATmega128RFA1 Register Bits Value Description 0x04 Oscillator Cycles 32k, (0.25s) 0x05 Oscillator Cyc

186 8266A-MCU Wireless-12/09 ATmega128RFA1 14 I/O-Ports 14.1 Introduction All ATmega128RFA1 ports have true Read-Modify-Write

187 8266A-MCU Wireless-12/09 ATmega128RFA1 14.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional inte

188 8266A-MCU Wireless-12/09 ATmega128RFA1 14.2.3 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, indepe

189 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 14-3. Synchronization when reading an external applied pin value Consider the cloc

19 8266A-MCU Wireless-12/09 ATmega128RFA1 The five different addressing modes for the data memory cover: Direct, Indirect

190 8266A-MCU Wireless-12/09 ATmega128RFA1 Assembly Code Example(1) … ; Define pull-ups and set outputs high ; Define directions fo

191 8266A-MCU Wireless-12/09 ATmega128RFA1 described above, floating inputs should be avoided to reduce current consumption in all oth

192 8266A-MCU Wireless-12/09 ATmega128RFA1 Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.

193 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 14-3. Port B Pins Alternate Functions Port Pin Alternate Functions PB7 OC0A/

194 8266A-MCU Wireless-12/09 ATmega128RFA1 PCINT4, Pin Change Interrupt source 4: The PB4 pin can serve as an external interrupt so

195 8266A-MCU Wireless-12/09 ATmega128RFA1 Signal Name PB7/OC0A/OC1C PB6/OC1B PB5/OC1A PB4/OC2A PUOV 0 0 0 0

196 8266A-MCU Wireless-12/09 ATmega128RFA1 • T1 – Port D, Bit 6 T1, this is Timer/Counter1 counter source. • XCK1 – Port D, Bit 5

197 8266A-MCU Wireless-12/09 ATmega128RFA1 Signal Name PD7/T0 PD6/T1 PD5/XCK1 PD4/ICP1 DDOV 0 0 1 0 PVOE 0 0 XCK1 OUTPUT ENA

198 8266A-MCU Wireless-12/09 ATmega128RFA1 Port Pin Alternate Function PE0 RXD0/PCINT8 (USART0 Receive Pin or Pin Change Interrupt

199 8266A-MCU Wireless-12/09 ATmega128RFA1 RXD0, USART0 Receive Pin. Receive Data (Data input pin for the USART0). When the USART0 rec

2 8266A-MCU Wireless-12/09 ATmega128RFA1 1 Pin Configurations Figure 1-1. Pinout ATmega128RFA1 Note: The large center pad undernea

20 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 8-8. On-Chip Data SRAM Access Cycles clkWRRDDataDataAddressAddress validT1 T2 T3Co

200 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 14-12. Port F Pins Alternate Functions Port Pin Alternate Function PF7 ADC7/TDI

201 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 14-13. Overriding Signals for Alternate Functions PF7:PF4 Signal Name PF7/ADC7/TDI P

202 8266A-MCU Wireless-12/09 ATmega128RFA1 TOSC2, Timer Oscillator pin 1: Setting the AS2 bit to one and the EXCLKAMR bit

203 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 14-17. Overriding Signals for Alternate Functions PG1:PG0 Signal Name PG1/DIG1 PG0/D

204 8266A-MCU Wireless-12/09 ATmega128RFA1 14.4 Register Description 14.4.1 MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1

205 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 14-20 PDDRV Register Bits Register Bits Value Description 0 2 mA 1 4 mA 2 6 mA P

206 8266A-MCU Wireless-12/09 ATmega128RFA1 logic zero or the pin has to be configured as an output pin. If PORTBn is written logic

207 8266A-MCU Wireless-12/09 ATmega128RFA1 14.4.8 DDRD – Port D Data Direction Register Bit 7 6 5 4 3 2 1 0 $0A ($2A) DDD7

208 8266A-MCU Wireless-12/09 ATmega128RFA1 The DDEn bit in the DDRE Register selects the direction of the PORTE pin n. If DDEn is w

209 8266A-MCU Wireless-12/09 ATmega128RFA1 14.4.15 PINF – Port F Input Pins Address Bit 7 6 5 4 3 2 1 0 $0F ($2F) PINF7:0

21 8266A-MCU Wireless-12/09 ATmega128RFA1 The following code examples show one assembly and one C function for writing to the EEPROM.

210 8266A-MCU Wireless-12/09 ATmega128RFA1 14.4.18 PING – Port G Input Pins Address Bit 7 6 5 4 3 2 1 0 $12 ($32) Res1

211 8266A-MCU Wireless-12/09 ATmega128RFA1 15 Interrupts This section describes the specifics of the interrupt handling as p

212 8266A-MCU Wireless-12/09 ATmega128RFA1 Vector No. Program Address(2) Source Interrupt Definition 29 $003A ADC ADC Conversi

213 8266A-MCU Wireless-12/09 ATmega128RFA1 Vector No. Program Address(2) Source Interrupt Definition 65 $0082 SCNT_CMP1 Symbol Co

214 8266A-MCU Wireless-12/09 ATmega128RFA1 0X0018 jmp WDT ;Watchdog Timeout Handler 0x001A jmp TIM2_COMPA ;Timer2 CompareA H

215 8266A-MCU Wireless-12/09 ATmega128RFA1 0x008C jmp AES_READY ;Encryption/Decryption Ready H. 0x008E jmp BAT_LOW ;Batterie Monit

216 8266A-MCU Wireless-12/09 ATmega128RFA1 0xF073 out SPH,r16 ;Set Stack Pointer to top of RAM 0xF074 ldi r16,lo

217 8266A-MCU Wireless-12/09 ATmega128RFA1 When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is pr

218 8266A-MCU Wireless-12/09 ATmega128RFA1 16 External Interrupts The External Interrupts are triggered by the INT7:0 pin

219 8266A-MCU Wireless-12/09 ATmega128RFA1 16.2 Register Description 16.2.1 EICRA – External Interrupt Control Register A Bit 7 6

22 8266A-MCU Wireless-12/09 ATmega128RFA1 Assembly Code Example sbic EECR,EEPE rjcmp EEPROM_read ; Set up address (r18:r17) i

220 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 16-128 ISC1 Register Bits Register Bits Value Description 0x00 The low level of

221 8266A-MCU Wireless-12/09 ATmega128RFA1 Register Bits Value Description request. 0x01 Any edge of INTn generates asynchronously

222 8266A-MCU Wireless-12/09 ATmega128RFA1 16.2.3 EIMSK – External Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 $1D ($3D)

223 8266A-MCU Wireless-12/09 ATmega128RFA1 16.2.5 PCICR – Pin Change Interrupt Control Register Bit 7 6 5 4 3 2 1 0 NA ($68)

224 8266A-MCU Wireless-12/09 ATmega128RFA1 • Bit 1 – PCIF1 - Pin Change Interrupt Flag 1 When a logic change on any PCINT15:

225 8266A-MCU Wireless-12/09 ATmega128RFA1 • Bit 7:1 – PCINT15:9 - Pin Change Enable Mask Bits 15:9 of the PCMSK1 register have

226 8266A-MCU Wireless-12/09 ATmega128RFA1 17 8-bit Timer/Counter0 with PWM 17.1 Features • Two Independent Output Compare Units •

227 8266A-MCU Wireless-12/09 ATmega128RFA1 17.2.1 Registers The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) a

228 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 17-2. Counter Unit Block Diagram DATA BUSTCNTn Control LogiccountTOVn(Int.Req.)Cl

229 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 17-3. Output Compare Unit, Block Diagram OCFnx (Int.Req.)= (8-bit Comparator )OCRnxO

23 8266A-MCU Wireless-12/09 ATmega128RFA1 8.4 EEPROM Register Description 8.4.1 EEARH – EEPROM Address Register High Byte Bit 7 6 5

230 8266A-MCU Wireless-12/09 ATmega128RFA1 Be aware that the COM0x1:0 bits are not double buffered together with the com

231 8266A-MCU Wireless-12/09 ATmega128RFA1 A state change of the COM0x1:0 bits will have effect at the first Compare Match after the b

232 8266A-MCU Wireless-12/09 ATmega128RFA1 17.7 Modes of Operation The mode of operation i.e., the behavior of the Timer/Counter an

233 8266A-MCU Wireless-12/09 ATmega128RFA1 for the counter, hence also its resolution. This mode allows greater control of

234 8266A-MCU Wireless-12/09 ATmega128RFA1 PWM mode well suited for power regulation, rectification and DAC applications.

235 8266A-MCU Wireless-12/09 ATmega128RFA1 equal to MAX will result in a constantly high or low output (depending on the polarity of t

236 8266A-MCU Wireless-12/09 ATmega128RFA1 In phase correct PWM mode, the compare unit allows generating PWM waveforms on the OC0x

237 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 17-9 shows the same timing data, but with the prescaler enabled. Figure 17-9. Timer/

238 8266A-MCU Wireless-12/09 ATmega128RFA1 17.9 Register Description 17.9.1 GTCCR – General Timer/Counter Control Register Bit 7

239 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 17-6 COM0A Register Bits Register Bits Value Description 0 Normal port operation,

24 8266A-MCU Wireless-12/09 ATmega128RFA1 8.4.4 EECR – EEPROM Control Register Bit 7 6 5 4 3 2 1 0 $1F ($3F) Res1 Res0

240 8266A-MCU Wireless-12/09 ATmega128RFA1 17.9.3 TCCR0B – Timer/Counter0 Control Register B Bit 7 6 5 4 3 2 1 0 $25 ($45

241 8266A-MCU Wireless-12/09 ATmega128RFA1 Register Bits Value Description 0x04 clk_IO/256 (from prescaler) 0x05 clk_IO/1024 (from

242 8266A-MCU Wireless-12/09 ATmega128RFA1 17.9.6 OCR0B – Timer/Counter0 Output Compare Register B Bit 7 6 5 4 $28 ($48) OCR

243 8266A-MCU Wireless-12/09 ATmega128RFA1 17.9.8 TIFR0 – Timer/Counter0 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 $15 ($3

244 8266A-MCU Wireless-12/09 ATmega128RFA1 18 16-bit Timer/Counter (Timer/Counter 1, 3, 4, and 5) 18.1 Features • True 16-bit Desi

245 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 18-1. 16-bit Timer/Counter Block Diagram(1) Clock SelectTimer/CounterDATA BUSOCRnAOC

246 8266A-MCU Wireless-12/09 ATmega128RFA1 Timer/Counter value at all time. The result of the compare can be used by

247 8266A-MCU Wireless-12/09 ATmega128RFA1 Assembly Code Examples(1) ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r

248 8266A-MCU Wireless-12/09 ATmega128RFA1 C Code Examples(1) unsigned int TIM16_ReadTCNTn( void ) { unsigned char sreg; unsign

249 8266A-MCU Wireless-12/09 ATmega128RFA1 C Code Examples(1) void TIM16_WriteTCNTn( unsigned int i ) { unsigned char sreg; unsign

25 8266A-MCU Wireless-12/09 ATmega128RFA1 The EEPROM can not be programmed during a CPU write to the Flash memory. The software must

250 8266A-MCU Wireless-12/09 ATmega128RFA1 Clear Clear TCNTn (set all bits to zero); clkTn Timer/Counter clock; TOP Signalize th

251 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 18-3. Input Capture Unit Block Diagram ICFn (Int.Req.)AnalogComparatorWRITEICRn (16

252 8266A-MCU Wireless-12/09 ATmega128RFA1 clock cycles. Note that the input of the noise canceller and edge detector

253 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 18-4 shows a block diagram of the Output Compare unit. The small “n” in the

254 8266A-MCU Wireless-12/09 ATmega128RFA1 18.7.1 Force Output Compare In non-PWM Waveform Generation modes, the match output of th

255 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 18-5. Compare Match Output Unit, Schematic PORTDDRD QD QOCnxPinOCnxD QWaveformGenera

256 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 18-3. Compare Output Mode, Fast PWM COMnA1 COMnB1 COMnC1 COMnA0 COMnB0 COMnC0 Des

257 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 18-5. Waveform Generation Mode Bit Description (1) Mode WGMn3 WGMn2 (CTCn) WGMn1 (PW

258 8266A-MCU Wireless-12/09 ATmega128RFA1 cleared to zero when the counter value (TCNTn) matches either the OCRnA (WGMn3:0 = 4)

259 8266A-MCU Wireless-12/09 ATmega128RFA1 OCnx is set at BOTTOM. In inverting Compare Output mode output is set on compare match and

26 8266A-MCU Wireless-12/09 ATmega128RFA1 8.6 General Purpose I/O Registers The ATmega128RFA1 contains three General Purpose I/O

260 8266A-MCU Wireless-12/09 ATmega128RFA1 The procedure for updating ICRn differs from updating OCRnA when used for defining the T

261 8266A-MCU Wireless-12/09 ATmega128RFA1 up-counting, and set on the compare match while down-counting. In inverting Outpu

262 8266A-MCU Wireless-12/09 ATmega128RFA1 TCNTn and the OCRnx. Note that when working with fixed TOP values, the unused bits are m

263 8266A-MCU Wireless-12/09 ATmega128RFA1 The PWM resolution for the phase and frequency correct PWM mode can be defined by either IC

264 8266A-MCU Wireless-12/09 ATmega128RFA1 The definition of TOP with the ICRn Register works well when using fixed TOP values. Com

265 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 18-11 shows the same timing data, but with the prescaler enabled. Figure 18-11. Ti

266 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 18-13 shows the same timing data, but with the prescaler enabled. Figure 18-13. T

267 8266A-MCU Wireless-12/09 ATmega128RFA1 The COM1B1:0 bits control the output compare behavior of pin OC1B. If one or both of the C

268 8266A-MCU Wireless-12/09 ATmega128RFA1 Register Bits Value Description 0x2 PWM, phase correct, 9-bit 0x3 PWM, phase correct

269 8266A-MCU Wireless-12/09 ATmega128RFA1 Combined with the WGM11:0 bits found in the TCCR1A Register, these bits control the countin

27 8266A-MCU Wireless-12/09 ATmega128RFA1 8.7.1 PORTA – Port A Data Register Bit 7 6 5 4 3 2 1 0 $02 ($22) PORTA7:0 PORTA

270 8266A-MCU Wireless-12/09 ATmega128RFA1 18.11.3 TCCR1C – Timer/Counter1 Control Register C Bit 7 6 5 4 3 2 1 0 NA ($82

271 8266A-MCU Wireless-12/09 ATmega128RFA1 16-bit registers. See section "Accessing 16-bit Registers" for details.

272 8266A-MCU Wireless-12/09 ATmega128RFA1 The Output Compare Registers contain a 16-bit value that is continuously com

273 8266A-MCU Wireless-12/09 ATmega128RFA1 18.11.10 OCR1CH – Timer/Counter1 Output Compare Register C High Byte Bit 7 6 5 4 3 2

274 8266A-MCU Wireless-12/09 ATmega128RFA1 18.11.13 ICR1L – Timer/Counter1 Input Capture Register Low Byte Bit 7 6 5 4 3 2 1

275 8266A-MCU Wireless-12/09 ATmega128RFA1 The corresponding Interrupt Vector is executed when the OCF1A Flag, located in T

276 8266A-MCU Wireless-12/09 ATmega128RFA1 overflows. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vec

277 8266A-MCU Wireless-12/09 ATmega128RFA1 Register Bits Value Description (set output to high level). • Bit 3:2 – COM3C1:0 - Compa

278 8266A-MCU Wireless-12/09 ATmega128RFA1 Register Bits Value Description 0xE Fast PWM, TOP = ICRn 0xF Fast PWM, TOP = OCRnA

279 8266A-MCU Wireless-12/09 ATmega128RFA1 Register Bits Value Description 0x7 Fast PWM, 10-bit 0x8 PWM, Phase and frequency corre

28 8266A-MCU Wireless-12/09 ATmega128RFA1 8.7.5 DDRC – Port C Data Direction Register Bit 7 6 5 4 3 2 1 0 $07 ($27) DDC7

280 8266A-MCU Wireless-12/09 ATmega128RFA1 • Bit 6 – FOC3B - Force Output Compare for Channel B The FOC3B bit is only active when

281 8266A-MCU Wireless-12/09 ATmega128RFA1 The two Timer/Counter I/O locations (TCNT3H and TCNT3L, combined TCNT3) give dire

282 8266A-MCU Wireless-12/09 ATmega128RFA1 18.11.23 OCR3BH – Timer/Counter3 Output Compare Register B High Byte Bit 7 6 5 4 3

283 8266A-MCU Wireless-12/09 ATmega128RFA1 18.11.26 OCR3CL – Timer/Counter3 Output Compare Register C Low Byte Bit 7 6 5 4 3 2

284 8266A-MCU Wireless-12/09 ATmega128RFA1 18.11.29 TIMSK3 – Timer/Counter3 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 N

285 8266A-MCU Wireless-12/09 ATmega128RFA1 This bit is reserved for future use. A read access always will return zero. A write access

286 8266A-MCU Wireless-12/09 ATmega128RFA1 COM4A1:0 bit functionality when the WGM43:0 bits are set to a normal or a CTC mode (non-

287 8266A-MCU Wireless-12/09 ATmega128RFA1 Register Bits Value Description 0x5 Fast PWM, 8-bit 0x6 Fast PWM, 9-bit 0x7 Fast PWM,

288 8266A-MCU Wireless-12/09 ATmega128RFA1 Register Bits Value Description 0x4 CTC, TOP = OCRnA 0x5 Fast PWM, 8-bit 0x6 Fast P

289 8266A-MCU Wireless-12/09 ATmega128RFA1 Compare Match (CTC) mode using OCR4A as TOP. The FOC4A bits are always read as zero. • Bit

29 8266A-MCU Wireless-12/09 ATmega128RFA1 9 Low-Power 2.4 GHz Transceiver 9.1 Features • High performance RF-CMOS 2.4 GHz radio trans

290 8266A-MCU Wireless-12/09 ATmega128RFA1 The two Timer/Counter I/O locations (TCNT4H and TCNT4L, combined TCNT4) give

291 8266A-MCU Wireless-12/09 ATmega128RFA1 18.11.38 OCR4BH – Timer/Counter4 Output Compare Register B High Byte Bit 7 6 5 4 3 2

292 8266A-MCU Wireless-12/09 ATmega128RFA1 18.11.41 OCR4CL – Timer/Counter4 Output Compare Register C Low Byte Bit 7 6 5 4 3

293 8266A-MCU Wireless-12/09 ATmega128RFA1 18.11.44 TIMSK4 – Timer/Counter4 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 NA (

294 8266A-MCU Wireless-12/09 ATmega128RFA1 • Bit 5 – ICF4 - Timer/Counter4 Input Capture Flag The Timer/Counter4 has only limi

295 8266A-MCU Wireless-12/09 ATmega128RFA1 Register Bits Value Description 1 Reserved 2 Reserved 3 Reserved • Bit 5:4 – COM5B1:0

296 8266A-MCU Wireless-12/09 ATmega128RFA1 Register Bits Value Description 0x8 PWM, Phase and frequency correct, TOP = ICRn 0x9

297 8266A-MCU Wireless-12/09 ATmega128RFA1 Register Bits Value Description 0x7 Fast PWM, 10-bit 0x8 PWM, Phase and frequency corre

298 8266A-MCU Wireless-12/09 ATmega128RFA1 The FOC5B bit is only active when the WGM53:0 bits specify a non-PWM mode. When writing

299 8266A-MCU Wireless-12/09 ATmega128RFA1 counter. To ensure that both the high and low bytes are read and written simultaneously whe

3 8266A-MCU Wireless-12/09 ATmega128RFA1 3 Overview The ATmega128RFA1 is a low-power CMOS 8 bit microcontroller based on the

30 8266A-MCU Wireless-12/09 ATmega128RFA1 The ATmega128RFA1 features a low-power 2.4 GHz radio transceiver designed for in

300 8266A-MCU Wireless-12/09 ATmega128RFA1 The Output Compare Registers contain a 16-bit value that is continuously com

301 8266A-MCU Wireless-12/09 ATmega128RFA1 18.11.56 OCR5CL – Timer/Counter5 Output Compare Register C Low Byte Bit 7 6 5 4 3 2

302 8266A-MCU Wireless-12/09 ATmega128RFA1 18.11.59 TIMSK5 – Timer/Counter5 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 N

303 8266A-MCU Wireless-12/09 ATmega128RFA1 • Bit 5 – ICF5 - Timer/Counter5 Input Capture Flag The Timer/Counter5 has only limited

304 8266A-MCU Wireless-12/09 ATmega128RFA1 19 Timer/Counter 0, 1, 3, 4, and 5 Prescaler Timer/Counter 0, 1, 3, 4, and 5 shar

305 8266A-MCU Wireless-12/09 ATmega128RFA1 Enabling and disabling of the clock input must be done when Tn has been stable for at least

306 8266A-MCU Wireless-12/09 ATmega128RFA1 This bit is reserved for future use. A read access always will return zero. A write acce

307 8266A-MCU Wireless-12/09 ATmega128RFA1 20 Output Compare Modulator (OCM1C0A) 20.1 Overview The Output Compare Modulator (OCM) allo

308 8266A-MCU Wireless-12/09 ATmega128RFA1 When the modulator is enabled the type of modulation (logical AND or OR) ca

309 8266A-MCU Wireless-12/09 ATmega128RFA1 21 8-bit Timer/Counter2 with PWM and Asynchronous Operation 21.1 Features Timer/Counter2 is

31 8266A-MCU Wireless-12/09 ATmega128RFA1 The received RF signal at pins RFN and RFP is differentially fed through the low-noise ampli

310 8266A-MCU Wireless-12/09 ATmega128RFA1 register or bit defines in a program, the precise form must be used, i.e.,

311 8266A-MCU Wireless-12/09 ATmega128RFA1 "Asynchronous Operation of Timer/Counter2" on page 320. For details on clock sour

312 8266A-MCU Wireless-12/09 ATmega128RFA1 not (inverted or non-inverted PWM). For non-PWM modes the COM2x1:0 bits control w

313 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 21-3. CTC Mode, Timing Diagram TCNTnOCn(Toggle)OCnx Interrupt Flag Set1 4Period2 3(C

314 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 21-4. Fast PWM Mode, Timing Diagram TCNTnOCRnx Update andTOVn Interrupt Flag Set

315 8266A-MCU Wireless-12/09 ATmega128RFA1 includes non-inverted and inverted PWM outputs. The small horizontal line marks

316 8266A-MCU Wireless-12/09 ATmega128RFA1 • OCR2A changes its value from MAX, like in Figure 21-5 on page 315. When t

317 8266A-MCU Wireless-12/09 ATmega128RFA1 The OCR2x Register access may seem complex, but this is not the case. When th

318 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 21-7. Compare Match Output Unit, Schematic PORTDDRD QD QOCnxPinOCnxD QWaveformGen

319 8266A-MCU Wireless-12/09 ATmega128RFA1 COM2x1 COM2x0 Description 1 0 Clear OC2x on Compare Match, set OC2x at BOTTOM, (non-in

32 8266A-MCU Wireless-12/09 ATmega128RFA1 register access is only possible, if the transceiver clock is available. There

320 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 21-9 below shows the same timing data, but with the prescaler enabled. Figure 21-

321 8266A-MCU Wireless-12/09 ATmega128RFA1 • Warning: When switching between asynchronous and synchronous clocking of Timer/C

322 8266A-MCU Wireless-12/09 ATmega128RFA1 advanced by at least one before the processor can read the counter value. A

323 8266A-MCU Wireless-12/09 ATmega128RFA1 The TOSC1 pin is selected by setting the EXCLKAMR bit in the ASSR register to logic zero.

324 8266A-MCU Wireless-12/09 ATmega128RFA1 • Bit 1 – OCIE2A - Timer/Counter2 Output Compare Match A Interrupt Enable When the OCIE

325 8266A-MCU Wireless-12/09 ATmega128RFA1 21.11.3 TCCR2A – Timer/Counter2 Control Register A Bit 7 6 5 4 3 2 1 0 NA ($B0)

326 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 21-9 WGM2 Register Bits Register Bits Value Description 0x0 Normal mode of oper

327 8266A-MCU Wireless-12/09 ATmega128RFA1 the counter even if the pin is configured as an output. This feature allows s

328 8266A-MCU Wireless-12/09 ATmega128RFA1 The Output Compare Register B contains an 8-bit value that is continuously compared wit

329 8266A-MCU Wireless-12/09 ATmega128RFA1 this bit is cleared by hardware. A logical zero in this bit indicates that OCR2B is ready t

33 8266A-MCU Wireless-12/09 ATmega128RFA1 A second configuration bit (SLPTR) is used to control frame transmission or sleep and wakeup

330 8266A-MCU Wireless-12/09 ATmega128RFA1 22 SPI- Serial Peripheral Interface 22.1 Features The Serial Peripheral Interface (S

331 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 22-1. SPI Block Diagram(1) SPI2XSPI2XDIVIDER/2/4/8/16/32/64/128 Note: 1. Refer to

332 8266A-MCU Wireless-12/09 ATmega128RFA1 control logic will sample the incoming signal of the SCK pin. To ensure correct sampling

333 8266A-MCU Wireless-12/09 ATmega128RFA1 C Code Example(1) void SPI_MasterInit(void) { /* Set MOSI and SCK output, all others inp

334 8266A-MCU Wireless-12/09 ATmega128RFA1 C Code Example(1) void SPI_SlaveInit(void) { /* Set MISO output, all others input */

335 8266A-MCU Wireless-12/09 ATmega128RFA1 22.3.3 Data Mode There are four combinations of SCK phase and polarity with respe

336 8266A-MCU Wireless-12/09 ATmega128RFA1 22.4 Register Description 22.4.1 SPCR – SPI Control Register Bit 7 6 5 4 3 2 1

337 8266A-MCU Wireless-12/09 ATmega128RFA1 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR

338 8266A-MCU Wireless-12/09 ATmega128RFA1 22.4.3 SPDR – SPI Data Register Bit 7 6 5 4 3 2 1 0 $2E ($4E) SPDR7:0 SPDR R

339 8266A-MCU Wireless-12/09 ATmega128RFA1 23 USART 23.1 Features • Full duplex operation (independent serial receive and transmit re

34 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 9-2. Interrupt Description in Basic Operating Mode IRQ Vector Number/ Priority (1)

340 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 23-1. USART Block Diagram(1) Note: 1. See "Figure 1-1" on page

341 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 22-2 on page 331 shows a block diagram of the clock generation logic. Figure 23-2.

342 8266A-MCU Wireless-12/09 ATmega128RFA1 Operating Mode Equation for Calculating Baud Rate(1) Equation for Calculating UBRR Va

343 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 23-3. Synchronous Mode XCKn Timing The UCPOLn bit UCRSC selects which XCKn clock ed

344 8266A-MCU Wireless-12/09 ATmega128RFA1 The USART Character Size (UCSZn2:0) bits select the number of data bits in

345 8266A-MCU Wireless-12/09 ATmega128RFA1 C Code Example(1) #define FOSC 8000000// Clock Speed #define BAUD 9600 #define (MYUBRR FOS

346 8266A-MCU Wireless-12/09 ATmega128RFA1 Assembly Code Example(1) USART_Transmit: ; Wait for empty transmit buffer sbis UCSRnA

347 8266A-MCU Wireless-12/09 ATmega128RFA1 C Code Example(1)(2) void USART_Transmit( unsigned int data ) { /* Wait for empty transmi

348 8266A-MCU Wireless-12/09 ATmega128RFA1 23.6.4 Parity Generator The parity generator calculates the parity bit for the serial fr

349 8266A-MCU Wireless-12/09 ATmega128RFA1 C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for data to be received *

35 8266A-MCU Wireless-12/09 ATmega128RFA1 9.4 Operating Modes 9.4.1 Basic Operating Mode This section summarizes all states to provide

350 8266A-MCU Wireless-12/09 ATmega128RFA1 C Code Example(1) unsigned int USART_Receive( void ) { unsigned char status, resh, res

351 8266A-MCU Wireless-12/09 ATmega128RFA1 read (as one), and the FEn flag will be one when the stop bit was incorrect (zero). This fl

352 8266A-MCU Wireless-12/09 ATmega128RFA1 C Code Example(1) void USART_Flush( void ) { unsigned char dummy; while ( UCSRnA &am

353 8266A-MCU Wireless-12/09 ATmega128RFA1 shows the sampling of the data bits and the parity bit. Each of the samples is given a numb

354 8266A-MCU Wireless-12/09 ATmega128RFA1 The following equations can be used to calculate the ratio of the incoming data rate and

355 8266A-MCU Wireless-12/09 ATmega128RFA1 division of the system frequency to get the baud rate wanted. In this case an

356 8266A-MCU Wireless-12/09 ATmega128RFA1 Do not use read-modify-write instructions (SBI and CBI) to set or clear the MPCMn bit. T

357 8266A-MCU Wireless-12/09 ATmega128RFA1 • Bit 5 – UDRE0 - USART Data Register Empty The UDRE0 Flag indicates if the transmit buffe

358 8266A-MCU Wireless-12/09 ATmega128RFA1 Writing this bit to one enables interrupt on the UDRE0 Flag. A Data Registe

359 8266A-MCU Wireless-12/09 ATmega128RFA1 compare it to the UPM0 setting. If a mismatch is detected, the UPE0 Flag in UCSR0A will be

36 8266A-MCU Wireless-12/09 ATmega128RFA1 Bit SLPTR is a multifunctional bit (refer to section "Transceiver Pin Register TRXPR

360 8266A-MCU Wireless-12/09 ATmega128RFA1 23.10.5 UBRR0H – USART0 Baud Rate Register High Byte Bit 7 6 5 4 3 2 1 0 NA ($

361 8266A-MCU Wireless-12/09 ATmega128RFA1 Receive Data Buffer Register (RXB). For 5-, 6-, or 7-bit characters the upper unused

362 8266A-MCU Wireless-12/09 ATmega128RFA1 This bit is set if the next character in the receive buffer had a Parity Error when rece

363 8266A-MCU Wireless-12/09 ATmega128RFA1 The UCSZ12 bits combined with the UCSZ11:0 bit in UCSR1C sets the number of data bits (Char

364 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 23-11 USBS1 Register Bits Register Bits Value Description 0x00 1-bit USBS1 0x01

365 8266A-MCU Wireless-12/09 ATmega128RFA1 • Bit 3:0 – UBRR11:8 - USART Baud Rate Register These bits represent bits [11:8] of

366 8266A-MCU Wireless-12/09 ATmega128RFA1 fOSC = 1.8432 MHz fOSC = 2.0000 MHz fOSC = 3.6864 MHz U2Xn = 0 U2Xn = 1 U2Xn =

367 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 23-16. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued

368 8266A-MCU Wireless-12/09 ATmega128RFA1 24 USART in SPI Mode The Universal Synchronous and Asynchronous Serial Receiver a

369 8266A-MCU Wireless-12/09 ATmega128RFA1 24.2.1 Clock Generation The Clock Generation logic generates the base clock for the Transmi

37 8266A-MCU Wireless-12/09 ATmega128RFA1 9.4.1.2.3 PLL_ON – PLL State Entering the PLL_ON state from TRX_OFF state first enab

370 8266A-MCU Wireless-12/09 ATmega128RFA1 UCPOLn UCPHAn SPI Mode Leading Edge Trailing Edge 1 1 3 Setup (Falling)

371 8266A-MCU Wireless-12/09 ATmega128RFA1 Assembly Code Example(1) USART_Init: clr r18 out UBRRnH,r18 out UBRRnL,r18 ; Setting t

372 8266A-MCU Wireless-12/09 ATmega128RFA1 UDRn is moved from the transmit buffer to the shift register when the shift register is

373 8266A-MCU Wireless-12/09 ATmega128RFA1 24.5.1 Transmitter and Receiver Flags and Interrupts The RXCn, TXCn, and UDREn flags and co

374 8266A-MCU Wireless-12/09 ATmega128RFA1 • Bit 5 – UDRE0 - USART Data Register Empty The UDRE0 Flag indicates if the transmit bu

375 8266A-MCU Wireless-12/09 ATmega128RFA1 When set to one the LSB of the data word is transmitted first. When set to ze

376 8266A-MCU Wireless-12/09 ATmega128RFA1 • Bit 6 – TXCIE1 - TX Complete Interrupt Enable Writing this bit to one enables interru

377 8266A-MCU Wireless-12/09 ATmega128RFA1 25 2-wire Serial Interface 25.1 Features • Simple yet powerful and flexible communication

378 8266A-MCU Wireless-12/09 ATmega128RFA1 The Power Reduction TWI bit, PRTWI bit in "PRR0 – Power Reduction Register0&quo

379 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 25-3. START, REPEATED START and STOP conditions SDASCLSTART STOPREPEATED STARTSTOP

38 8266A-MCU Wireless-12/09 ATmega128RFA1 During the transition to BUSY_TX state, the PLL frequency shifts to the trans

380 8266A-MCU Wireless-12/09 ATmega128RFA1 pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line

381 8266A-MCU Wireless-12/09 ATmega128RFA1 • An algorithm must be implemented allowing only one of the masters to complete the transm

382 8266A-MCU Wireless-12/09 ATmega128RFA1 must contain the same number of data packets, otherwise the result of the arbitration is

383 8266A-MCU Wireless-12/09 ATmega128RFA1 25.5.1 SCL and SDA Pins These pins interface the AVR TWI with the rest of the MCU system. T

384 8266A-MCU Wireless-12/09 ATmega128RFA1 compare addresses even if the AVR MCU is in sleep mode, enabling the MCU to wake up if a

385 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 25-10. Interfacing the Application to the TWI in a Typical Transmission START SLA+W

386 8266A-MCU Wireless-12/09 ATmega128RFA1 clears the flag. The TWI will not start any operation as long as the TWINT

387 8266A-MCU Wireless-12/09 ATmega128RFA1 Assembly Code Example C Example Comments 4 wait2: in r16,TWCR sbrs r16,TWINT rjmp w

388 8266A-MCU Wireless-12/09 ATmega128RFA1 details of the following serial transfer are given in Table 25-3 on page 390 to Table 25

389 8266A-MCU Wireless-12/09 ATmega128RFA1 TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE Value 1 X 0 0 X 1 0 X This sch

39 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 9-13. Timing of TRX24_RX_START, TRX24_XAH_AMI, TRX24_TX_END and TRX24_RX_END

390 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 25-3. Status codes for Master Transmitter Mode Application Software Response To T

391 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 25-13. Data Transfer in Master Receiver Mode Device 1MASTERRECEIVERDevice 2SLAVETRAN

392 8266A-MCU Wireless-12/09 ATmega128RFA1 START enables the Master to switch between Slaves, Master Transmitter mode an

393 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 25-14. Formats and States in the Master Receiver Mode S SLA R A DATA A$08$40 $50SLA

394 8266A-MCU Wireless-12/09 ATmega128RFA1 The upper 7 bits are the address to which the 2-wire Serial Interface will respond when

395 8266A-MCU Wireless-12/09 ATmega128RFA1 0x78 Arbitration lost in SLA+R/W as Master; General call address has been received; ACK h

396 8266A-MCU Wireless-12/09 ATmega128RFA1 0xA0 A STOP condition or repeated START condition has been received while still addres

397 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 25-17. Data Transfer in Slave Transmitter Mode Device 3Device nSDASCL...R1 R2

398 8266A-MCU Wireless-12/09 ATmega128RFA1 will then wake up from sleep and the TWI will hold the SCL clock will low

399 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 25-18. Formats and States in the Slave Transmitter Mode S SLA R A DATA A$A8 $B8A$B0

4 8266A-MCU Wireless-12/09 ATmega128RFA1 Spectrum Signal (DSSS) processing with spreading and despreading. The device is

40 8266A-MCU Wireless-12/09 ATmega128RFA1 During this wake-up procedure the calibration of the filter-tuning network (FTN

400 8266A-MCU Wireless-12/09 ATmega128RFA1 3. The reading must be performed. 4. The transfer must be finished. Note that data

401 8266A-MCU Wireless-12/09 ATmega128RFA1 will lose the arbitration. Losing masters will switch to not addressed Slave mode or wait

402 8266A-MCU Wireless-12/09 ATmega128RFA1 25.9.2 TWCR – TWI Control Register Bit 7 6 5 4 3 2 1 0 NA ($BC) TWINT TWEA

403 8266A-MCU Wireless-12/09 ATmega128RFA1 pins enabling the slew-rate limiters and spike filters. If this bit is written to zero, the

404 8266A-MCU Wireless-12/09 ATmega128RFA1 Register Bits Value Description returned. 0x58 Data byte has been received; NOT ACK h

405 8266A-MCU Wireless-12/09 ATmega128RFA1 Register Bits Value Description 0x01 4 0x02 16 0x03 64 25.9.4 TWDR – TWI Data Registe

406 8266A-MCU Wireless-12/09 ATmega128RFA1 25.9.6 TWAMR – TWI (Slave) Address Mask Register Bit 7 6 5 4 3 2 1 0 NA ($BD)

407 8266A-MCU Wireless-12/09 ATmega128RFA1 26 AC – Analog Comparator The Analog Comparator compares the input values on the p

408 8266A-MCU Wireless-12/09 ATmega128RFA1 ACME ADEN MUX5 MUX2:0 Analog Comparator Negative Input 1 0 0 101 ADC5 1 0 0 1

409 8266A-MCU Wireless-12/09 ATmega128RFA1 • Bit 1:0 – ACIS1:0 - Analog Comparator Interrupt Mode Select These bits determine whic

41 8266A-MCU Wireless-12/09 ATmega128RFA1 tTR10 = 16 µs after initiating the transmission, the radio transceiver changes into

410 8266A-MCU Wireless-12/09 ATmega128RFA1 27 ADC – Analog to Digital Converter 27.1 Features • 10-bit Resolution • Differential

411 8266A-MCU Wireless-12/09 ATmega128RFA1 The Power Reduction ADC bit, PRADC (see "PRR0 – Power Reduction Register0" on pag

412 8266A-MCU Wireless-12/09 ATmega128RFA1 cause instable operation of the internal reference voltage buffer and will no

413 8266A-MCU Wireless-12/09 ATmega128RFA1 27.4 Starting a Conversion A single conversion is started by writing a logical one to the A

414 8266A-MCU Wireless-12/09 ATmega128RFA1 frequency to the ADC can be as high as 8 MHz to get a higher sample rate

415 8266A-MCU Wireless-12/09 ATmega128RFA1 Parameter Duration in ADC Clock Cycles Gain Amplifier Initialization Time tAINIT 2(ADTHT+

416 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 27-3. Conversion Start Delay Channel ADPS Delay from Conversion Start Request to

417 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 27-8. ADC Timing Diagram, Free Running Conversion A D C C lockA D T S [2 :0]A D S C

418 8266A-MCU Wireless-12/09 ATmega128RFA1 the MUX4:0 bits need to be modified then a write access to the MUX4:0 bits

419 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 27-9. ADC Timing Diagram, Changing MUXn after a Conversion A D C C loc kA D IFA D C

42 8266A-MCU Wireless-12/09 ATmega128RFA1 9.4.1.4.5 State Transition Timing Summary The transition numbers correspond to Table

420 8266A-MCU Wireless-12/09 ATmega128RFA1 disabled and enabled again for new reference selections. For internal referenc

421 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 27-11. Analog Input Circuitry A D C nIILIIHCS /H = 1 4 p FVA V D D/22 k Signal comp

422 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 27-12. Offset Error Output CodeVREFInput VoltageIdeal ADCActual ADCOffsetError •

423 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 27-14. Integral Non-linearity (INL) Output CodeVREFInput VoltageIdeal ADCActual ADCI

424 8266A-MCU Wireless-12/09 ATmega128RFA1 For single ended conversion, the result is REFINVVADC1024⋅= where VIN is the voltage

425 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 27-7. Correlation Between Input Voltage and Output Codes VADCn Read Code Correspond

426 8266A-MCU Wireless-12/09 ATmega128RFA1 8.27213.1/−⋅=°TEMPADCCθ Note that the above equations are only valid in the al

427 8266A-MCU Wireless-12/09 ATmega128RFA1 Parameter Register Recommended Setup ADCSRB MUX5 = 1; ADC Clock ADCSRA Select a clock

428 8266A-MCU Wireless-12/09 ATmega128RFA1 ADCSRA is set). Note that the MUX5 bit is located in the ADCSRB register. A write access

429 8266A-MCU Wireless-12/09 ATmega128RFA1 MUX5:0 Single Ended Input Positive Differential Input Negative Differential Input Gain 000

43 8266A-MCU Wireless-12/09 ATmega128RFA1 No Symbol Block Time [µs], (typ) Time [µs], (max) Comments 24 tTR24 PLL, TX  RX 32 Ma

430 8266A-MCU Wireless-12/09 ATmega128RFA1 MUX5:0 Single Ended Input Positive Differential Input Negative Differential Input Gain

431 8266A-MCU Wireless-12/09 ATmega128RFA1 • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. The AVDD supply voltag

432 8266A-MCU Wireless-12/09 ATmega128RFA1 This register defines the track-and-hold time for sampling the analog input v

433 8266A-MCU Wireless-12/09 ATmega128RFA1 • ADC9:0: A/D Conversion Result These bits represent the result from the conversion

434 8266A-MCU Wireless-12/09 ATmega128RFA1 • Bit 6:3 – BGCAL_FINE3:0 - Fine Calibration Bits These bits allow the calibration of t

435 8266A-MCU Wireless-12/09 ATmega128RFA1 28 JTAG Interface and On-chip Debug System 28.1 Features • JTAG (IEEE std. 1149.1 Complian

436 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 28-1. Block Diagram TAPCONTROLLERTDITDOTCKTMSFLASHMEMORYAVR CPUDIGITALPERIPHERALU

437 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 28-2. TAP Controller State Diagram Test-Logic-ResetRun-Test/IdleShift-DRExit1-DRPaus

438 8266A-MCU Wireless-12/09 ATmega128RFA1 selects a particular Data Register as path between TDI and TDO and controls the ci

439 8266A-MCU Wireless-12/09 ATmega128RFA1 • 2 single program memory breakpoints + 1 program memory breakpoint with mask (“

44 8266A-MCU Wireless-12/09 ATmega128RFA1 frame pending subfield in the received acknowledgement frame the transaction status is se

440 8266A-MCU Wireless-12/09 ATmega128RFA1 The JTAG programming capability supports: • Flash programming and verifying. • EEPROM

441 8266A-MCU Wireless-12/09 ATmega128RFA1 29 IEEE 1149.1 (JTAG) Boundary-scan 29.1 Features • JTAG (IEEE std. 1149.1 compliant) Inte

442 8266A-MCU Wireless-12/09 ATmega128RFA1 • Reset Register • Boundary-scan Chain 29.3.1 Bypass Register The Bypass Register c

443 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 29-2. Reset Register D QFromTDIClockDR · AVR_RESETTo TDOFrom Other Internal andEx

444 8266A-MCU Wireless-12/09 ATmega128RFA1 The active states are: • Capture-DR: Data in the IDCODE Register is sampled int

445 8266A-MCU Wireless-12/09 ATmega128RFA1 When no alternate port function is present, the Input Data - ID - corresponds

446 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 29-4. General Port Pin Schematic Diagram CLKRPxRRxWRxRDxWDxPUDSYNCHRONIZERWDx: WR

447 8266A-MCU Wireless-12/09 ATmega128RFA1 29.5.3 Scanning the RSTON Pin For the low-active reset output pin RSTON a boundary-scan cel

448 8266A-MCU Wireless-12/09 ATmega128RFA1 • Bit 4 – JTRF - JTAG Reset Flag This bit is set if a reset is being caused b

449 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 29-1. ATmega128RFA1 Boundary-Scan Order Bit Number Signal Name Module Bit Number

45 8266A-MCU Wireless-12/09 ATmega128RFA1 9.4.2.1 State Control The Extended Operating Mode states RX_AACK and TX_ARET are controlled

450 8266A-MCU Wireless-12/09 ATmega128RFA1 30 Boot Loader Support – Read-While-Write Self-Programming The Boot Loader Support p

451 8266A-MCU Wireless-12/09 ATmega128RFA1 30.3 Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports R

452 8266A-MCU Wireless-12/09 ATmega128RFA1 programming is completed, the RWWSB must be cleared by software before reading co

453 8266A-MCU Wireless-12/09 ATmega128RFA1 30.4 Boot Loader Lock Bits If no Boot Loader capability is needed, the entire Flash is avai

454 8266A-MCU Wireless-12/09 ATmega128RFA1 Since the Flash is organized in pages (see "Table 31-7" on page 46

455 8266A-MCU Wireless-12/09 ATmega128RFA1 • Fill temporary page buffer, • Perform a Page Write; If only a part of the page needs to

456 8266A-MCU Wireless-12/09 ATmega128RFA1 30.6.5 Consideration While Updating BLS Special care must be taken if the user allows th

457 8266A-MCU Wireless-12/09 ATmega128RFA1 Bit 7 6 5 4 3 2 1 0 Rd - - BLB12 BLB11 BLB02 BLB01 LB2 LB1 The algorith

458 8266A-MCU Wireless-12/09 ATmega128RFA1 30.6.11 Preventing Flash Corruption During periods of VDEVDD<1.8V, the Flash program

459 8266A-MCU Wireless-12/09 ATmega128RFA1 Assembly Code Example(1) .equ PAGESIZEB=PAGESIZE*2 ;PAGESIZEB is page in BYTES, not words .

46 8266A-MCU Wireless-12/09 ATmega128RFA1 o Handling of Pending Data Indicator o Characterize as PAN coordinator o Handling of S

460 8266A-MCU Wireless-12/09 ATmega128RFA1 Assembly Code Example(1) ; If RWWSB is set, the RWW section is not ready yet sbrs te

461 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 30-6. Explanation of different variables used in Figure 30-3 on page 454 and the mapp

462 8266A-MCU Wireless-12/09 ATmega128RFA1 30.7 Register Description 30.7.1 SPMCSR – Store Program Memory Control Register Bit 7

463 8266A-MCU Wireless-12/09 ATmega128RFA1 instruction is executed within four clock cycles. The CPU is halted during the

464 8266A-MCU Wireless-12/09 ATmega128RFA1 31 Memory Programming 31.1 Program And Data Memory Lock Bits The ATmega128RFA1 provides

465 8266A-MCU Wireless-12/09 ATmega128RFA1 Memory Lock Bits Protection Type BLB1 Mode BL12 BL11 1 1 1 No restrictions for SPM o

466 8266A-MCU Wireless-12/09 ATmega128RFA1 Fuse High Byte Bit No Description Default Value EESAVE 3 EEPROM memory is preserved

467 8266A-MCU Wireless-12/09 ATmega128RFA1 The three bytes reside in a separate address space. For the ATmega128RFA1 the s

468 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 31-1. Parallel Programming (1) Note: 1. Unused Pins should be left floating.

469 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 31-11. Pin Values Used to Enter Programming Mode Pin Symbol Value PAGEL Prog_enabl

47 8266A-MCU Wireless-12/09 ATmega128RFA1 Generally, at nodes, configured as a normal device or PAN coordinator, a frame is not indica

470 8266A-MCU Wireless-12/09 ATmega128RFA1 31.7.2 Considerations for Efficient Programming The loaded command and address are retai

471 8266A-MCU Wireless-12/09 ATmega128RFA1 C. Load Data Low Byte 1. Set XA1, XA0 to “01”. This enables data loading. 2. Set DATA = D

472 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 31-5. Addressing the Flash which is Organized in Pages (1) PROGRAM MEMORYWORD ADD

473 8266A-MCU Wireless-12/09 ATmega128RFA1 K: Repeat 3 through 5 until the entire buffer is filled. L: Program EEPROM page 1. Set BS2

474 8266A-MCU Wireless-12/09 ATmega128RFA1 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3.

475 8266A-MCU Wireless-12/09 ATmega128RFA1 31.7.12 Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is

476 8266A-MCU Wireless-12/09 ATmega128RFA1 31.7.15 Parallel Programming Characteristics Figure 31-10. Parallel programming timing i

477 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 31-14. Parallel Programming Characteristics, VDEVDD = 3.3V ± 10% Symbol Parameter M

478 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 31-13. Serial Programming and Verify (1)(2) Notes: 1. If the device is clo

479 8266A-MCU Wireless-12/09 ATmega128RFA1 not, all four bytes of the instruction must be transmitted. If the 0x53 did n

48 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 9-19. Flow Diagram of RX_AACK Reserved FramesTRX_STATE = RX_AACK_ONSHR detectedTRX

480 8266A-MCU Wireless-12/09 ATmega128RFA1 Instruction Format (1) Read Fuse Bits $50 $00 $00 data byte out Read Fuse High Bits

481 8266A-MCU Wireless-12/09 ATmega128RFA1 31.8.4 Serial Programming Characteristics For characteristics of the Serial Programming mod

482 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 31-16. State Machine Sequence for Changing the Instruction Word Test-Logic-ResetR

483 8266A-MCU Wireless-12/09 ATmega128RFA1 • Update-DR: The programming enable signature is compared to the correct value,

484 8266A-MCU Wireless-12/09 ATmega128RFA1 • Programming Enable Register • Programming Command Register • Flash Data Byte Regist

485 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 31-18. Programming Command Register TDITDOSTROBESADDRESS/DATAFlash

486 8266A-MCU Wireless-12/09 ATmega128RFA1 Instruction TDI Sequence TDO Sequence Notes 4a. Enter EEPROM Write 0100011_00010001

487 8266A-MCU Wireless-12/09 ATmega128RFA1 Instruction TDI Sequence TDO Sequence Notes 8a. Enter Fuse/Lock Bit Read 0100011_000001

488 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 31-19. State Machine Sequence for Changing/Reading the Data Word Test-Logic-Reset

489 8266A-MCU Wireless-12/09 ATmega128RFA1 During Page Read, the content of the selected Flash byte is captured into the

49 8266A-MCU Wireless-12/09 ATmega128RFA1 9.4.2.3.1 Description of RX_AACK Configuration Bits Overview The following table summariz

490 8266A-MCU Wireless-12/09 ATmega128RFA1 31.9.15 Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start Chip E

491 8266A-MCU Wireless-12/09 ATmega128RFA1 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instructi

492 8266A-MCU Wireless-12/09 ATmega128RFA1 5. Poll for Fuse write complete using programming instruction 6d, or wait fo

493 8266A-MCU Wireless-12/09 ATmega128RFA1 32 Application Circuits 32.1 Basic Application Schematic A basic application schematic

494 8266A-MCU Wireless-12/09 ATmega128RFA1 The crystal (XTAL), the two load capacitors (CX1, CX2), and the internal cir

495 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 32-2. Extended Feature Application schematic 8765432117 18 19 20 21 22 23 2456575859

496 8266A-MCU Wireless-12/09 ATmega128RFA1 33 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

497 8266A-MCU Wireless-12/09 ATmega128RFA1 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x144) TRX_CTR

498 8266A-MCU Wireless-12/09 ATmega128RFA1 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xDE) SCSR

499 8266A-MCU Wireless-12/09 ATmega128RFA1 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x92) TCCR3C

5 8266A-MCU Wireless-12/09 ATmega128RFA1 trough an SPI serial interface, by a conventional nonvolatile memory programmer, or by on on

50 8266A-MCU Wireless-12/09 ATmega128RFA1 9.4.2.3.2 Configuration of IEEE Scenarios Normal Device The Table 9-6 below shows a

500 8266A-MCU Wireless-12/09 ATmega128RFA1 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page ... Reserved

501 8266A-MCU Wireless-12/09 ATmega128RFA1 34 Electrical Characteristics 34.1 Absolute Maximum Ratings Note that stresses beyond thos

502 8266A-MCU Wireless-12/09 ATmega128RFA1 34.2 Clock Characteristics 34.2.1 Calibrated Internal RC Oscillator Accuracy Table 34-2.

503 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 34-23. BODLEVEL Fuse Coding BODLEVEL2:0 Fuses Min VBOD Typ VBOD Max VBOD Units 1

504 8266A-MCU Wireless-12/09 ATmega128RFA1 Symbol Parameter Condition Min. Max. Units VIH Input High-voltage 0.7VDEVDD VD

505 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 34-3. SPI timing Requirements (Master Mode) MOSI(Data Output)SCK(CPOL = 1)MISO(Data

506 8266A-MCU Wireless-12/09 ATmega128RFA1 Symbol Parameter Condition Min(1) Typ(1) Max(1) Units VREF = 1.6V CLKADC = 200kHz

507 8266A-MCU Wireless-12/09 ATmega128RFA1 Symbol Parameter Condition Min(1) Typ(1) Max(1) Units Gain = 10x VREF = 1.6V CLKAD

508 8266A-MCU Wireless-12/09 ATmega128RFA1 Symbol Parameter Condition Min. Typ. Max. Units fPSDU PSDU bit rate As specified

509 8266A-MCU Wireless-12/09 ATmega128RFA1 Symbol Parameter Condition Min. Typ. Max. Units Receiver sensitivity 250 kb/s

51 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 9-7. Configuration of a PAN Coordinator Register Name Register Bits Description SHOR

510 8266A-MCU Wireless-12/09 ATmega128RFA1 Symbol Parameter Condition Min. Typ. Max. Units IBUSY_TX Supply current transmit

511 8266A-MCU Wireless-12/09 ATmega128RFA1 36 Ordering Information ATmega128RFA1 Speed (MHz) Power Supply Ordering Code Package Pa

512 8266A-MCU Wireless-12/09 ATmega128RFA1 37 Packaging Information PI ALL DIMENSIONS ARE IN MILLIMETERS.PACKAGE WARPAGE MAX 0.08

513 8266A-MCU Wireless-12/09 ATmega128RFA1 38 Errata 38.1 ATmega128RFA1 revision D (1.2) • Power-Chain turns off when power supply dr

514 8266A-MCU Wireless-12/09 ATmega128RFA1 38.5.2 JTAG interface reads wrong data If the Power Reduction Register bits associ

515 8266A-MCU Wireless-12/09 ATmega128RFA1 Problem Fix/Workaround Set ENDRT=1 in DRTRAM3…0 at the beginning of the firmware program.

516 8266A-MCU Wireless-12/09 ATmega128RFA1 39 Revision history Please note that the referring page numbers in this sectio

517 8266A-MCU Wireless-12/09 ATmega128RFA1 Table of Contents 1 Pin Configurations...

518 8266A-MCU Wireless-12/09 ATmega128RFA1 9.9 Continuous Transmission Test Mode...

519 8266A-MCU Wireless-12/09 ATmega128RFA1 13.1 Resetting the AVR...

52 8266A-MCU Wireless-12/09 ATmega128RFA1 Register Name Register Bits Description AACK_FVN_MODE 7:6 Controls the ACK behavior,

520 8266A-MCU Wireless-12/09 ATmega128RFA1 18.8 Compare Match Output Unit...

521 8266A-MCU Wireless-12/09 ATmega128RFA1 23.6 Data Transmission – The USART Transmitter...

522 8266A-MCU Wireless-12/09 ATmega128RFA1 27.10 SRAM DRT Voltage Measurement ...

523 8266A-MCU Wireless-12/09 ATmega128RFA1 31.6 Parallel Programming Parameters, Pin Mapping, and Commands ... 467 31.7

524 8266A-MCU Wireless-12/09 ATmega128RFA1 Disclaimer Headquarters International Atmel Corporation 2325 Orchard Parkway S

53 8266A-MCU Wireless-12/09 ATmega128RFA1 Reception of Reserved Frames Frames with reserved frame types (see section Table 9-1

54 8266A-MCU Wireless-12/09 ATmega128RFA1 If AACK_FLT_RES_FT = 1 any frame with a reserved frame type is filtered by the address fi

55 8266A-MCU Wireless-12/09 ATmega128RFA1 2. At least one address field must be configured. Address match, indicated by the TRX2

56 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 9-10. Example Timing of an RX_AACK Transaction for Slotted Operation RX/TXFrame on

57 8266A-MCU Wireless-12/09 ATmega128RFA1 9.4.2.5 TX_ARET_ON – Transmit with Automatic Retry and CSMA-CA Retry Figure 9-12. Flow Diagr

58 8266A-MCU Wireless-12/09 ATmega128RFA1 Overview The implemented TX_ARET algorithm is shown in Figure 9-12 on page 57. In TX_ARE

59 8266A-MCU Wireless-12/09 ATmega128RFA1 Value Name Description 5 NO_ACK No acknowledgement frames were received during all retr

6 8266A-MCU Wireless-12/09 ATmega128RFA1 3.2.10 Port F (PF7...PF0) Port F is an 8-bit bi-directional I/O port with internal pull-up

60 8266A-MCU Wireless-12/09 ATmega128RFA1 Table 9-13. Interrupt Handling in Extended Operating Mode Mode Interrupt Description TR

61 8266A-MCU Wireless-12/09 ATmega128RFA1 Register Name Description IEEE_ADDR7 …. IEEE_ADDR0 PAN_ID1 PAN_ID0 SHORT_ADDR1 SHORT_ADDR0

62 8266A-MCU Wireless-12/09 ATmega128RFA1 On receive the PHR is returned as the first octet during Frame Buffer read

63 8266A-MCU Wireless-12/09 ATmega128RFA1 9.5.1.2.2 Frame Control Field (FCF) The FCF consists of 16 bits, and occupies the first two

64 8266A-MCU Wireless-12/09 ATmega128RFA1 Bit 6: the “Intra-PAN” subfield indicates that in a frame, where both, the destination an

65 8266A-MCU Wireless-12/09 ATmega128RFA1 9.5.1.2.3 Frame Compatibility between IEEE 802.15.4-2003 and IEEE 802.15.4-2006 All unsecure

66 8266A-MCU Wireless-12/09 ATmega128RFA1 subfield b3 is set to one (see section "Frame Compatibility between IEEE 8

67 8266A-MCU Wireless-12/09 ATmega128RFA1 Example: Consider a 5 octet ACK frame. The MHR field consists of 0100 0000 0000 0000 0101 0

68 8266A-MCU Wireless-12/09 ATmega128RFA1 received signal strength is evaluated. The RSSI provides the basis for an ED

69 8266A-MCU Wireless-12/09 ATmega128RFA1 For High Data Rate Modes the automated ED measurement duration is reduced to 32

7 8266A-MCU Wireless-12/09 ATmega128RFA1 registers are unchanged as long as it fits the target application of a very sma

70 8266A-MCU Wireless-12/09 ATmega128RFA1 PRF = -90 + ED [dBm] Figure 9-18. Mapping between values in PHY_ED_LEVEL and Received I

71 8266A-MCU Wireless-12/09 ATmega128RFA1 CCA Mode Description 0, 3 Carrier sense with energy above threshold. CCA shall report a b

72 8266A-MCU Wireless-12/09 ATmega128RFA1 9.5.5.5 Measurement Time The response time for a manually initiated CCA measurement depen

73 8266A-MCU Wireless-12/09 ATmega128RFA1 can be associated with an expected packet error rate. The PER is the ratio of erroneous rece

74 8266A-MCU Wireless-12/09 ATmega128RFA1 Note that the received signal power as indicated by the received signal stren

75 8266A-MCU Wireless-12/09 ATmega128RFA1 converter (RX ADC) and generates a digital RSSI signal. The ADC output signal i

76 8266A-MCU Wireless-12/09 ATmega128RFA1 9.6.2 Transmitter (TX) 9.6.2.1 Overview The transmitter consists of a digital base band p

77 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 9-22. TX Power Ramping 0 6 8 10SLPTRTR X _STA TE PLL_ON2 12 14 16 18Length [µ s]PA b

78 8266A-MCU Wireless-12/09 ATmega128RFA1 Alternatively Dynamic Frame Buffer Protection can be used to protect received frames agai

79 8266A-MCU Wireless-12/09 ATmega128RFA1 The PHR and the PSDU need to be stored in the Frame Buffer for frame transmission. The PHR

8 8266A-MCU Wireless-12/09 ATmega128RFA1 • over 10 years at 85°C • TBD years at 25°C.

80 8266A-MCU Wireless-12/09 ATmega128RFA1 The value BATMON_OK should be read out to verify the current supply voltage value after s

81 8266A-MCU Wireless-12/09 ATmega128RFA1 The following figure shows all parasitic capacitances, such as PCB stray capacitances and th

82 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 9-26. Setup for Using an External Frequency Reference XTAL2XTAL1IC internalPCB16 M

83 8266A-MCU Wireless-12/09 ATmega128RFA1 9.6.6.4 Calibration Loops Due to temperature, supply voltage and part-to-part variations of

84 8266A-MCU Wireless-12/09 ATmega128RFA1 9.7.1 Frame Receive Procedure A frame reception comprises of two actions: The PHY listens

85 8266A-MCU Wireless-12/09 ATmega128RFA1 command TX_START to register TRX_STATE after a Frame Buffer write access and while

86 8266A-MCU Wireless-12/09 ATmega128RFA1 • Generate random values for AES key generation (see "Security Module (AES)&

87 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 9-30. High Data Rate Frame Structure 250 kb/s0 time [µs]192SFDPHR832 1472 2752500 kb/

88 8266A-MCU Wireless-12/09 ATmega128RFA1 9.8.2.5 High Data Rate Mode Options Receiver Sensitivity Control The different data ra

89 8266A-MCU Wireless-12/09 ATmega128RFA1 Antenna Diversity uses two antennas to switch to the most reliable RF signal path. This is d

9 8266A-MCU Wireless-12/09 ATmega128RFA1 7 AVR CPU Core 7.1 Introduction This section discusses the AVR core architecture in general.

90 8266A-MCU Wireless-12/09 ATmega128RFA1 If the radio transceiver is not in a receive or transmit state, it is recommended to disa

91 8266A-MCU Wireless-12/09 ATmega128RFA1 Figure 9-34. TX Power Ramping Control for RF Front-Ends 0 6 8 10TRX_STA TESLPTRPLL_O N2 12 1

92 8266A-MCU Wireless-12/09 ATmega128RFA1 Protection prevents that a new valid frame passes to the Frame Buffer until the buffer pr

93 8266A-MCU Wireless-12/09 ATmega128RFA1 Step Description Description 2 AES configuration Select AES mode: ECB or CBC Select encr

94 8266A-MCU Wireless-12/09 ATmega128RFA1 A 16-folded read access to registers AES_KEY returns the last round key of t

95 8266A-MCU Wireless-12/09 ATmega128RFA1 key is the content of the key address space stored after running one full encr

96 8266A-MCU Wireless-12/09 ATmega128RFA1 The status of the security processing is indicated by register AES_STATUS. Aft

97 8266A-MCU Wireless-12/09 ATmega128RFA1 The transmission is started by enabling the PLL (TRX_CMD = PLL_ON) and writing the TX_START

98 8266A-MCU Wireless-12/09 ATmega128RFA1 To measure CW signals it is necessary to write either 0x00 or 0xFF to the

99 8266A-MCU Wireless-12/09 ATmega128RFA1 ISM - Industrial, scientific, and medical LDO - Low-drop output LNA - Low-noise