Rainbow-electronics ATmega32L User Manual

1Features• High-performance, Low-power AVR® 8-bit Microcontroller• Advanced RISC Architecture– 131 Powerful Instructions – Most Single-clock Cycle Exe

10ATmega32(L) 2503C–AVR–10/02The X-register, Y-register and Z-registerThe registers R26..R31 have some added functions to their general purpose usage.

100ATmega32(L) 2503C–AVR–10/02Figure 47. Phase Correct PWM Mode, Timing DiagramThe Timer/Counter Overflow Flag (TOV1) is set each time the counter re

101ATmega32(L)2503C–AVR–10/02for the output when using phase correct PWM can be calculated by the followingequation:The N variable represents the pres

102ATmega32(L) 2503C–AVR–10/02Figure 48. Phase and Frequency Correct PWM Mode, Timing DiagramThe Timer/Counter Overflow Flag (TOV1) is set at the sam

103ATmega32(L)2503C–AVR–10/02The extreme values for the OCR1x Register represents special cases when generatinga PWM waveform output in the phase corr

104ATmega32(L) 2503C–AVR–10/02Figure 51 shows the count sequence close to TOP in various modes. When using phaseand frequency correct PWM mode the OCR

105ATmega32(L)2503C–AVR–10/0216-bit Timer/Counter Register DescriptionTimer/Counter1 Control Register A – TCCR1A• Bit 7:6 – COM1A1:0: Compare Output M

106ATmega32(L) 2503C–AVR–10/02Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 isset. In this case the compare match is ig

107ATmega32(L)2503C–AVR–10/02A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in ClearTimer on Compare match (CTC) mod

108ATmega32(L) 2503C–AVR–10/02Timer/Counter1 Control Register B – TCCR1B• Bit 7 – ICNC1: Input Capture Noise CancelerSetting this bit (to one) activat

109ATmega32(L)2503C–AVR–10/02If external pin modes are used for the Timer/Counter1, transitions on the T1 pin willclock the counter even if the pin is

11ATmega32(L)2503C–AVR–10/02Instruction Execution TimingThis section describes the general access timing concepts for instruction execution. TheAVR CP

110ATmega32(L) 2503C–AVR–10/02Input Capture Register 1 – ICR1H and ICR1LThe Input Capture is updated with the counter (TCNT1) value each time an event

111ATmega32(L)2503C–AVR–10/02Timer/Counter Interrupt Flag Register – TIFRNote: This register contains flag bits for several Timer/Counters, but only T

112ATmega32(L) 2503C–AVR–10/028-bit Timer/Counter2 with PWM and Asynchronous OperationTimer/Counter2 is a general purpose, single channel, 8-bit Timer

113ATmega32(L)2503C–AVR–10/02The double buffered Output Compare Register (OCR2) is compared with theTimer/Counter value at all times. The result of th

114ATmega32(L) 2503C–AVR–10/02top Signalizes that TCNT2 has reached maximum value.bottom Signalizes that TCNT2 has reached minimum value (zero).Depend

115ATmega32(L)2503C–AVR–10/02The OCR2 Register is double buffered when using any of the Pulse Width Modulation(PWM) modes. For the normal and Clear Ti

116ATmega32(L) 2503C–AVR–10/02Figure 56. Compare Match Output Unit, SchematicThe general I/O port function is overridden by the Output Compare (OC2)

117ATmega32(L)2503C–AVR–10/02Normal Mode The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode thecounting direction is always

118ATmega32(L) 2503C–AVR–10/02quency of fOC2 = fclk_I/O/2 when OCR2 is set to zero (0x00). The waveform frequency isdefined by the following equation:

119ATmega32(L)2503C–AVR–10/02pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2register at the compare match between

12ATmega32(L) 2503C–AVR–10/02– the External Interrupt Request 0. The Interrupt Vectors can be moved to the start ofthe Boot Flash section by setting t

120ATmega32(L) 2503C–AVR–10/02Figure 59. Phase Correct PWM Mode, Timing DiagramThe Timer/Counter Overflow Flag (TOV2) is set each time the counter re

121ATmega32(L)2503C–AVR–10/02Figure 60. Timer/Counter Timing Diagram, no PrescalingFigure 61 shows the same timing data, but with the prescaler enabl

122ATmega32(L) 2503C–AVR–10/02Figure 63 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode.Figure 63. Timer/Counter Timing Diagram, Clea

123ATmega32(L)2503C–AVR–10/02Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 def-initions. However, the functionalit

124ATmega32(L) 2503C–AVR–10/02.Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, thecompare match is ignored, but th

125ATmega32(L)2503C–AVR–10/02Output Compare Register – OCR2The Output Compare Register contains an 8-bit value that is continuously comparedwith the c

126ATmega32(L) 2503C–AVR–10/02Asynchronous Operation of Timer/Counter2When Timer/Counter2 operates asynchronously, some considerations must be taken.•

127ATmega32(L)2503C–AVR–10/02from Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or

128ATmega32(L) 2503C–AVR–10/02Timer/Counter Interrupt Flag Register – TIFR• Bit 7 – OCF2: Output Compare Flag 2The OCF2 bit is set (one) when a compar

129ATmega32(L)2503C–AVR–10/02For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64,clkT2S/128, clkT2S/256, and clk

13ATmega32(L)2503C–AVR–10/02When using the SEI instruction to enable interrupts, the instruction following SEI will beexecuted before any pending inte

130ATmega32(L) 2503C–AVR–10/02Serial Peripheral Interface – SPIThe Serial Peripheral Interface (SPI) allows high-speed synchronous data transferbetwee

131ATmega32(L)2503C–AVR–10/02When configured as a Master, the SPI interface has no automatic control of the SS line.This must be handled by user softw

132ATmega32(L) 2503C–AVR–10/02The following code examples show how to initialize the SPI as a master and how to per-form a simple transmission. DDR_SP

133ATmega32(L)2503C–AVR–10/02The following code examples show how to initialize the SPI as a Slave and how to per-form a simple reception.Note: 1. The

134ATmega32(L) 2503C–AVR–10/02SS Pin FunctionalitySlave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. WhenSS

135ATmega32(L)2503C–AVR–10/02• Bit 4 – MSTR: Master/Slave SelectThis bit selects Master SPI mode when written to one, and Slave SPI mode when writtenl

136ATmega32(L) 2503C–AVR–10/02SPI Status Register – SPSR• Bit 7 – SPIF: SPI Interrupt FlagWhen a serial transfer is complete, the SPIF flag is set. An

137ATmega32(L)2503C–AVR–10/02Data Modes There are four combinations of SCK phase and polarity with respect to serial data,which are determined by cont

138ATmega32(L) 2503C–AVR–10/02USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter(USART) is a highly flexible serial comm

139ATmega32(L)2503C–AVR–10/02The dashed boxes in the block diagram separate the three main parts of the USART(listed from the top): Clock Generator, T

14ATmega32(L) 2503C–AVR–10/02AVR ATmega32 MemoriesThis section describes the different memories in the ATmega32. The AVR architecturehas two main memo

140ATmega32(L) 2503C–AVR–10/02Figure 70. Clock Generation Logic, Block DiagramSignal description:txclk Transmitter clock (Internal Signal).rxclk Rece

141ATmega32(L)2503C–AVR–10/02Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps).BAUD Baud rate (in bits per second, bps

142ATmega32(L) 2503C–AVR–10/02Figure 71. Synchronous Mode XCK Timing.The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling andwh

143ATmega32(L)2503C–AVR–10/02The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame.The USART Parity mode (UPM1:0) bits e

144ATmega32(L) 2503C–AVR–10/02USART Initialization The USART has to be initialized before any communication can take place. The initial-ization proces

145ATmega32(L)2503C–AVR–10/02Data Transmission – The USART TransmitterThe USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in th

146ATmega32(L) 2503C–AVR–10/02Sending Frames with 9 Data BitIf 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit inU

147ATmega32(L)2503C–AVR–10/02either write new data to UDR in order to clear UDRE or disable the Data Register emptyInterrupt, otherwise a new interrup

148ATmega32(L) 2503C–AVR–10/02Data Reception – The USART ReceiverThe USART Receiver is enabled by writing the Receive Enable (RXEN) bit in theUCSRB Re

149ATmega32(L)2503C–AVR–10/02Receiving Frames with 9 DatabitsIf 9 bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit inUCSR

15ATmega32(L)2503C–AVR–10/02SRAM Data Memory Figure 9 shows how the ATmega32 SRAM Memory is organized.The lower 2144 Data Memory locations address the

150ATmega32(L) 2503C–AVR–10/02The receive function example reads all the I/O registers into the register file before anycomputation is done. This give

151ATmega32(L)2503C–AVR–10/02The PE bit is set if the next character that can be read from the receive buffer had a par-ity error when received and th

152ATmega32(L) 2503C–AVR–10/02Figure 73. Start Bit SamplingWhen the clock recovery logic detects a high (idle) to low (start) transition on the RxDli

153ATmega32(L)2503C–AVR–10/02Figure 75. Stop Bit Sampling and Next Start Bit SamplingThe same majority voting is done to the stop bit as done for the

154ATmega32(L) 2503C–AVR–10/02Table 61 and Table 62 list the maximum receiver baud rate error that can be tolerated.Note that Normal Speed mode has hi

155ATmega32(L)2503C–AVR–10/02Multi-processor Communication ModeSetting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a fil-tering

156ATmega32(L) 2503C–AVR–10/02Accessing UBRRH/ UCSRC RegistersThe UBRRH Register shares the same I/O location as the UCSRC Register. Thereforesome spe

157ATmega32(L)2503C–AVR–10/02Read Access Doing a read access to the UBRRH or the UCSRC Register is a more complex opera-tion. However, in most applica

158ATmega32(L) 2503C–AVR–10/02The transmit buffer can only be written when the UDRE flag in the UCSRA Register isset. Data written to UDR when the UDR

159ATmega32(L)2503C–AVR–10/02• Bit 2 – PE: Parity ErrorThis bit is set if the next character in the receive buffer had a Parity Error when receivedand

16ATmega32(L) 2503C–AVR–10/02Data Memory Access Times This section describes the general access timing concepts for internal memory access.The interna

160ATmega32(L) 2503C–AVR–10/02do not contain data to be transmitted. When disabled, the transmitter will no longer over-ride the TxD port.• Bit 2 – UC

161ATmega32(L)2503C–AVR–10/02• Bit 5:4 – UPM1:0: Parity ModeThese bits enable and set type of parity generation and check. If enabled, the transmit-te

162ATmega32(L) 2503C–AVR–10/02• Bit 0 – UCPOL: Clock PolarityThis bit is used for Synchronous mode only. Write this bit to zero when Asynchronousmode

163ATmega32(L)2503C–AVR–10/02Examples of Baud Rate SettingFor standard crystal and resonator frequencies, the most commonly used baud rates forasynchr

164ATmega32(L) 2503C–AVR–10/02Table 69. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)Baud Rate (bps)fosc = 3.6864 MH

165ATmega32(L)2503C–AVR–10/02Table 70. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)Baud Rate (bps)fosc = 8.0000 MHz

166ATmega32(L) 2503C–AVR–10/02Table 71. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)Baud Rate (bps)fosc = 16.0000 M

167ATmega32(L)2503C–AVR–10/02Two-wire Serial InterfaceFeatures • Simple Yet Powerful and Flexible Communication Interface, Only Two Bus Lines Needed•

168ATmega32(L) 2503C–AVR–10/02Electrical Interconnection As depicted in Figure 76, both bus lines are connected to the positive supply voltagethrough

169ATmega32(L)2503C–AVR–10/02Figure 78. START, REPEATED START, and STOP ConditionsAddress Packet Format All address packets transmitted on the TWI bu

17ATmega32(L)2503C–AVR–10/02The EEPROM Address Register – EEARH and EEARL• Bits 15..10 – Res: Reserved BitsThese bits are reserved bits in the ATmega3

170ATmega32(L) 2503C–AVR–10/02any more bytes, it should inform the transmitter by sending a NACK after the final byte.The MSB of the data byte is tran

171ATmega32(L)2503C–AVR–10/02• Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial clocks from all

172ATmega32(L) 2503C–AVR–10/02Figure 83. Arbitration between Two MastersNote that arbitration is not allowed between:• A REPEATED START condition and

173ATmega32(L)2503C–AVR–10/02Overview of the TWI ModuleThe TWI module is comprised of several submodules, as shown in Figure 84. All regis-ters drawn

174ATmega32(L) 2503C–AVR–10/02Bus Interface Unit This unit contains the Data and Address Shift Register (TWDR), a START/STOP Con-troller and Arbitrati

175ATmega32(L)2503C–AVR–10/02TWI register descriptionTWI Bit Rate Register – TWBR• Bits 7..0 – TWI Bit Rate RegisterTWBR selects the division factor f

176ATmega32(L) 2503C–AVR–10/02until a STOP condition is detected, and then generates a new START condition to claimthe bus Master status. TWSTA must b

177ATmega32(L)2503C–AVR–10/02• Bits 1..0 – TWPS: TWI Prescaler BitsThese bits can be read and written, and control the bit rate prescaler. To calculat

178ATmega32(L) 2503C–AVR–10/02• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call give

179ATmega32(L)2503C–AVR–10/023. The application software should now examine the value of TWSR, to make sure that the START condition was successfully

18ATmega32(L) 2503C–AVR–10/02When EEMWE has been written to one by software, hardware clears the bit to zero afterfour clock cycles. See the descripti

180ATmega32(L) 2503C–AVR–10/02set. Writing a one to TWINT clears the flag. The TWI will then commence executing whatever operation was specified by th

181ATmega32(L)2503C–AVR–10/02Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter(MT), Master Receive

182ATmega32(L) 2503C–AVR–10/02Figure 86. Data Transfer in Master Transmitter ModeA START condition is sent by writing the following value to TWCR:TWE

183ATmega32(L)2503C–AVR–10/02After a repeated START condition (state $10) the Two-wire Serial Interface can accessthe same slave again, or a new slave

184ATmega32(L) 2503C–AVR–10/02Figure 87. Formats and States in the Master Transmitter ModeMaster Receiver Mode In the Master Receiver mode, a number

185ATmega32(L)2503C–AVR–10/02Figure 88. Data Transfer in Master Receiver ModeA START condition is sent by writing the following value to TWCR:TWEN mu

186ATmega32(L) 2503C–AVR–10/02Table 75. Status Codes for Master Receiver Mode Status Code(TWSR) Prescaler Bitsare 0Status of the Two-wire SerialBus a

187ATmega32(L)2503C–AVR–10/02Figure 89. Formats and States in the Master Receiver ModeSlave Receiver Mode In the Slave Receiver mode, a number of dat

188ATmega32(L) 2503C–AVR–10/02The upper seven bits are the address to which the Two-wire Serial Interface will respondwhen addressed by a master. If t

189ATmega32(L)2503C–AVR–10/02Table 76. Status Codes for Slave Receiver Mode Status Code(TWSR)Prescaler Bitsare 0Status of the Two-wire Serial Busand

19ATmega32(L)2503C–AVR–10/02The following code examples show one assembly and one C function for writing to theEEPROM. The examples assume that interr

190ATmega32(L) 2503C–AVR–10/02Figure 91. Formats and States in the Slave Receiver ModeSlave Transmitter Mode In the Slave Transmitter mode, a number

191ATmega32(L)2503C–AVR–10/02The upper seven bits are the address to which the Two-wire Serial Interface will respondwhen addressed by a master. If th

192ATmega32(L) 2503C–AVR–10/02Table 77. Status Codes for Slave Transmitter ModeStatus Code(TWSR)Prescaler Bitsare 0Status of the Two-wire Serial Busa

193ATmega32(L)2503C–AVR–10/02Figure 93. Formats and States in the Slave Transmitter ModeMiscellaneous States There are two status codes that do not c

194ATmega32(L) 2503C–AVR–10/02Combining Several TWI ModesIn some cases, several TWI modes must be combined in order to complete the desiredaction. Con

195ATmega32(L)2503C–AVR–10/02Several different scenarios may arise during arbitration, as described below:• Two or more masters are performing identic

196ATmega32(L) 2503C–AVR–10/02Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and nega-tive pin AIN1. When

197ATmega32(L)2503C–AVR–10/02Analog Comparator Control and Status Register – ACSR• Bit 7 – ACD: Analog Comparator DisableWhen this bit is written logi

198ATmega32(L) 2503C–AVR–10/02• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode SelectThese bits determine which comparator events that tri

199ATmega32(L)2503C–AVR–10/02Analog to Digital ConverterFeatures • 10-bit Resolution• 0.5 LSB Integral Non-linearity• ±2 LSB Absolute Accuracy• 65 - 2

2ATmega32(L) 2503C–AVR–10/02Pin Configurations Figure 1. Pinouts ATmega32Disclaimer Typical values contained in this data sheet are based on simulati

20ATmega32(L) 2503C–AVR–10/02The next code examples show assembly and C functions for reading the EEPROM. Theexamples assume that interrupts are contr

200ATmega32(L) 2503C–AVR–10/02Figure 98. Analog to Digital Converter Block SchematicOperation The ADC converts an analog input voltage to a 10-bit di

201ATmega32(L)2503C–AVR–10/02amplified value then becomes the analog input to the ADC. If single ended channels areused, the gain amplifier is bypasse

202ATmega32(L) 2503C–AVR–10/02Figure 99. ADC Auto Trigger LogicUsing the ADC Interrupt Flag as a trigger source makes the ADC start a new conversiona

203ATmega32(L)2503C–AVR–10/02setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADENbit is set, and is continuously reset

204ATmega32(L) 2503C–AVR–10/02Figure 102. ADC Timing Diagram, Single ConversionFigure 103. ADC Timing Diagram, Auto Triggered ConversionFigure 104.

205ATmega32(L)2503C–AVR–10/02Differential Gain Channels When using differential gain channels, certain aspects of the conversion need to betaken into

206ATmega32(L) 2503C–AVR–10/02If Auto Triggering is used, the exact time of the triggering event can be indeterministic.Special care must be taken whe

207ATmega32(L)2503C–AVR–10/02external voltage. If no external voltage is applied to the AREF pin, the user may switchbetween AVCC and 2.56V as referen

208ATmega32(L) 2503C–AVR–10/02Figure 105. Analog Input CircuitryAnalog Noise Canceling TechniquesDigital circuitry inside and outside the device gene

209ATmega32(L)2503C–AVR–10/02Offset Compensation SchemesThe gain stage has a built-in offset cancellation circuitry that nulls the offset of differen-

21ATmega32(L)2503C–AVR–10/02I/O Memory The I/O space definition of the ATmega32 is shown in “Register Summary” on page 297.All ATmega32 I/Os and perip

210ATmega32(L) 2503C–AVR–10/02• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual

211ATmega32(L)2503C–AVR–10/02ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found inthe ADC Resul

212ATmega32(L) 2503C–AVR–10/02Example: ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result) Voltage on ADC3 is 300 mV, voltage

213ATmega32(L)2503C–AVR–10/02less of any ongoing conversions. For a complete description of this bit, see “The ADCData Register – ADCL and ADCH” on pa

214ATmega32(L) 2503C–AVR–10/02Note: 1. The differential input channels are not tested for devices in PDIP Package. This fea-ture is only guaranteed to

215ATmega32(L)2503C–AVR–10/02• Bits 2:0 – ADPS2:0: ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and th

216ATmega32(L) 2503C–AVR–10/02• ADC9:0: ADC Conversion ResultThese bits represent the result from the conversion, as detailed in “ADC ConversionResult

217ATmega32(L)2503C–AVR–10/02JTAG Interface and On-chip Debug SystemFeatures • JTAG (IEEE std. 1149.1 Compliant) Interface• Boundary-scan Capabilities

218ATmega32(L) 2503C–AVR–10/02The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT –which is not provided.When the JTAGEN Fus

219ATmega32(L)2503C–AVR–10/02Figure 113. TAP Controller State DiagramTAP Controller The TAP controller is a 16-state finite state machine that contro

22ATmega32(L) 2503C–AVR–10/02System Clock and Clock OptionsClock Systems and their DistributionFigure 11 presents the principal clock systems in the A

220ATmega32(L) 2503C–AVR–10/02this state is left by setting TMS high. While the instruction is shifted in from the TDI pin, the captured IR-state 0x01

221ATmega32(L)2503C–AVR–10/02• 2 single Program Memory Break Points + 1 Program Memory Break Point with mask (“range Break Point”)• 2 single Program M

222ATmega32(L) 2503C–AVR–10/02On-chip Debug Related Register in I/O MemoryOn-chip Debug Register – OCDRThe OCDR Register provides a communication chan

223ATmega32(L)2503C–AVR–10/02IEEE 1149.1 (JTAG) Boundary-scanFeatures • JTAG (IEEE std. 1149.1 Compliant) Interface• Boundary-scan Capabilities Accord

224ATmega32(L) 2503C–AVR–10/02Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Regis-ter is selected as

225ATmega32(L)2503C–AVR–10/02Figure 115. Reset RegisterBoundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the lo

226ATmega32(L) 2503C–AVR–10/02SAMPLE_PRELOAD; $2 Mandatory JTAG instruction for pre-loading the output latches and talking a snap-shot ofthe input/out

227ATmega32(L)2503C–AVR–10/02Boundary-scan Chain The Boundary-scan chain has the capability of driving and observing the logic levels onthe digital I/

228ATmega32(L) 2503C–AVR–10/02Figure 117. General Port Pin Schematic Diagram(1)Note: 1. See Boundary-scan descriptin for details.Boundary-scan and th

229ATmega32(L)2503C–AVR–10/02Figure 118. Additional Scan Signal for the Two-wire InterfaceScanning the RESET Pin The RESET pin accepts 5V active low

23ATmega32(L)2503C–AVR–10/02Asynchronous Timer Clock – clkASYThe Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clockeddirectly

230ATmega32(L) 2503C–AVR–10/02Figure 120. Boundary-scan Cells for Oscillators and Clock OptionsTable 90 summaries the scan registers for the external

231ATmega32(L)2503C–AVR–10/02Figure 121. Analog ComparatorFigure 122. General Boundary-scan Cell used for Signals for Comparator and ADCACBGBANDGAPR

232ATmega32(L) 2503C–AVR–10/02Scanning the ADCFigure 123 shows a block diagram of the ADC with all relevant control and observe signals. The Boundary-

233ATmega32(L)2503C–AVR–10/02Table 92. Boundary-scan Signals for the ADC Signal NameDirection as Seenfrom the ADC DescriptionRecommended Input when N

234ATmega32(L) 2503C–AVR–10/02Note: Incorrect setting of the switches in Figure 123 will make signal contention and may damage the part. There are sev

235ATmega32(L)2503C–AVR–10/02If the ADC is not to be used during scan, the recommended input values from Table 92should be used. The user is recommend

236ATmega32(L) 2503C–AVR–10/02Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clockfrequency. As the algorithm keeps

237ATmega32(L)2503C–AVR–10/02ATmega32 Boundary-scan OrderTable 94 shows the scan order between TDI and TDO when the Boundary-scan chain isselected as

238ATmega32(L) 2503C–AVR–10/02112 MUXEN_7 ADC111 MUXEN_6110 MUXEN_5109 MUXEN_4108 MUXEN_3107 MUXEN_2106 MUXEN_1105 MUXEN_0104 NEGSEL_2103 NEGSEL_1102

239ATmega32(L)2503C–AVR–10/0281 PB5.Data Port B80 PB5.Control79 PB5.Pullup_Enable78 PB6.Data77 PB6.Control76 PB6.Pullup_Enable75 PB7.Data74 PB7.Contro

24ATmega32(L) 2503C–AVR–10/02Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which canbe configured f

240ATmega32(L) 2503C–AVR–10/0246 PD5.Data Port D45 PD5.Control44 PD5.Pullup_Enable43 PD6.Data42 PD6.Control41 PD6.Pullup_Enable40 PD7.Data39 PD7.Contr

241ATmega32(L)2503C–AVR–10/02Notes: 1. PRIVATE_SIGNAL1 should always be scanned in as zero.2. PRIVATE_SIGNAL2 should always be scanned in as zero.Boun

242ATmega32(L) 2503C–AVR–10/02Boot Loader Support – Read-While-Write Self-ProgrammingThe Boot Loader Support provides a real Read-While-Write Self-Pro

243ATmega32(L)2503C–AVR–10/02Note that the user software can never read any code that is located inside the RWWsection during a Boot Loader software o

244ATmega32(L) 2503C–AVR–10/02Figure 125. Memory Sections(1)Note: 1. The parameters in the figure above are given in Table 100 on page 253.Boot Loade

245ATmega32(L)2503C–AVR–10/02Note: 1. “1” means unprogrammed, “0” means programmedNote: 1. “1” means unprogrammed, “0” means programmedEntering the Bo

246ATmega32(L) 2503C–AVR–10/02Note: 1. “1” means unprogrammed, “0” means programmedStore Program Memory Control Register – SPMCRThe Store Program Memo

247ATmega32(L)2503C–AVR–10/02• Bit 2 – PGWRT: Page WriteIf this bit is written to one at the same time as SPMEN, the next SPM instruction withinfour c

248ATmega32(L) 2503C–AVR–10/02Figure 126. Addressing the Flash during SPM(1)Note: 1. The different variables used in Figure 126 are listed in Table 1

249ATmega32(L)2503C–AVR–10/02Performing Page Erase by SPMTo execute Page Erase, set up the address in the Z-pointer, write “X0000011” toSPMCR and exec

25ATmega32(L)2503C–AVR–10/02The CKSEL0 Fuse together with the SUT1..0 fuses select the start-up times as shown inTable 5.Notes: 1. These options shoul

250ATmega32(L) 2503C–AVR–10/02See Table 96 and Table 97 for how the different settings of the Boot Loader bits affectthe Flash access.If bits 5..2 in

251ATmega32(L)2503C–AVR–10/02correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supplyvoltage for executing instructions

252ATmega32(L) 2503C–AVR–10/02call Do_spmadiw ZH:ZL, 2sbiw loophi:looplo, 2 ;use subi for PAGESIZEB<=256brne Wrloop; execute page writesubi ZL, low

253ATmega32(L)2503C–AVR–10/02ATmega32 Boot Loader ParametersIn Table 100 through Table 102, the parameters used in the description of the self pro-gra

254ATmega32(L) 2503C–AVR–10/02Memory ProgrammingProgram And Data Memory Lock BitsThe ATmega32 provides six Lock bits which can be left unprogrammed (“

255ATmega32(L)2503C–AVR–10/02Notes: 1. Program the fuse bits before programming the Lock bits.2. “1” means unprogrammed, “0” means programmedFuse Bits

256ATmega32(L) 2503C–AVR–10/02Notes: 1. The default value of SUT1..0 results in maximum start-up time. SeeTable 10 on page28 for details.2. The defaul

257ATmega32(L)2503C–AVR–10/02Parallel Programming Parameters, Pin Mapping, and CommandsThis section describes how to parallel program and verify Flash

258ATmega32(L) 2503C–AVR–10/02Table 108. Pin Values used to Enter Programming ModePin Symbol ValuePAGEL Prog_enable[3] 0XA1 Prog_enable[2] 0XA0 Prog_

259ATmega32(L)2503C–AVR–10/02Parallel ProgrammingEnter Programming Mode The following algorithm puts the device in Parallel Programming mode:1. Apply

26ATmega32(L) 2503C–AVR–10/02Low-frequency Crystal OscillatorTo use a 32.768 kHz watch crystal as the clock source for the device, the Low-fre-quency

260ATmega32(L) 2503C–AVR–10/02Programming the Flash The Flash is organized in pages, see Table 111 on page 258. When programming theFlash, the program

261ATmega32(L)2503C–AVR–10/02G. Load Address High byte1. Set XA1, XA0 to “00”. This enables address loading.2. Set BS1 to “1”. This selects high addre

262ATmega32(L) 2503C–AVR–10/02Figure 129. Programming the Flash Waveforms(1)Note: 1. “XX” is don’t care. The letters refer to the programming descrip

263ATmega32(L)2503C–AVR–10/02Programming the EEPROM The EEPROM is organized in pages, see Table 112 on page 258. When programmingthe EEPROM, the progr

264ATmega32(L) 2503C–AVR–10/025. Set BS1 to “1”. The Flash word high byte can now be read at DATA.6. Set OE to “1”.Reading the EEPROM The algorithm fo

265ATmega32(L)2503C–AVR–10/02Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming theFlash” on p

266ATmega32(L) 2503C–AVR–10/02Parallel Programming CharacteristicsFigure 133. Parallel Programming Timing, Including some General TimingRequirementsF

267ATmega32(L)2503C–AVR–10/02Figure 135. Parallel Programming Timing, Reading Sequence (within the Same Page)with Timing Requirements(1)Note: 1. The

268ATmega32(L) 2503C–AVR–10/02Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lockbits commands.2. tWLRH_CE is

269ATmega32(L)2503C–AVR–10/02Chip Erase instruction. The Chip Erase operation turns the content of every memorylocation in both the Program and EEPROM

27ATmega32(L)2503C–AVR–10/02When this Oscillator is selected, start-up times are determined by the SUT fuses asshown in Table 8.Note: 1. This option s

270ATmega32(L) 2503C–AVR–10/02Data Polling Flash When a page is being programmed into the Flash, reading an address location withinthe page being prog

271ATmega32(L)2503C–AVR–10/02Note: a = address high bitsb = address low bitsH = 0 – Low byte, 1 – High Byteo = data outi = data inx = don’t careTable

272ATmega32(L) 2503C–AVR–10/02SPI Serial Programming CharacteristicsFor Characteristics of SPI module, see “SPI Timing Characteristics” on page 288.Pr

273ATmega32(L)2503C–AVR–10/02Figure 138. State Machine Sequence for Changing the Instruction WordAVR_RESET ($C) The AVR specific public JTAG instruct

274ATmega32(L) 2503C–AVR–10/02PROG_COMMANDS ($5) The AVR specific public JTAG instruction for entering programming commands via theJTAG port. The 15-b

275ATmega32(L)2503C–AVR–10/02Programming Enable Register The Programming Enable Register is a 16-bit register. The contents of this register iscompare

276ATmega32(L) 2503C–AVR–10/02Table 117. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 – Low byte, 1 – High By

277ATmega32(L)2503C–AVR–10/025c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx5d. Read Data Byte 0110011_bbbbbbbb0110010_000000000110011_000

278ATmega32(L) 2503C–AVR–10/02Notes: 1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (whi

279ATmega32(L)2503C–AVR–10/02Figure 141. State Machine Sequence for Changing/Reading the Data WordVirtual Flash Page Load RegisterThe Virtual Flash P

28ATmega32(L) 2503C–AVR–10/02When this Oscillator is selected, start-up times are determined by the SUT fuses asshown in Table 10. XTAL1 and XTAL2 sho

280ATmega32(L) 2503C–AVR–10/02Figure 142. Virtual Flash Page Load RegisterVirtual Flash Page Read RegisterThe Virtual Flash Page Read Register is a v

281ATmega32(L)2503C–AVR–10/02Programming Algorithm All references below of type “1a”, “1b”, and so on, refer to Table 117.Entering Programming Mode 1.

282ATmega32(L) 2503C–AVR–10/02Reading the Flash 1. Enter JTAG instruction PROG_COMMANDS.2. Enable Flash read using programming instruction 3a.3. Load

283ATmega32(L)2503C–AVR–10/025. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH (refer to Table 113 on page 267).6. L

284ATmega32(L) 2503C–AVR–10/02Electrical CharacteristicsAbsolute Maximum Ratings*DC Characteristics Operating Temperature...

285ATmega32(L)2503C–AVR–10/02Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low2. “Min” means the lowest value wher

286ATmega32(L) 2503C–AVR–10/026] The sum of all IOH, for ports C0 - C7, should not exceed 200 mA.If IOH exceeds the test condition, VOH may exceed the

287ATmega32(L)2503C–AVR–10/02Two-wire Serial Interface CharacteristicsTable 120 describes the requirements for devices connected to the Two-wire Seria

288ATmega32(L) 2503C–AVR–10/025. This requirement applies to all ATmega32 Two-wire Serial Interface operation. Otherdevices connected to the Two-wire

289ATmega32(L)2503C–AVR–10/02Figure 146. SPI Interface Timing Requirements (Master Mode)Figure 147. SPI Interface Timing Requirements (Slave Mode)MO

29ATmega32(L)2503C–AVR–10/02External Clock To drive the device from an external clock source, XTAL1 should be driven as shown inFigure 14. To run the

290ATmega32(L) 2503C–AVR–10/02ADC Characteristics – Preliminary DataTable 122. ADC Characteristics Symbol Parameter Condition Min Typ Max UnitsResolu

291ATmega32(L)2503C–AVR–10/02Notes: 1. Minimum for AVCC is 2.7V.2. Maximum for AVCC is 5.5V.VINTInternal Voltage Reference 2.3 2.56 2.7 VRREFReference

292ATmega32(L) 2503C–AVR–10/02ATmega32 Typical Characteristics – Preliminary DataThe following charts show typical behavior. These figures are not tes

293ATmega32(L)2503C–AVR–10/02Figure 148. RC Oscillator Frequency vs. Temperature (the devices are calibrated to1 MHz at Vcc = 5V, T=25c)Figure 149.

294ATmega32(L) 2503C–AVR–10/02Figure 150. RC Oscillator Frequency vs. Temperature (the devices are calibrated to2 MHz at Vcc = 5V, T=25c)Figure 151.

295ATmega32(L)2503C–AVR–10/02Figure 152. RC Oscillator Frequency vs. Temperature (the devices are calibrated to4 MHz at Vcc = 5V, T=25c)Figure 153.

296ATmega32(L) 2503C–AVR–10/02Figure 154. RC Oscillator Frequency vs. Temperature (the devices are calibrated to 8MHz at Vcc = 5V, T=25c)Figure 155.

297ATmega32(L)2503C–AVR–10/02Register SummaryAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page$3F ($5F) SREG I T H S V N Z C 8$3E ($5E

298ATmega32(L) 2503C–AVR–10/02Notes: 1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debu

299ATmega32(L)2503C–AVR–10/02Instruction Set SummaryMnemonics Operands Description Operation Flags #ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr

3ATmega32(L)2503C–AVR–10/02Overview The ATmega32 is a low-power CMOS 8-bit microcontroller based on the AVR enhancedRISC architecture. By executing po

30ATmega32(L) 2503C–AVR–10/02Power Management and Sleep ModesSleep modes enable the application to shut down unused modules in the MCU, therebysaving

300ATmega32(L) 2503C–AVR–10/02BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1 / 2BRID k Branch if Interrupt Disabled if (

301ATmega32(L)2503C–AVR–10/02CLH Clear Half Carry Flag in SREG H ← 0 H 1MCU CONTROL INSTRUCTIONSNOP No Operation None 1SLEEP Sleep (see specific desc

302ATmega32(L) 2503C–AVR–10/02Ordering InformationSpeed (MHz) Power Supply Ordering Code Package Operation Range8 2.7 - 5.5V ATmega32L-8ACATmega32L-8P

303ATmega32(L)2503C–AVR–10/02Packaging Information44A1.20(0.047) MAX10.10(0.394) 9.90(0.386)SQ12.25(0.482)11.75(0.462)SQ0.75(0.030)0.45(0.018)0.15(0.

304ATmega32(L) 2503C–AVR–10/0240P652.71(2.075)51.94(2.045)PIN113.97(0.550)13.46(0.530)0.38(0.015)MIN0.56(0.022)0.38(0.015)REF15.88(0.625)15.24(0.600)1

305ATmega32(L)2503C–AVR–10/0244M1 2325 Orchard Parkway San Jose, CA 95131TITLE44M1, 44-pad ,7 x 7 x 1.0 mm body, lead pitch 0.50mmMicro lead frame

306ATmega32(L) 2503C–AVR–10/02ErrataATmega32 Rev. A There are no errata for this revision of ATmega32.

307ATmega32(L)2503C–AVR–10/02Data Sheet Change Log for ATmega32Please note that the referring page numbers in this section are referred to this docu-m

iATmega32(L)2503C–AVR–10/02Table of Contents Features...

iiATmega32(L) 2503C–AVR–10/02Minimizing Power Consumption ... 32System Control a

31ATmega32(L)2503C–AVR–10/02Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enterIdle mode, stopping the CPU bu

iiiATmega32(L)2503C–AVR–10/02Compare Match Output Unit ... 115Modes of Opera

ivATmega32(L) 2503C–AVR–10/02ADC Conversion Result... 211JTAG Interfa

vATmega32(L)2503C–AVR–10/02External Clock Drive Waveforms ... 286External Clock Dri

Printed on recycled paper.© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than those expressly contai

32ATmega32(L) 2503C–AVR–10/02Asynchronous Timer should be considered undefined after wake-up in Power-savemode if AS2 is 0.This sleep mode basically h

33ATmega32(L)2503C–AVR–10/02Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. Whenentering ADC Noise Re

34ATmega32(L) 2503C–AVR–10/02System Control and ResetResetting the AVR During Reset, all I/O Registers are set to their initial values, and the progra

35ATmega32(L)2503C–AVR–10/02Figure 15. Reset LogicNotes: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT(falling).2

36ATmega32(L) 2503C–AVR–10/02Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-tion level is defined

37ATmega32(L)2503C–AVR–10/02External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longerthan the minimum pulse w

38ATmega32(L) 2503C–AVR–10/02Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura-tion. On the fallin

39ATmega32(L)2503C–AVR–10/02Internal Voltage ReferenceATmega32 features an internal bandgap reference. This reference is used for Brown-out Detection,

4ATmega32(L) 2503C–AVR–10/02The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are directly c

40ATmega32(L) 2503C–AVR–10/02Watchdog Timer Control Register – WDTCR• Bits 7..5 – Res: Reserved BitsThese bits are reserved bits in the ATmega32 and w

41ATmega32(L)2503C–AVR–10/02The following code example shows one assembly and one C function for turning off theWDT. The example assumes that interrup

42ATmega32(L) 2503C–AVR–10/02Interrupts This section describes the specifics of the interrupt handling as performed inATmega32. For a general explanat

43ATmega32(L)2503C–AVR–10/02Note: 1. The Boot Reset Address is shown in Table 100 on page 253. For the BOOTRSTFuse “1” means unprogrammed while “0” me

44ATmega32(L) 2503C–AVR–10/02When the BOOTRST Fuse is unprogrammed, the Boot section size set to 4K bytes andthe IVSEL bit in the GICR Register is set

45ATmega32(L)2503C–AVR–10/02Moving Interrupts Between Application and Boot SpaceThe General Interrupt Control Register controls the placement of the I

46ATmega32(L) 2503C–AVR–10/02• Bit 0 – IVCE: Interrupt Vector Change EnableThe IVCE bit must be written to logic one to enable change of the IVSEL bit

47ATmega32(L)2503C–AVR–10/02I/O PortsIntroduction All AVR ports have true Read-Modify-Write functionality when used as general digitalI/O ports. This

48ATmega32(L) 2503C–AVR–10/02Ports as General Digital I/OThe ports are bi-directional I/O ports with optional internal pull-ups. Figure 23 shows afunc

49ATmega32(L)2503C–AVR–10/02enabled state is fully acceptable, as a high-impedant environment will not notice the dif-ference between a strong high dr

5ATmega32(L)2503C–AVR–10/02Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Po

50ATmega32(L) 2503C–AVR–10/02succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, asingle signal transition on the pin

51ATmega32(L)2503C–AVR–10/02The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, anddefine the port pins from 4 to 7 as

52ATmega32(L) 2503C–AVR–10/02Unconnected pins If some pins are unused, it is recommended to ensure that these pins have a definedlevel. Even though mo

53ATmega32(L)2503C–AVR–10/02Table 21 summarizes the function of the overriding signals. The pin and port indexesfrom Figure 26 are not shown in the su

54ATmega32(L) 2503C–AVR–10/02Special Function I/O Register – SFIOR• Bit 2 – PUD: Pull-up disableWhen this bit is written to one, the pull-ups in the I

55ATmega32(L)2503C–AVR–10/02Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 25.The alternate pin configurati

56ATmega32(L) 2503C–AVR–10/02DDB6. When the pin is forced by the SPI to be an input, the pull-up can still be con-trolled by the PORTB6 bit.• MOSI – P

57ATmega32(L)2503C–AVR–10/02 Table 26. Overriding Signals for Alternate Functions in PB7..PB4SignalName PB7/SCK PB6/MISO PB5/MOSI PB4/SSPUOE SPE • MS

58ATmega32(L) 2503C–AVR–10/02Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 28. If the JTAG interface isena

59ATmega32(L)2503C–AVR–10/02• TCK – Port C, Bit 2TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG inter-face is enabled, this

6ATmega32(L) 2503C–AVR–10/02AVR CPU CoreIntroduction This section discusses the AVR core architecture in general. The main function of theCPU core is

60ATmega32(L) 2503C–AVR–10/02Note: 1. When enabled, the Two-wire Serial Interface enables slew-rate controls on the outputpins PC0 and PC1. This is no

61ATmega32(L)2503C–AVR–10/02• OC1A – Port D, Bit 5OC1A, Output Compare Match A output: The PD5 pin can serve as an external outputfor the Timer/Counte

62ATmega32(L) 2503C–AVR–10/02 Register Description for I/O PortsPort A Data Register – PORTAPort A Data Direction Register – DDRAPort A Input Pins Add

63ATmega32(L)2503C–AVR–10/02Port B Input Pins Address – PINBPort C Data Register – PORTCPort C Data Direction Register – DDRCPort C Input Pins Address

64ATmega32(L) 2503C–AVR–10/02External Interrupts The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, ifenabled, the

65ATmega32(L)2503C–AVR–10/02• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0The External Interrupt 0 is activated by the external

66ATmega32(L) 2503C–AVR–10/02ISC10) in the MCU General Control Register (MCUCR) define whether the ExternalInterrupt is activated on rising and/or fal

67ATmega32(L)2503C–AVR–10/028-bit Timer/Counter0 with PWMTimer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. Themain feat

68ATmega32(L) 2503C–AVR–10/02The double buffered Output Compare Register (OCR0) is compared with theTimer/Counter value at all times. The result of th

69ATmega32(L)2503C–AVR–10/02BOTTOM Signalize that TCNT0 has reached minimum value (zero).Depending of the mode of operation used, the counter is clear

7ATmega32(L)2503C–AVR–10/02an arithmetic operation, the Status Register is updated to reflect information about theresult of the operation.Program flo

70ATmega32(L) 2503C–AVR–10/02The OCR0 Register is double buffered when using any of the Pulse Width Modulation(PWM) modes. For the normal and Clear Ti

71ATmega32(L)2503C–AVR–10/02Figure 30. Compare Match Output Unit, SchematicThe general I/O port function is overridden by the Output Compare (OC0) fr

72ATmega32(L) 2503C–AVR–10/02Normal Mode The simplest mode of operation is the normal mode (WGM01:0 = 0). In this mode thecounting direction is always

73ATmega32(L)2503C–AVR–10/02quency of fOC0 = fclk_I/O/2 when OCR0 is set to zero (0x00). The waveform frequency isdefined by the following equation:Th

74ATmega32(L) 2503C–AVR–10/02pin is set as output. The PWM waveform is generated by setting (or clearing) the OC0register at the compare match between

75ATmega32(L)2503C–AVR–10/02Figure 33. Phase Correct PWM Mode, Timing DiagramThe Timer/Counter Overflow Flag (TOV0) is set each time the counter reac

76ATmega32(L) 2503C–AVR–10/02Timer/Counter Timing DiagramsThe Timer/Counter is a synchronous design and the timer clock (clkT0) is thereforeshown as a

77ATmega32(L)2503C–AVR–10/02Figure 36. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (fclk_I/O/8)Figure 37 shows the setting of OCF0

78ATmega32(L) 2503C–AVR–10/028-bit Timer/Counter Register DescriptionTimer/Counter Control Register – TCCR0• Bit 7 – FOC0: Force Output CompareThe FOC

79ATmega32(L)2503C–AVR–10/02When OC0 is connected to the pin, the function of the COM01:0 bits depends on theWGM01:0 bit setting. Table 39 shows the C

8ATmega32(L) 2503C–AVR–10/02Status Register The Status Register contains information about the result of the most recently executedarithmetic instruct

80ATmega32(L) 2503C–AVR–10/02If external pin modes are used for the Timer/Counter0, transitions on the T0 pin willclock the counter even if the pin is

81ATmega32(L)2503C–AVR–10/02Timer/Counter Interrupt Flag Register – TIFR• Bit 1 – OCF0: Output Compare Flag 0The OCF0 bit is set (one) when a compare

82ATmega32(L) 2503C–AVR–10/02Timer/Counter0 and Timer/Counter1 PrescalersTimer/Counter1 and Timer/Counter0 share the same prescaler module, but theTim

83ATmega32(L)2503C–AVR–10/02than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Sincethe edge detector uses samp

84ATmega32(L) 2503C–AVR–10/0216-bit Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event man-agement), wave ge

85ATmega32(L)2503C–AVR–10/02Figure 40. 16-bit Timer/Counter Block Diagram(1)Note: 1. Refer to Figure 1 on page 2, Table 25 on page 55, and Table 31 o

86ATmega32(L) 2503C–AVR–10/02(OC1A/B). See “Output Compare Units” on page 92. The compare match event will alsoset the Compare Match Flag (OCF1A/B) wh

87ATmega32(L)2503C–AVR–10/02Accessing 16-bit RegistersThe TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVRCPU via the 8-b

88ATmega32(L) 2503C–AVR–10/02The following code examples show how to do an atomic read of the TCNT1 Registercontents. Reading any of the OCR1A/B or IC

89ATmega32(L)2503C–AVR–10/02The following code examples show how to do an atomic write of the TCNT1 Registercontents. Writing any of the OCR1A/B or IC

9ATmega32(L)2503C–AVR–10/02• Bit 0 – C: Carry FlagThe Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruc-tion Set De

90ATmega32(L) 2503C–AVR–10/02Figure 41. Counter Unit Block DiagramSignal description (internal signals):Count Increment or decrement TCNT1 by 1.Direc

91ATmega32(L)2503C–AVR–10/02Input Capture Unit The Timer/Counter incorporates an input capture unit that can capture external eventsand give them a ti

92ATmega32(L) 2503C–AVR–10/02For more information on how to access the 16-bit registers refer to “Accessing 16-bitRegisters” on page 87.Input Capture

93ATmega32(L)2503C–AVR–10/02be cleared by software by writing a logical one to its I/O bit location. The Waveform Gen-erator uses the match signal to

94ATmega32(L) 2503C–AVR–10/02byte I/O location is written by the CPU, the TEMP Register will be updated by the valuewritten. Then when the low byte (O

95ATmega32(L)2503C–AVR–10/02Figure 44. Compare Match Output Unit, SchematicThe general I/O port function is overridden by the Output Compare (OC1x) f

96ATmega32(L) 2503C–AVR–10/02Normal Mode The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode thecounting direction is always

97ATmega32(L)2503C–AVR–10/02this feature is not desirable. An alternative will then be to use the fast PWM mode usingOCR1A for defining TOP (WGM13:0 =

98ATmega32(L) 2503C–AVR–10/02Figure 46. Fast PWM Mode, Timing DiagramThe Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP.

99ATmega32(L)2503C–AVR–10/02seting (or clearing) the OC1x Register at the compare match between OCR1x andTCNT1, and clearing (or setting) the OC1x Reg