Rainbow-electronics ATmega8515L User Manual

1Features• High-performance, Low-power AVR®8-bit Microcontroller• RISC Architecture– 130 Powerful Instructions – Most Single Clock Cycle Execution– 32

10ATmega8515(L)2512A–AVR–04/02The X-register, Y-register, andZ-registerThe registers R26..R31 have some addedfunctions to their generalpurposeusage.Th

100ATmega8515(L)2512A–AVR–04/02Timer/Counter ClockSourcesTheTimer/Countercan be clockedbyan internal or an externalclock source. The clocksourceissele

101ATmega8515(L)2512A–AVR–04/02howwaveforms are generated on the Output Compare outputsOC1x. For more detailsabout advancedcounting sequences andwavef

102ATmega8515(L)2512A–AVR–04/02byte iscopied into the highbyte temporary register(TEMP). When the CPUreads theICR1HI/Olocation it will access theTEMP

103ATmega8515(L)2512A–AVR–04/02measuring frequency only, the clearing of the ICF1 flag is not required(if an interrupthandler is used).Output Compare

104ATmega8515(L)2512A–AVR–04/02sequence. The synchronization prevents theoccurrenceof odd-length, non-symmetricalPWM pulses, thereby making the output

105ATmega8515(L)2512A–AVR–04/02Compare Match OutputUnitTheCompare Output mode(COM1x1:0)bitshave two functions.The Waveform Gener-ator uses the COM1x1:

106ATmega8515(L)2512A–AVR–04/02Compare Output Mode andWaveform GenerationThe Waveform Generator uses the COM1x1:0 bitsdifferently in Normal, CTC, and

107ATmega8515(L)2512A–AVR–04/02Clear Timer on CompareMatch (CTC) ModeInclear timer on compareorCTC mode (WGM13:0 = 4or 12), the OCR1A orICR1 Reg-ister

108ATmega8515(L)2512A–AVR–04/02Fast PWM Mode Thefast Pulse Width ModulationorfastPWM mode (WGM13:0 = 5,6,7,14, or 15)pro-vides a highfrequency PWM wav

109ATmega8515(L)2512A–AVR–04/02eitherOCR1A orICR1 is usedfordefining theTOPvalue. If one of theinterrupts areenabled, theinterrupt handlerroutine can

11ATmega8515(L)2512A–AVR–04/02Instruction ExecutionTimingThissection describes the general access timing conceptsfor instruction execution. TheAVR CPU

110ATmega8515(L)2512A–AVR–04/02Phase Correct PWM Mode Thephase correct Pulse Width Modulationorphase correctPWM mode (WGM13:0 = 1,2,3,10, or 11)provid

111ATmega8515(L)2512A–AVR–04/02TheTimer/CounterOverflowFlag (TOV1) isset each time the counterreachesBOT-TOM. When eitherOCR1A orICR1 is usedfordefini

112ATmega8515(L)2512A–AVR–04/02Phase and Frequency CorrectPWM ModeThephase and frequency correct Pulse Width Modulation,orphaseandfrequency cor-rectPW

113ATmega8515(L)2512A–AVR–04/02TheTimer/CounterOverflowFlag (TOV1) isset at the same timerclock cycleas theOCR1x Registers areupdatedwith the double b

114ATmega8515(L)2512A–AVR–04/02Timer/Counter TimingDiagramsTheTimer/Counter is a synchronousdesign and thetimerclock (clkT1) is thereforeshownas a clo

115ATmega8515(L)2512A–AVR–04/02Figure 57. Timer/Counter Timing Diagram,NoPrescalingFigure58shows the same timing data,but with the prescaler enabled.F

116ATmega8515(L)2512A–AVR–04/0216-bit Timer/CounterRegister DescriptionTimer/Counter1 ControlRegister A – TCCR1A• Bit 7:6 – COM1A1:0: Compare Output M

117ATmega8515(L)2512A–AVR–04/02Note: 1. A specialcaseoccurs when OCR1A/OCR1B equals TOPandCOM1A1/COM1B1isset. See “Phase CorrectPWM Mode” on page 110.

118ATmega8515(L)2512A–AVR–04/02Note: 1. The CTC1and PWM11:0 bit definition names areobsolete. Usethe WGM12:0 definitions. However, the functionality a

119ATmega8515(L)2512A–AVR–04/02When the ICR1 is used as TOPvalue (see description of the WGM13:0 bitslocated intheTCCR1A and theTCCR1B Register), the

12ATmega8515(L)2512A–AVR–04/02also bemoved to the startof the Boot Flash section by programming the BOOTRSTFuse,see “Boot LoaderSupport–Read-While-Wri

120ATmega8515(L)2512A–AVR–04/02Output Compare Register 1 A– OCR1AH and OCR1ALOutput Compare Register 1 B– OCR1BH and OCR1BLThe Output Compare Register

121ATmega8515(L)2512A–AVR–04/02• Bit 6 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt EnableWhen thisbit iswrittentoone, and the I-flag in

122ATmega8515(L)2512A–AVR–04/02• Bit 3 – ICF1: Timer/Counter1, Input Capture FlagThisflag isset when a capture event occurs on the ICP1 pin. When the

123ATmega8515(L)2512A–AVR–04/02Serial PeripheralInterface–SPIThe Serial PeripheralInterface (SPI) allows high-speedsynchronousdata transferbetween the

124ATmega8515(L)2512A–AVR–04/02When configured as a Master, the SPI interface has no automaticcontrol of the SS line.This must be handledbyusersoftwar

125ATmega8515(L)2512A–AVR–04/02The following codeexamplesshowhow to initializethe SPI as a Master andhow to per-formasimpletransmission. DDR_SPI in th

126ATmega8515(L)2512A–AVR–04/02The following codeexamplesshowhow to initializethe SPI as a Slave andhow to per-formasimple reception.Note: 1. Theexamp

127ATmega8515(L)2512A–AVR–04/02SS Pin FunctionalitySlave Mode When the SPI isconfigured as a Slave, the Slave Select (SS)pin is always input. WhenSSis

128ATmega8515(L)2512A–AVR–04/02• Bit 4 – MSTR: Master/Slave SelectThisbit selectsMasterSPI mode when writtentoone, andSlave SPI mode when writtenlogic

129ATmega8515(L)2512A–AVR–04/02SPI Status Register – SPSR• Bit 7 – SPIF: SPI Interrupt FlagWhen a serial transfer iscomplete, the SPIF flag isset. An

13ATmega8515(L)2512A–AVR–04/02When using the SEI instruction to enableinterrupts, theinstruction following SEI will beexecutedbeforeanypending interru

130ATmega8515(L)2512A–AVR–04/02Data Modes Thereare fourcombinations ofSCKphaseandpolaritywithrespecttoserialdata,which are determinedbycontrolbitsCPHA

131ATmega8515(L)2512A–AVR–04/02USART The UniversalSynchronous and Asynchronousserial Receiver and Transmitter(USART) is a highly flexible serialcommun

132ATmega8515(L)2512A–AVR–04/02Figure 63. USART Block Diagram(1)Note: 1. Refer to Figure1onpage 2, Table 37 on page 70, and Table 31onpage 66 forUSART

133ATmega8515(L)2512A–AVR–04/02AVRUSARTvs.AVRUART–CompatibilityThe USART isfully compatible with theAVRUART regarding:• Bit locations insideall USART

134ATmega8515(L)2512A–AVR–04/02Signaldescription:txclk Transmitterclock. (InternalSignal)rxclk Receiverbase clock. (InternalSignal)xcki Input from XCK

135ATmega8515(L)2512A–AVR–04/02Double Speed Operation(U2X)Thetransferrate can be doubledbysetting the U2Xbit in UCSRA. Setting thisbit onlyhas effect

136ATmega8515(L)2512A–AVR–04/02Frame Formats A serialframe isdefined to be one character ofdata bitswithsynchronization bits(startandstopbits), and op

137ATmega8515(L)2512A–AVR–04/02If used, the paritybit islocatedbetween the last data bit andfirst stopbit of a serialframe.USART Initialization The US

138ATmega8515(L)2512A–AVR–04/02be placeddirectly in themainroutine, orbe combinedwith initialization code for otherI/O modules.Data Transmission – The

139ATmega8515(L)2512A–AVR–04/02Sending Frames with 9 DataBitsIf 9-bit characters areused(UCSZ=7),theninthbit must be writtentotheTXB8 bit inUCSRBbefor

14ATmega8515(L)2512A–AVR–04/02AVR ATmega8515MemoriesThissection describes the different memories in the ATmega8515. The AVR architec-ture has twomainm

140ATmega8515(L)2512A–AVR–04/02empty interrupt, otherwiseanew interrupt will occur oncetheinterrupt routineterminates.TheTransmit Complete (TXC) flag

141ATmega8515(L)2512A–AVR–04/02Receiving Frames with 5 to 8Data BitsTheReceiverstartsdata reception when it detects avalidstart bit. Each bit that fol

142ATmega8515(L)2512A–AVR–04/02Receiving Frames with 9 DataBitsIf 9-bit characters areused(UCSZ=7)theninthbit must be readfrom theRXB8 bit inUCSRBbefo

143ATmega8515(L)2512A–AVR–04/02The receive function example reads all the I/Oregisters into the registerfile beforeanycomputation isdone. This gives a

144ATmega8515(L)2512A–AVR–04/02Parity Checker TheParityChecker is active when the highUSART Parity mode (UPM1)bit isset. Typeofparitycheck to be perfo

145ATmega8515(L)2512A–AVR–04/02Asynchronous ClockRecoveryThe clock recovery logicsynchronizes internalclock to theincoming serialframes. Fig-ure 67 il

146ATmega8515(L)2512A–AVR–04/02Figure 69 shows the sampling of the stopbit and theearliest possible beginning of thestart bit of thenext frame.Figure

147ATmega8515(L)2512A–AVR–04/02The recommendations of themaximum receiverbaudrate errorwas madeunder theassumption that the receiver and transmitter e

148ATmega8515(L)2512A–AVR–04/02The Multi-processorCommunication modeenablesseveralSlave MCUs to receive datafrom a MasterMCU.This isdone by first deco

149ATmega8515(L)2512A–AVR–04/02AccessingUBRRH/UCSRCRegistersThe UBRRH Registershares the same I/Olocation as the UCSRC Register.Thereforesome specialc

15ATmega8515(L)2512A–AVR–04/02SRAM Data Memory Figure 9shows how the ATmega8515 SRAMMemory is organized.The lower608 Data Memory locations address the

150ATmega8515(L)2512A–AVR–04/02Read Access Doing a read access to the UBRRH or the UCSRC Register is amore complex opera-tion. However, in mostapplica

151ATmega8515(L)2512A–AVR–04/02Thetransmit buffercan only be written when the UDREflag in the UCSRA Register isset. Data written to UDR when the UDREf

152ATmega8515(L)2512A–AVR–04/02• Bit2–PE:ParityErrorThisbit isset if thenext character in the receive bufferhad aParityErrorwhen receivedand the parit

153ATmega8515(L)2512A–AVR–04/02Buffer Registerdonotcontain data to betransmitted. When disabled, theTransmitterwill no longer overridetheTxD port.• Bi

154ATmega8515(L)2512A–AVR–04/02• Bit 3 – USBS: Stop Bit SelectThisbit selects the number ofstopbits to beinsertedbytheTransmitter.TheReceiverignores t

155ATmega8515(L)2512A–AVR–04/02USART Baud Rate Registers –UBRRL and UBRRHThe UBRRH Registershares the same I/Olocation as the UCSRC Register. See the“

156ATmega8515(L)2512A–AVR–04/02Table 68. Examples ofUBRR SettingsforCommonly UsedOscillatorFrequenciesBaudRate(bps)fosc= 1.0000 MHz fosc= 1.8432 MHz f

157ATmega8515(L)2512A–AVR–04/02Table 69. Examples ofUBRR SettingsforCommonly UsedOscillatorFrequencies(Continued)BaudRate(bps)fosc= 3.6864 MHz fosc= 4

158ATmega8515(L)2512A–AVR–04/02Table 70. Examples ofUBRR SettingsforCommonly UsedOscillatorFrequencies(Continued)BaudRate(bps)fosc= 8.0000 MHz fosc= 1

159ATmega8515(L)2512A–AVR–04/02Table 71. Examples ofUBRR SettingsforCommonly UsedOscillatorFrequencies(Continued)BaudRate(bps)fosc= 16.0000 MHz fosc=

16ATmega8515(L)2512A–AVR–04/02Figure 9. Data Memory MapData Memory Access Times Thissection describes the general access timing conceptsfor internal m

160ATmega8515(L)2512A–AVR–04/02Analog Comparator TheAnalog Comparatorcompares theinput values on the positive pin AIN0and nega-tive pin AIN1. When the

161ATmega8515(L)2512A–AVR–04/02theACIE bit isset and the I-bit in SREG isset. ACI isclearedbyhardware when execut-ing the corresponding interrupt hand

162ATmega8515(L)2512A–AVR–04/02Boot Loader Support– Read-While-WriteSelf-ProgrammingThe Boot LoaderSupport provides a real Read-While-Write Self-Progr

163ATmega8515(L)2512A–AVR–04/02Note that theusersoftware can neverread anycodethat islocated insidetheRWWsection during a Boot Loadersoftwareoperation

164ATmega8515(L)2512A–AVR–04/02Figure 72. Memory Sections(1)Note: 1. The parameters in the figureabove are given in Table 78onpage 173.Boot Loader Loc

165ATmega8515(L)2512A–AVR–04/02Note: 1. “1” means unprogrammed, “0” meansprogrammedNote: 1. “1” means unprogrammed, “0” meansprogrammedEntering the Bo

166ATmega8515(L)2512A–AVR–04/02Store Program MemoryControl Register – SPMCRThe StoreProgram Memory Control Registercontains the controlbits needed to

167ATmega8515(L)2512A–AVR–04/02• Bit1–PGERS:PageEraseIf thisbit iswritten to one at the same time asSPMEN, thenext SPM instruction withinfourclock cyc

168ATmega8515(L)2512A–AVR–04/02Figure 73. Addressing the Flash during SPM(1)Note: 1. The different variables used in Figure 73 are listed in Table80on

169ATmega8515(L)2512A–AVR–04/02Performing Page Erase bySPMTo execute Page Erase,set up theaddress in the Z-pointer, write “X0000011” toSPMCRand execut

17ATmega8515(L)2512A–AVR–04/02EEPROM Data Memory The ATmega8515 contains 512 bytes ofdata EEPROM memory. Itis organized as aseparate data space, in wh

170ATmega8515(L)2512A–AVR–04/02Setting the Boot Loader LockBits by SPMTo set the Boot LoaderLock bits, write the desireddatatoR0,write “X0001001” toSP

171ATmega8515(L)2512A–AVR–04/02Preventing Flash Corruption During periods oflow VCC,the Flash program can be corruptedbecausethe supply volt-age is to

172ATmega8515(L)2512A–AVR–04/02; transfer data from RAM to Flash page bufferldi looplo, low(PAGESIZEB) ;init loop variableldi loophi, high(PAGESIZEB)

173ATmega8515(L)2512A–AVR–04/02; restore SREG (to enable interrupts if originally enabled)out SREG, temp2retATmega8515 Boot LoaderParametersInTable 78

174ATmega8515(L)2512A–AVR–04/02Note: 1. Z15:Z13: always ignored.Z0:should be zero for all SPMcommands, byte select for the LPM instruction.See “Addres

175ATmega8515(L)2512A–AVR–04/02MemoryProgrammingProgram and DataMemory Lock BitsThe ATmega8515 providessixLock bitswhich can be leftunprogrammed(“1”)

176ATmega8515(L)2512A–AVR–04/02Notes: 1. Program the Fuse bitsbefore programming the Lock bits.2. “1” means unprogrammed, “0” meansprogrammedFuse Bits

177ATmega8515(L)2512A–AVR–04/02Notes: 1. The defaultvalue ofSUT1..0 results in maximum start-up time. See Table13 on page36 fordetails.2. The default

178ATmega8515(L)2512A–AVR–04/02Parallel ProgrammingParameters, PinMapping, andCommandsThissection describeshow to parallelprogram and verify Flash Pro

179ATmega8515(L)2512A–AVR–04/02Table 86. Pin Values used to Enter Programming ModePin Symbol ValuePAGEL Prog_enable[3] 0XA1 Prog_enable[2] 0XA0 Prog_e

18ATmega8515(L)2512A–AVR–04/02The EEPROM Control Register–EECR• Bits 7..4 – Res: Reserved BitsThese bits are reservedbits in the ATmega8515 andwill al

180ATmega8515(L)2512A–AVR–04/02Parallel ProgrammingEnter Programming Mode The following algorithm puts the deviceinParallel Programming mode:1. Apply

181ATmega8515(L)2512A–AVR–04/02Programming the Flash The Flash is organized in pages, see Table89 on page 179. When programming theFlash, the program

182ATmega8515(L)2512A–AVR–04/023. Wait until RDY/BSY goeshigh. (See Figure 76 forsignalwaveforms)I.Repeat B throughHuntil the entire Flash isprogramme

183ATmega8515(L)2512A–AVR–04/02Figure 76. Programming the Flash WaveformsNote: “XX”isdon’t care. The letters refer to the programming description abov

184ATmega8515(L)2512A–AVR–04/02Figure 77. Programming the EEPROM WaveformsReading the Flash Thealgorithm forreading the Flash memory is asfollows (ref

185ATmega8515(L)2512A–AVR–04/021. A:LoadCommand “0100 0000”.2. C: LoadData LowByte. Bit n = “0” programs andbit n = “1” erases the Fuse bit.3. Set BS1

186ATmega8515(L)2512A–AVR–04/02Figure 79. Mapping Between BS1,BS2, and the Fuse- andLock BitsDuring ReadReading the Signature Bytes Thealgorithm forre

187ATmega8515(L)2512A–AVR–04/02Figure 81. Parallel P rogramming Timing,Loading Se quence with TimingRequirements(1)Note: 1. The timing requirementssho

188ATmega8515(L)2512A–AVR–04/02Notes: 1. tWLRHis validfor the Write Flash, Write EEPROM, Write Fuse bits andWrite Lockbitscommands.2. tWLRH_CEis valid

189ATmega8515(L)2512A–AVR–04/02Serial Downloading Both the Flash andEEPROM memory arrays can be programmed using the serialSPIbuswhileRESETispulled to

19ATmega8515(L)2512A–AVR–04/02• Bit 0 – EERE: EEPROM Read EnableThe EEPROM ReadEnable SignalEERE is the readstrobetothe EEPROM. When thecorrectaddress

190ATmega8515(L)2512A–AVR–04/02Serial ProgrammingAlgorithmWhen writing serialdatatothe ATmega8515,data isclocked on the rising edge ofSCK.When reading

191ATmega8515(L)2512A–AVR–04/02Data Polling EEPROM Whenanewbyte hasbeen written and isbeing programmed into EEPROM, reading theaddress location being

192ATmega8515(L)2512A–AVR–04/02Note: a = address highbitsb = address lowbitsH = 0 -Lowbyte, 1 -HighByteo =data outi =data inx=don’t careTable 94. Seri

193ATmega8515(L)2512A–AVR–04/02Serial ProgrammingCharacteristicsFigure 85. Serial Programming TimingNote: 1. 2 tCLCLforfck< 12 MHz, 3 tCLCLforfck≥

194ATmega8515(L)2512A–AVR–04/02Electrical CharacteristicsAbsolute Maximum Ratings*Operating Temperature... -55°C to +12

195ATmega8515(L)2512A–AVR–04/02Notes: 1. “Max”means the highestvalue wherethe pin is guaranteed to be read aslow.2. “Min” means the lowestvalue wheret

196ATmega8515(L)2512A–AVR–04/02External Clock DriveWaveformsFigure 86. ExternalClock Drive WaveformsExternal Clock DriveNote: 1. R should beinthe rang

197ATmega8515(L)2512A–AVR–04/02SPI TimingCharacteristicsSee Figure87 andFigure88fordetails.Figure 87. SPIInterface Timing Requirements(MasterMode)Tabl

198ATmega8515(L)2512A–AVR–04/02Figure 88. SPIInterface Timing Requirements(Slave Mode)MISO(Data Output)SCK(CPOL = 1)MOSI(Data Input)SCK(CPOL = 0)SSMSB

199ATmega8515(L)2512A–AVR–04/02External Data Memory TimingNotes: 1. This assumes 50%clock duty cycle. The half period is actually the high time of the

2ATmega8515(L)2512A–AVR–04/02Pin ConfigurationsFigure 1. Pinout ATmega851512345678910111213141516171819204039383736353433323130292827262524232221(OC0/

20ATmega8515(L)2512A–AVR–04/02The following codeexamplesshow one assembly and one Cfunction forwriting to theEEPROM.Theexamples assume that interrupts

200ATmega8515(L)2512A–AVR–04/02Table 101. ExternalData Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1,SRWn0 = 0Symbol Parameter4 MHz Oscillator Va

201ATmega8515(L)2512A–AVR–04/02Notes: 1. This assumes 50%clock duty cycle. The half period is actually the high time of theexternalclock, XTA L1.2. Th

202ATmega8515(L)2512A–AVR–04/02Figure 89. ExternalMemory Timing (SRWn1 = 0,SRWn0 = 0Figure 90. ExternalMemory Timing (SRWn1 = 0,SRWn0 = 1)ALET1 T2 T3W

203ATmega8515(L)2512A–AVR–04/02Figure 91. ExternalMemory Timing (SRWn1 = 1,SRWn0 = 0)Figure 92. ExternalMemory Timing (SRWn1 = 1,SRWn0 = 1)(1)Note: 1.

204ATmega8515(L)2512A–AVR–04/02ATmega8515 TypicalCharacteristics –Preliminary DataThe following chartsshow typicalbehavior.These figures are not teste

205ATmega8515(L)2512A–AVR–04/02Figure 94. RCOscillatorFrequency vs. Operating Voltage (the devices are calibratedto 1 MHz at Vcc = 5V, T=25c)Figure 95

206ATmega8515(L)2512A–AVR–04/02Figure 96. RCOscillatorFrequency vs. Operating Voltage (the devices are calibratedto 2 MHz at Vcc = 5V, T=25c)Figure 97

207ATmega8515(L)2512A–AVR–04/02Figure 98. RCOscillatorFrequency vs. Operating Voltage (the devices are calibratedto 4 MHz at Vcc = 5V, T=25c)Figure 99

208ATmega8515(L)2512A–AVR–04/02Figure 100. RCOscillatorFrequency vs. Operating Voltage (the devices are calibratedto 8 MHz at Vcc = 5V, T=25c)CALIBRAT

209ATmega8515(L)2512A–AVR–04/02Register SummaryNotes: 1. Refer to the USART description fordetails on how to access UBRRH and UCSRC.2. Forcompatibilit

21ATmega8515(L)2512A–AVR–04/02Thenext codeexamplesshow assembly andCfunctionsforreading the EEPROM.Theexamples assume that interrupts are controlledso

210ATmega8515(L)2512A–AVR–04/023. Some of the statusflags are clearedbywriting a logical one to them. Note that the CBI and SBI instructionswill opera

211ATmega8515(L)2512A–AVR–04/02Instruction Set SummaryMnemonics Operands Description Operation Flags #ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, R

212ATmega8515(L)2512A–AVR–04/02BRIE k Branch ifInterrupt Enabled if(I=1) then PC ← PC+k+1 None1/2BRID k Branch ifInterrupt Disabled if(I=0) then PC ←

213ATmega8515(L)2512A–AVR–04/02NOP No Operation None 1SLEEP Sleep(see specificdescr. forSleepfunction)None 1WDR Watchdog Reset (see specificdescr. for

214ATmega8515(L)2512A–AVR–04/02Ordering Information(1)Note: 1. Thisdevice can also be supplied in waferform. Please contact yourlocal Atmelsales offic

215ATmega8515(L)2512A–AVR–04/02Packaging Information44A1.20(0.047) MAX10.10(0.394) 9.90(0.386)SQ12.25(0.482)11.75(0.462)SQ0.75(0.030)0.45(0.018)0.15(

216ATmega8515(L)2512A–AVR–04/0240P652.71(2.075)51.94(2.045)PIN113.97(0.550)13.46(0.530)0.38(0.015)MIN0.56(0.022)0.38(0.015)REF15.88(0.625)15.24(0.600)

217ATmega8515(L)2512A–AVR–04/0244J1.14(0.045) X 45˚PIN NO. 1IDENTIFY0.813(0.032)0.660(0.026)1.27(0.050) TYP12.70(0.500) REF SQ1.14(0.045) X 45˚0.51(0.

218ATmega8515(L)2512A–AVR–04/0244M12325 Orchard ParkwaySan Jose, CA 95131TITLE44M1, 44-pad ,7 x 7 x 1.0 mm body, lead pitch 0.50mmMicro lead frame pac

iATmega8515(L)2512A–AVR–04/02Table of ContentsFeatures...

22ATmega8515(L)2512A–AVR–04/02I/O Memory The I/Ospace definition of the ATmega8515 isshown in “RegisterSummary”onpage209.All ATmega8515 I/Os andperiph

iiATmega8515(L)2512A–AVR–04/02Internal Voltage Reference ... 47Watchdog

iiiATmega8515(L)2512A–AVR–04/02Frame Formats ... 136USAR

ivATmega8515(L)2512A–AVR–04/0244A ...

Printed on recycledpaper.© Atmel Corporation 2002.AtmelCorporation makes no warrantyfor theuseof itsproducts, other than thoseexpressly contained in t

23ATmega8515(L)2512A–AVR–04/02Figure 11. ExternalMemory withSectorSelectUsing the External MemoryInterfaceTheinterface consists of:•AD7:0:Multiplexedl

24ATmega8515(L)2512A–AVR–04/02data direction settings areused. Note that when the XMEM interfaceisdisabled, theaddress spaceabove theinternalSRAMbound

25ATmega8515(L)2512A–AVR–04/02time for theexternal memory in conjunction with the set-uprequirement of theATmega8515. Theaccess time for theexternal m

26ATmega8515(L)2512A–AVR–04/02Figure 14. ExternalData Memory CycleswithSRWn1 = 0andSRWn0 = 1(1)Note: 1. SRWn1 =SRW11 (uppersector) orSRW01 (lowersecto

27ATmega8515(L)2512A–AVR–04/02Figure 16. ExternalData Memory CycleswithSRWn1 = 1andSRWn0 = 1(1)Note: 1. SRWn1 =SRW11 (uppersector) orSRW01 (lowersecto

28ATmega8515(L)2512A–AVR–04/02SRAM address spaceisconfigured as one sector, the wait states are configuredbytheSRW11 andSRW10 bits.• Bit 1 and Bit 6 M

29ATmega8515(L)2512A–AVR–04/02Special Function IO Register –SFIOR•Bit6–XMBK: External Memory Bus Keeper EnableWriting XMBK to one enables the BusKeepe

3ATmega8515(L)2512A–AVR–04/02Overview The ATmega8515 is a low-powerCMOS8-bit microcontrollerbased on theAVRenhanced RISC architecture. By executing po

30ATmega8515(L)2512A–AVR–04/02Using all 64KB Locations ofExternal MemorySincethe ExternalMemory is mapped after the InternalMemory asshowninFigure11,o

31ATmega8515(L)2512A–AVR–04/02System Clock andClock OptionsClock Systems and theirDistributionFigure17presents the principalclock systems in the AVR a

32ATmega8515(L)2512A–AVR–04/02Flash Clock – clkFLASHThe Flash clock controls operation of the Flash interface. The Flash clock is usuallyactive simult

33ATmega8515(L)2512A–AVR–04/02Figure 18. CrystalOscillatorConnectionsThe Oscillatorcan operateinthree different modes, each optimizedfor a specificfre

34ATmega8515(L)2512A–AVR–04/02Notes: 1. Theseoptionsshould only beusedwhen not operating closetothemaximum fre-quency of the device, and only iffreque

35ATmega8515(L)2512A–AVR–04/02External RC Oscillator For timing insensitive applications, theexternal RCconfiguration showninFigure19can beused.The fr

36ATmega8515(L)2512A–AVR–04/02Calibrated Internal RCOscillatorThe calibrated internal RCOscillatorprovides a fixed 1.0, 2.0, 4.0, or 8.0 MHz clock.All

37ATmega8515(L)2512A–AVR–04/02External Clock To drive the device from an externalclock source,XTAL1 should be driven asshowninFigure20.Torun the devic

38ATmega8515(L)2512A–AVR–04/02Power Managementand Sleep ModesSleep modes enabletheapplication to shut down unused modules in the MCU, therebysaving po

39ATmega8515(L)2512A–AVR–04/02• Bits 7 – SM0: Sleep Mode Select Bit 0The SleepMode Select bitsselect between thethree available sleep modes asshownin

4ATmega8515(L)2512A–AVR–04/02TheAVRcore combines a rich instruction set with32 generalpurpose working registers.All the 32 registers are directly conn

40ATmega8515(L)2512A–AVR–04/02Standby Mode When the SM2..0 bits are written to 110, and an externalcrystal/resonatorclock optionisselected, the SLEEPi

41ATmega8515(L)2512A–AVR–04/02Port Pins When entering a sleep mode, all port pinsshould be configured to useminimumpower.Themostimportant thing is to

42ATmega8515(L)2512A–AVR–04/02System Control andResetResetting the AVR During Reset, all I/O Registers are set to their initial values, and the progra

43ATmega8515(L)2512A–AVR–04/02Figure 21. Reset LogicNote: 1. ThePower-on Reset will not work unless the supply voltage hasbeen below VPOT(falling)Tabl

44ATmega8515(L)2512A–AVR–04/02Power-on Reset APower-on Reset (POR)pulseis generatedbyan On-chipdetection circuit. The detec-tion level isdefined in Ta

45ATmega8515(L)2512A–AVR–04/02External Reset An External Reset is generatedbya lowlevel on theRESET pin. Reset pulseslongerthan theminimumpulse width(

46ATmega8515(L)2512A–AVR–04/02Watchdog Reset When the Watchdog times out, it will generate a short reset pulseof one CK cycle dura-tion. Onthe falling

47ATmega8515(L)2512A–AVR–04/02Internal VoltageReferenceATmega8515 features an internalbandgapreference. Thisreferenceis usedforBrown-out Detection, an

48ATmega8515(L)2512A–AVR–04/02Figure 27. Watchdog TimerWatchdog Timer ControlRegister – WDTCR• Bits 7..5 – Res: Reserved BitsThese bits are reservedbi

49ATmega8515(L)2512A–AVR–04/021. Inthe same operation,write a logic one to WDCE andWDE.Alogic one must bewritten to WDE even though it isset to one be

5ATmega8515(L)2512A–AVR–04/02Pin DescriptionsVCC Digitalsupply voltage.GND Ground.Port A (PA7..PA0) PortAis an 8-bit bi-directionalI/Oport with intern

50ATmega8515(L)2512A–AVR–04/02Timed Sequences forChanging theConfiguration of theWatchdog TimerThe sequence forchanging configuration differs slightly

51ATmega8515(L)2512A–AVR–04/02Interrupts Thissection describes the specifics of theinterrupt handling asperformed inATmega8515. For ageneral explanati

52ATmega8515(L)2512A–AVR–04/02Note: 1. The Boot Reset Address isshowninTable 78onpage 173. For the BOOTRST Fuse“1” means unprogrammedwhile “0” meanspr

53ATmega8515(L)2512A–AVR–04/02When the BOOTRST Fuseis unprogrammed, the Boot section size set to 2Kbytes andthe IVSEL bit in the GICRRegister isset be

54ATmega8515(L)2512A–AVR–04/02Moving Interrupts betweenApplication and Boot SpaceThe GeneralInterrupt Control Registercontrols the placement of the In

55ATmega8515(L)2512A–AVR–04/02• Bit 0 – IVCE: Interrupt Vector Change EnableThe IVCE bit must be written to logic one to enable change of the IVSEL bi

56ATmega8515(L)2512A–AVR–04/02I/O PortsIntroduction All AVR portshave true Read-Modify-Write functionalitywhen used as generaldigitalI/Oports.This mea

57ATmega8515(L)2512A–AVR–04/02Ports as General DigitalI/OThe ports are bi-directionalI/Oportswith optional internalpull-ups. Figure29shows afunctional

58ATmega8515(L)2512A–AVR–04/02enabledstate isfully acceptable, as a high-impedant environment will not noticethe dif-ference between a strong highdriv

59ATmega8515(L)2512A–AVR–04/02signal transition on the pin will be delayedbetween ½ and 1½ system clock perioddepending upon thetimeof assertion.When

6ATmega8515(L)2512A–AVR–04/02About CodeExamplesThisdocumentation containssimple codeexamples that briefly showhow to usevariousparts of the device. Th

60ATmega8515(L)2512A–AVR–04/02The following codeexample shows how to set port Bpins 0and 1 high, 2and3low, anddefine the port pinsfrom 4 to 7 as input

61ATmega8515(L)2512A–AVR–04/02Alternate Port Functions Most port pinshave alternate functions in addition to being generaldigitalI/Os. Figure32 shows

62ATmega8515(L)2512A–AVR–04/02The following subsectionsshortly describethealternate functionsfor each port, andrelate theoverriding signals to thealte

63ATmega8515(L)2512A–AVR–04/02Alternate Functions of Port A PortAhas an alternate function as theaddress lowbyte anddata linesfor the ExternalMemory I

64ATmega8515(L)2512A–AVR–04/02Alternate Functions Of Port B ThePort Bpinswith alternate functions are showninTable29.Thealternate pin configuration is

65ATmega8515(L)2512A–AVR–04/02DDB6. When the pin isforcedbythe SPI to beaninput, the pull-upcan still be con-trolledbythePORTB6 bit.• MOSI – Port B, B

66ATmega8515(L)2512A–AVR–04/02Table 30. Overriding Signals for Alternate Functions in PB7..PB4SignalName PB7/SCK PB6/MISO PB5/MOSI PB4/SSPUOE SPE • MS

67ATmega8515(L)2512A–AVR–04/02Alternate Functions of Port C ThePort Cpinswith alternate functions are showninTable 32.•A15–PortC,Bit7A15,External memo

68ATmega8515(L)2512A–AVR–04/02Table 33. Overriding Signals for Alternate Functions in PC7..PC4Signal Name PC7/A15 PC6/A14 PC5/A13 PC4/A12PUOE SRE • (X

69ATmega8515(L)2512A–AVR–04/02Alternate Functions of Port D ThePort Dpinswith alternate functions are showninTable 35.Thealternate pin configuration i

7ATmega8515(L)2512A–AVR–04/02The fast-access RegisterFile contains32 x 8-bit generalpurpose working registers witha single clock cycleaccess time. Thi

70ATmega8515(L)2512A–AVR–04/02•RXD–PortD,Bit0RXD, Receive Data (Data input pin forUSART). When the USART Receiver is enabledthispin isconfigured as an

71ATmega8515(L)2512A–AVR–04/02Alternate Functions of Port E ThePort Epinswith alternate functions are showninTable 38.Thealternate pin configuration i

72ATmega8515(L)2512A–AVR–04/02Register Description forI/O PortsPort A Data Register – PORTAPort A Data Direction Register– DDRAPort A Input Pins Addre

73ATmega8515(L)2512A–AVR–04/02Port C Input Pins Address –PINCPort D Data Register – PORTDPort D Data Direction Register– DDRDPort D Input Pins Address

74ATmega8515(L)2512A–AVR–04/02External Interrupts The ExternalInterrupts aretriggeredbythe INT0,INT1, andINT2 pins. Observe that, ifenabled, theinterr

75ATmega8515(L)2512A–AVR–04/02• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0The ExternalInterrupt0is activatedbytheexternalpin I

76ATmega8515(L)2512A–AVR–04/02on the pin will causeaninterrupt requestevenifINT1 isconfigured as an output. Thecorresponding interruptofExternalInterr

77ATmega8515(L)2512A–AVR–04/028-bit Timer/Counter0with PWMTimer/Counter0is ageneralpurpose,single channel, 8-bit Timer/Counter module. Themain feature

78ATmega8515(L)2512A–AVR–04/02inactive when no clock sourceisselected.Theoutput from the clock select logic isreferred to as thetimerclock (clkT0).The

79ATmega8515(L)2512A–AVR–04/02clkTnTimer/Counterclock, referred to asclkT0in the following.top Signalizethat TCNT0 hasreached maximum value.bottom Sig

8ATmega8515(L)2512A–AVR–04/02Status Register The Status Registercontains information about the resultof themost recently executedarithmetic instructio

80ATmega8515(L)2512A–AVR–04/02The OCR0 Register isdouble bufferedwhen using any of thePulse WidthModulation(PWM) modes. For thenormal andClear Timer o

81ATmega8515(L)2512A–AVR–04/02Compare Match OutputUnitThe Compare Output mode (COM01:0)bitshave two functions.The Waveform Genera-tor uses the COM01:0

82ATmega8515(L)2512A–AVR–04/02Modes of Operation Themodeof operation, i.e., the behavior of theTimer/Counter and the output comparepins, isdefinedbyth

83ATmega8515(L)2512A–AVR–04/02the counter isrunning with none or a lowprescaler value must be done withcare sincethe CTC mode does not have the double

84ATmega8515(L)2512A–AVR–04/02Figure 38. FastPWM Mode, Timing DiagramTheTimer/CounterOverflowFlag (TOV0) isset each time the counterreachesMAX. Ifthei

85ATmega8515(L)2512A–AVR–04/02Phase Correct PWM Mode The phase correctPWM mode (WGM01:0 =3)provides a highresolution phase correctPWM waveform generat

86ATmega8515(L)2512A–AVR–04/02OCR0 and TCNT0 when the counterdecrements.ThePWM frequency for theoutputwhen using phase correctPWM can be calculatedbyt

87ATmega8515(L)2512A–AVR–04/02Figure 42. Timer/Counter Timing Diagram,Setting ofOCF0,with Prescaler(fclk_I/O/8)Figure43shows the setting ofOCF0and the

88ATmega8515(L)2512A–AVR–04/02as a strobe. Thereforeitis thevalue present in the COM01:0 bits that determines theeffectof the forcedcompare.A FOC0 str

89ATmega8515(L)2512A–AVR–04/02Note: 1. A specialcaseoccurs when OCR0 equals TOPandCOM01 isset. Inthiscase, thecomparematch is ignored, but the set orc

9ATmega8515(L)2512A–AVR–04/02• Bit0–C:CarryFlagThe Carry Flag C indicates a carry in an arithmetic orlogic operation. See the“Instruc-tion Set Descrip

90ATmega8515(L)2512A–AVR–04/02Timer/Counter Register –TCNT0TheTimer/Counter Register givesdirectaccess, bothforread andwrite operations, totheTimer/Co

91ATmega8515(L)2512A–AVR–04/02Timer/Counter Interrupt FlagRegister – TIFR• Bit 1 – TOV0: Timer/Counter0 Overflow FlagThe bit TOV0 isset (one)when an o

92ATmega8515(L)2512A–AVR–04/02Timer/Counter0 andTimer/Counter1PrescalersTimer/Counter1and Timer/Counter0 sharethe same prescaler module,but theTimer/C

93ATmega8515(L)2512A–AVR–04/02theedge detector usessampling, themaximum frequency of an externalclock it candetectishalf the sampling frequency (Nyqui

94ATmega8515(L)2512A–AVR–04/0216-bitTimer/Counter1The16-bit Timer/Counter unit allows accurate program execution timing (event man-agement), wave gene

95ATmega8515(L)2512A–AVR–04/02Figure 46. 16-bit Timer/CounterBlock Diagram(1)Note: 1. Refer to Figure1onpage 2, Table29 on page 64, and Table 35onpage

96ATmega8515(L)2512A–AVR–04/02also set the Compare Match Flag (OCF1A/B) which can beused to generate an outputcompareinterrupt request.The Input Captu

97ATmega8515(L)2512A–AVR–04/02Accessing 16-bitRegistersTheTCNT1,OCR1A/B, andICR1 are16-bit registers that can beaccessedbythe AVRCPU via the8-bit data

98ATmega8515(L)2512A–AVR–04/02The following codeexamplesshowhow to doanatomicread of theTCNT1 Registercontents.Reading any of the OCR1A/B orICR1 Regis

99ATmega8515(L)2512A–AVR–04/02The following codeexamplesshowhow to doanatomicwrite of theTCNT1 Registercontents. Writing any of the OCR1A/B orICR1 Reg