W78C32C 8-BIT MICROCONTROLLER Publication Release Date: July 1999 - 1 - Revision A2 GENERAL DESCRIPTION The W78C32C microcontroller supplies a wi
W78C32C - 10 - Timing Waveforms, continued Data Write Cycle S2 S3S5 S6 S1S2 S3 S4S1S5 S6S4XTAL1ALE PSENA8-A15DATA OUTPORT 2PORT 0 A0-A7 WRTTDAWDADTDW
W78C32C Publication Release Date: July 1999 - 11 - Revision A2 TYPICAL APPLICATION CIRCUIT Using External Program Memory and Crystal AD0A0A0A0 1
W78C32C - 12 - Expanded External Data Memory and Oscillator 10 u8.2 KVOSCILLATOREA 31XTAL1 19XTAL2 18RST 9INT0 12INT1 13T0 14T1 15P1.0 1P1.1 2P1.2
W78C32C Publication Release Date: July 1999 - 13 - Revision A2 PACKAGE DIMENSIONS 40-pin DIP Seating Plane1. Dimension D Max. & S include mo
W78C32C - 14 - Package Dimensions, continued 44-pin QFP Seating Plane112212See Detail FebAy1AALL1cEEH1D44HD3433Detail F1. Dimension D & E do not
W78C32C - 2 - PIN CONFIGURATIONS Vcc12345678910111213141516171819203940343536373830313233262728292122232425P0.0, AD0P0.1, AD1P0.2, AD2P0.3, AD3P0.4,
W78C32C Publication Release Date: July 1999 - 3 - Revision A2 PIN DESCRIPTION P0.0−P0.7 Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O
W78C32C - 4 - PSEN Program Store Enable Output, active low. PSEN enables the external ROM onto the Port 0 address/data bus during fetch and MOVC oper
W78C32C Publication Release Date: July 1999 - 5 - Revision A2 FUNCTIONAL DESCRIPTION The W78C32C architecture consists of a core controller surr
W78C32C - 6 - Reset The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the osci
W78C32C Publication Release Date: July 1999 - 7 - Revision A2 DC Characteristics, continued PARAMETER SYM. TEST CONDITIONS SPECIFICATION UNIT
W78C32C - 8 - Program Fetch Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES Address Valid to ALE Low TAAS 1 TCP-∆ - - nS 4 Address Hold af
W78C32C Publication Release Date: July 1999 - 9 - Revision A2 Port Access Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT Port Input Setup to ALE
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