Features• Single 2.3V - 3.6V or 2.7V - 3.6V Supply• Serial Peripheral Interface (SPI) Compatible– Supports SPI Modes 0 and 3• 70 MHz Maximum Clock Fre
103668E–DFLASH–11/2012AT25DF041AThe Byte/Page Program mode is the default programming mode after the device powers-up orresumes from a device reset.Fi
113668E–DFLASH–11/2012AT25DF041Adevice. Deasserting the CS pin will start the internally self-timed program operation, and the byteof data will be pro
123668E–DFLASH–11/2012AT25DF041AFigure 8-3. Sequential Program Mode – Status Register PollingFigure 8-4. Sequential Program Mode – Waiting Maximum Byt
133668E–DFLASH–11/2012AT25DF041AIf the address specified by A23 - A0 points to a memory location within a sector that is in the pro-tected state, then
143668E–DFLASH–11/2012AT25DF041A8.4 Chip EraseThe entire memory array can be erased in a single operation by using the Chip Erase command.Before a Chi
153668E–DFLASH–11/2012AT25DF041A9. Protection Commands and Features9.1 Write EnableThe Write Enable command is used to set the Write Enable Latch (WEL
163668E–DFLASH–11/2012AT25DF041AFigure 9-2. Write Disable9.3 Protect SectorEvery physical sector of the device has a corresponding single-bit Sector P
173668E–DFLASH–11/2012AT25DF041AFigure 9-3. Protect Sector9.4 Unprotect SectorIssuing the Unprotect Sector command to a particular sector address will
183668E–DFLASH–11/2012AT25DF041A9.5 Global Protect/UnprotectThe Global Protect and Global Unprotect features can work in conjunction with the Protect
193668E–DFLASH–11/2012AT25DF041AEssentially, if the SPRL bit of the Status Register is in the logical “0” state (Sector ProtectionRegisters are not lo
23668E–DFLASH–11/2012AT25DF041AThe physical sectoring and the erase block sizes of the AT25DF041A have been optimized tomeet the needs of today’s code
203668E–DFLASH–11/2012AT25DF041AIf the desire is to only change the SPRL bit without performing a Global Protect or Global Unpro-tect, then the system
213668E–DFLASH–11/2012AT25DF041A9.7 Protected States and the Write Protect (WP) PinThe WP pin is not linked to the memory array itself and has no dire
223668E–DFLASH–11/2012AT25DF041ATable 9-5. Hardware and Software LockingWP SPRL Locking SPRL Change Allowed Sector Protection Registers0 0 Can be modi
233668E–DFLASH–11/2012AT25DF041A10. Status Register Commands10.1 Read Status RegisterThe Status Register can be read to determine the device's re
243668E–DFLASH–11/2012AT25DF041A10.1.1 SPRL BitThe SPRL bit is used to control whether the Sector Protection Registers can be modified or not.When the
253668E–DFLASH–11/2012AT25DF041A10.1.6 WEL BitThe WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit isin the l
263668E–DFLASH–11/2012AT25DF041A10.2 Write Status RegisterThe Write Status Register command is used to modify the SPRL bit of the Status Registerand/o
273668E–DFLASH–11/2012AT25DF041A11. Other Commands and Functions11.1 Read Manufacturer and Device IDIdentification information can be read from the de
283668E–DFLASH–11/2012AT25DF041AFigure 11-1. Read Manufacturer and Device ID11.2 Deep Power-downDuring normal operation, the device will be placed in
293668E–DFLASH–11/2012AT25DF041AFigure 11-2. Deep Power-down11.3 Resume from Deep Power-downIn order exit the Deep Power-down mode and resume normal d
33668E–DFLASH–11/2012AT25DF041A2. Pin Descriptions and PinoutsTable 2-1. Pin DescriptionsSymbol Name and FunctionAssertedState TypeCSCHIP SELECT: Asse
303668E–DFLASH–11/2012AT25DF041A11.4 HoldThe HOLD pin is used to pause the serial communication with the device without having to stopor reset the clo
313668E–DFLASH–11/2012AT25DF041A12. Electrical Specifications12.1 Absolute Maximum Ratings*Temperature under Bias ... -55
323668E–DFLASH–11/2012AT25DF041ANotes: 1. Not 100% tested (value guaranteed by design and characterization).2. 15 pF load at 70 MHz, 30 pF load at 66
333668E–DFLASH–11/2012AT25DF041ANote: 1. Maximum values indicate worst-case performance after 100,000 erase/program cycles.2. Not 100% tested (value g
343668E–DFLASH–11/2012AT25DF041A13. WaveformsFigure 13-1. Serial Input TimingFigure 13-2. Serial Output TimingFigure 13-3.HOLD Timing – Serial InputCS
353668E–DFLASH–11/2012AT25DF041AFigure 13-4. HOLD Timing – Serial OutputFigure 13-5. WP Timing for Write Status Register Command When SPRL = 1CSSISCKS
363668E–DFLASH–11/2012AT25DF041A14. Ordering Information14.1 Ordering Code DetailNote: The shipping carrier option code is not marked on the devices.A
373668E–DFLASH–11/2012AT25DF041A15. Packaging Information15.1 8MA1 – UDFNTITLEDRAWING NO.GPCREV. Package Drawing Contact: [email protected]
383668E–DFLASH–11/2012AT25DF041A15.2 8S1 – JEDEC SOICDRAWING NO. REV. TITLE GPCCOMMON DIMENSIONS(Unit of Measure = mm)SYMBOLMINNOMMAXNOTE A1 0.10 –
393668E–DFLASH–11/2012AT25DF041A15.3 8S2 – EIAJ SOICTITLEDRAWING NO. GPCREV. Package Drawing Contact: [email protected] STN F 8S2, 8-lea
43668E–DFLASH–11/2012AT25DF041A3. Block Diagram4. Memory ArrayTo provide the greatest flexibility, the memory array of the AT25DF041A can be erased in
403668E–DFLASH–11/2012AT25DF041A16. Revision HistoryRevision Level – Release Date HistoryA – March 2007 Initial release.B – November 2007Changed part
Corporate OfficeCalifornia | USAAdesto Headquarters1250 Borregas AvenueSunnyvale, CA 94089 Phone: (+1) 408.400.0578Email: [email protected]© 2012
53668E–DFLASH–11/2012AT25DF041AFigure 4-1. Memory Architecture Diagram4KB07FFFFh – 07F000h256 Bytes07FFFFh – 07FF00h4KB07EFFFh – 07E000h256 Bytes07FEF
63668E–DFLASH–11/2012AT25DF041A5. Device OperationThe AT25DF041A is controlled by a set of instructions that are sent from a host controller, com-monl
73668E–DFLASH–11/2012AT25DF041ANote: 1. Three address bytes are only required for the first operation to designate the address to start programming at
83668E–DFLASH–11/2012AT25DF041A7. Read Commands7.1 Read ArrayThe Read Array command can be used to sequentially read a continuous stream of data fromt
93668E–DFLASH–11/2012AT25DF041A8. Program and Erase Commands8.1 Byte/Page ProgramThe Byte/Page Program command allows anywhere from a single byte of d
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