Rainbow-electronics BR24L64FJ-W User Manual

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs1/258k×8 bit electrically erasable PROMBR24L64-W / BR24L64F-W / BR24L64FJ-WThe BR

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs10/25zByte writeSDALINEWPSTARTSLAVEADDRESS10 01R/WWRITEACKACKD7DATAD0STOPFig.8 B

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs11/25zCurrent readSDALINESTARTSLAVEADDRESS11R/WACKACKDATASTOP00A2 A1 A0D7 D0READF

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs12/25zSequential readSTARTSLAVEADDRESSR/WACKACKACKACKREADDATA(n)DATA(n+x)SDALINE1

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs13/25zApplication1) WP effective timing WP is fixed to “H” or “L” usually. But

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs14/252) Software reset Please execute software reset in case that the device i

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs15/253) Acknowledge polling Since the device ignore all input commands during

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs16/254) Command cancellation by start and stop condition During a command inpu

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs17/255) Notes for power supply VCC rises through the low voltage region in which

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs18/25 • LVCC circuit LVCC circuit inhibit write operation at low voltage, and p

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs19/25 • The minimum value RPU The minimum value of RPU is determined by followi

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs2/25zRecommended operating conditionsParameter Symbol Limits UnitSupply voltageVI

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs20/258) Notes for noise on VCC • About bypass capacitor Noise and surges on

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs21/25 • The maximum value of RS The maximum value of RS is determined by follow

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs22/2510) The special character DATA The following characteristic data are ty

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs23/2520.60.50.40.30.20.1001 34 65CURRENT CONSUMPTION AT READING : ICC2 (mA)Fig.

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs24/2523001002000−100−20001 34 65INPUT DATA SET UP TIME : tSU:DAT (ns)Fig.35

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs25/2520.60.30.40.50.20.1001 34 65NOISE REDUCTION EFFECTIVE TIME : tI (SCL H) (

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs3/25zDimensionFig.1(a) PHYSICAL DIMENSION (Units : mm) DIP8 (BR24L64-W) 0.5±0.1

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs4/25zBlock diagram1A0A1 2A2 3GND 4VCC8WP76 SCLSDA564kbit EEPROM arrayControl logi

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs5/25zAC operating characteristics (Unless otherwise specified Ta=−40 to 85°C, VCC

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs6/25zSynchronous data timingtBUFtPDtHIGH tHD : STA tLOWtFtRSCLSTART BIT STOP BITS

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs7/25zWP timingSCLSDAWPtHD : WPtWRSTOP BITACKACKD1DATA (n)DATA (1)tSU : WPD0Fig.6(

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs8/25zDevice operation1) Start condition (Recognition of start bit) • All commands

BR24L64-W / BR24L64F-W / BE24L64FJ-WMemory ICs9/256) Acknowledge • Acknowledge is a software convention used to indicate succes