Rainbow-electronics AT25040A User Manual

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1
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
Medium-voltage and Standard-voltage Operation
5.0 (V
CC
= 4.5V to 5.5V)
2.7 (V
CC
= 2.7V to 5.5V)
3.0 MHz Clock Rate (5V)
8-byte Page Mode
Block Write Protection
Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
Self-timed Write Cycle (10 ms max)
High Reliability
Endurance: One Million Write Cycles
Data Retention: 100 Years
8-pin PDIP and 8-lead JEDEC SOIC Package
Description
The AT25010A/020A/040A provides 1024/2048/4096 bits of serial electrically eras-
able programmable read only memory (EEPROM) organized as 128/256/512 words of
8 bits each. The device is optimized for use in many automotive applications where
low-power and low voltage operation are essential. The AT25010A/020A/040A is avail-
able in space saving 8-pin PDIP and 8-lead JEDEC SOIC packages.
The AT25010A/020A/040A is enabled through the Chip Select pin (CS
) and accessed
via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate ERASE cycle is required before WRITE.
BLOCK WRITE protection is enabled by programming the status register with one of
four blocks of write protection. Separate program enable and program disable instruc-
tions are provided for additional data protection. Hardware data protection is provided
via the WP
pin to protect against inadvertent write attempts. The HOLD pin may be
used to suspend any serial communication without resetting the serial sequence.
SPI Serial
Automotive
EEPROMs
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
AT25010A
AT25020A
AT25040A
Preliminary
SPI, 1K Serial
E
2
PROM
Pin Configurations
Pin Name Function
CS
Chip Select
SCK Serial Data Clock
SI Serial Data Input
SO Serial Data Output
GND Ground
VCC Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
8-pin PDIP
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
8-lead SOIC
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
Rev. 3402A–SEEPR–10/3/03
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1 2 3 4 5 6 ... 17 18

Summary of Contents

Page 1 - Pin Configurations

1Features• Serial Peripheral Interface (SPI) Compatible• Supports SPI Modes 0 (0,0) and 3 (1,1)• Medium-voltage and Standard-voltage Operation– 5.0 (V

Page 2 - Absolute Maximum Ratings*

10AT25010A/020A/040A [Preliminary]3402A–SEEPR–10/3/03Timing DiagramsSynchronous Data Timing (for mode 0)WREN Timing WRDI Timing SOVOHVOLHI-ZHI-ZtVVA

Page 3 - DC Characteristics

11AT25010A/020A/040A [Preliminary]3402A–SEEPR–10/3/03RDSR Timing WRSR Timing READ Timing CSSCK01234567891011121314SIINSTRUCTIONSO76543210DATA OUTMS

Page 4 - AC Characteristics

12AT25010A/020A/040A [Preliminary]3402A–SEEPR–10/3/03WRITE Timing HOLD Timing CSSCK01234567891011121314SIINSTRUCTIONSO76543210DATA INHIGH IMPEDANCE1

Page 5 - Serial Interface

13AT25010A/020A/040A [Preliminary]3402A–SEEPR–10/3/03 AT25010A Ordering InformationOrdering Code Package Operation RangeAT25010A-10PA-5.0CAT25010AN-10

Page 6 - SPI Serial Interface

14AT25010A/020A/040A [Preliminary]3402A–SEEPR–10/3/03 AT25020A Ordering InformationOrdering Code Package Operation RangeAT25020A-10PA-5.0CAT25020AN-10

Page 7 - Functional

15AT25010A/020A/040A [Preliminary]3402A–SEEPR–10/3/03 AT25040A Ordering InformationOrdering Code Package Operation RangeAT25040A-10PA-5.0CAT25040AN-1

Page 8 - 3402A–SEEPR–10/3/03

16AT25010A/020A/040A [Preliminary]3402A–SEEPR–10/3/03Packaging Information8P3 – PDIP 2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 8P

Page 9

17AT25010A/020A/040A [Preliminary]3402A–SEEPR–10/3/038S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd.Colorado Springs, CO 80906TITLEDRAWING NO.RREV. Not

Page 10 - Timing Diagrams

Printed on recycled paper.3402A–SEEPR–10/3/03 xMDisclaimer: Atmel Corporation makes no warranty for the use of its products, other than those express

Page 11 - READ Timing

2AT25010A/020A/040A [Preliminary]3402A–SEEPR–10/3/03Block Diagram Absolute Maximum Ratings*Operating Temperature... -55

Page 12 - HOLD Timing

3AT25010A/020A/040A [Preliminary]3402A–SEEPR–10/3/03Note: 1. This parameter is characterized and is not 100% tested.Notes: 1. This parameter is prelim

Page 13 - AT25010A Ordering Information

4AT25010A/020A/040A [Preliminary]3402A–SEEPR–10/3/03Note: 1. This parameter is characterized and is not 100% tested.AC Characteristics Applicable over

Page 14 - AT25020A Ordering Information

5AT25010A/020A/040A [Preliminary]3402A–SEEPR–10/3/03Serial Interface DescriptionMASTER: The device that generates the serial clock.SLAVE: Because the

Page 15 - AT25040A Ordering Information

6AT25010A/020A/040A [Preliminary]3402A–SEEPR–10/3/03SPI Serial Interface AT25010A/020A/040A

Page 16 - End View

7AT25010A/020A/040A [Preliminary]3402A–SEEPR–10/3/03Functional DescriptionThe AT25010A/020A/040A is designed to interface directly with the synchronou

Page 17

8AT25010A/020A/040A [Preliminary]3402A–SEEPR–10/3/03WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user toselect one of four levels of

Page 18 - Regional Headquarters

9AT25010A/020A/040A [Preliminary]3402A–SEEPR–10/3/03The AT25010A/020A/040A is capable of an 8-byte PAGE WRITE operation. After eachbyte of data is rec

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