Rainbow-electronics AT93C46C User Manual download pdf

Features

• Low-Voltage and Standard-Voltage Operation

–2.7(V

=2.7Vto5.5V)

–2.5(V

=2.5Vto5.5V)

• 3-Wire Serial Interface

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• 2MHzClockRate(5V)

• Self-Timed Write Cycle (10 ms max)

• High Reliability

– Endurance: 1 Million Write Cycles

– Data Retention: 100 Years

• Automotive Grade and Extended Temperature Devices Available

• 8-lead PDIP and 8-lead JEDEC SOIC Packages

Description

The AT93C46C provides 1024 bits of serial electrically-erasable programmable read

only memory (EEPROM) organized as 64 words of 16 bits each. The device is opti-

mized for use in many industrial and commercial applications where low-power and

low-voltage operation are essential. The AT93C46C is available in space saving 8-

lead PDIP and 8-lead JEDEC SOIC packages.

TheAT93C46CisenabledthroughtheChipSelectpin(CS),andaccessedviaa3-

wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock

(SK). Upon receiving a READ instruction at DI, the address is decoded and the data is

clocked out serially on the data output pin DO. The WRITE cycle is completely self-

timed and no separate ERASE cycle is required before WRITE. The WRITE cycle is

only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is

brought “high” following the initiation of a WRITE cycle, the DO pin outputs the

READY/BUSY status of the part.

The AT93C46C is available in 2.7V to 5.5V and 2.5V to 5.5V versions.

Pin Configurations

Pin Name Function

CS Chip Select

SK Serial Data Clock

DI Serial Data Input

DO Serial Data Output

GND Ground

VCC Power Supply

NC No Connect

DC Don’t Connect

3-Wire

Serial EEPROM

1K (64 x 16)

AT93C46C

Rev. 1122D–SEEPR–08/02

8-lead PDIP

VCC

GND

8-lead SOIC

VCC

GND

1 2 3 4 5 6 ... 13 14

Summary of Contents

Page 1 - AT93C46C

1Features• Low-Voltage and Standard-Voltage Operation–2.7(VCC=2.7Vto5.5V)–2.5(VCC=2.5Vto5.5V)• 3-Wire Serial Interface• Schmitt Trigger, Filtered Inpu

Page 2

10AT93C46C1122D–SEEPR–08/02ERASE TimingERAL Timing(1)Note: 1. Valid only at VCC= 4.5V to 5.5V.SK1 1 ...1CSDI ANtCStSVtDFtWPAN-1AN-2A0CHECKSTATUSSTANDB

Page 3

11AT93C46C1122D–SEEPR–08/02Note: For 2.7V and 2.5V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC charact

Page 4

12AT93C46C1122D–SEEPR–08/02Packaging Information8P3 – PDIP2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 8P3, 8-lead, 0.300" Wide

Page 5

13AT93C46C1122D–SEEPR–08/028S1 – JEDEC SOIC 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. Note:10/10/018S1, 8-lead (0.150" Wid

Page 6

Printed on recycled paper.© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than those expressly contain

Page 7

2AT93C46C1122D–SEEPR–08/02Block DiagramAbsolute Maximum Ratings*Operating Temperature... -55°Cto+125°C*NOTICE: Stresses

Page 8

3AT93C46C1122D–SEEPR–08/02Note: 1. This parameter is characterized and is not 100% tested.Note: 1. VILmin and VIHmax are reference only and are not te

Page 9

4AT93C46C1122D–SEEPR–08/02Note: 1. This parameter is characterized and is not 100% tested.AC CharacteristicsApplicable over recommended operating rang

Page 10

5AT93C46C1122D–SEEPR–08/02FunctionalDescriptionThe AT93C46C is accessed via a simple and versatile three-wire serial communicationinterface. Device op

Page 11

6AT93C46C1122D–SEEPR–08/02ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in thememory array to the logic “1” state and is prima

Page 12

7AT93C46C1122D–SEEPR–08/02Timing DiagramsSynchronous Data TimingNote: This is the minimum SK period.

Page 13

8AT93C46C1122D–SEEPR–08/02READ TimingEWEN Timing(1)Note: 1. Requires a minimum of nine clock cycles.EWDS Timing(1)Note: 1. Requires a minimum of nine

Page 14 - 1122D–SEEPR–08/02 xM

9AT93C46C1122D–SEEPR–08/02WRITE TimingWRAL Timing(1)(2)Notes: 1. Valid only at VCC= 4.5V to 5.5V.2. Requires a minimum of nine clock cycles.SKCStCStWP

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