75
ATAR862-8
4589B–4BMCU–02/03
• In Transmit mode (SDD = 1) shifting starts only if the transmit buffer has been
loaded (SRDY = 1).
• Setting SIR-bit loads the contents of the shift register into the receive buffer
(synchronous 8-bit mode only).
• In MCL modes, writing a 0 to SIR generates a start condition and writing a 1
generates a stop condition.
Serial Interface Control
Register 2 (SIC2)
Auxiliary register address: "A"hex
Note: SDD controls port directional control and defines the reset function for the SRDY-flag
Bit 3Bit 2Bit 1Bit 0
MSM SM1 SM0 SDD Reset value: 1111b
MSM M
odular Stop Mode
MSM = 1, modulator stop mode disabled (output masking off)
MSM = 0, modulator stop mode enabled (output masking on) - used in
modulation modes for generating bit streams which are not sub–multiples of 8
bits.
SM1 Serial Mode control bit 1
SM0 S
erial Mode control bit 0
Mode SM1 SM0 SSI Mode
1 1 1 8-bit NRZ-Data changes with the rising edge of SC
2 1 0 8-bit NRZ-Data changes with the falling edge of SC
3 0 1 9-bit two-wire MCL mode
4 0 0 8-bit two-wire MCL mode (no acknowledge)
SDD Serial Data Direction
SDD = 1, transmit mode – SD line used as output (transmit data). SRDY is set
by a transmit buffer write access.
SDD = 0, receive mode – SD line used as input (receive data). SRDY is set
by a receive buffer read access
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