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Rainbow-electronics DS3131 User Manual Page 48
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DS3131
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Figure 6-1. Lay
er 1 Port Interfac
e Block Diagram
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DS3131 BoSS
1
40-Port, Unchannelized
1
TABLE OF CONTENTS
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LIST OF FIGURES
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LIST OF TABLES
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1. MAIN FEATURES
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2. DETAILED DESCRIPTION
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Figure 2-1. Block Diagram
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Table 2-A. Restrictions
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3. SIGNAL DESCRIPTION
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3.1 Overview/Signal List
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Signal Naming Convention
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Figure 3-1. Signal Floorplan
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3.4 JTAG Signal Description
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3.6 PCI Extension Signals
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4. MEMORY MAP
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4.1 Introduction
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4.7 BERT Registers (5xx)
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4.10 FIFO Registers (9xx)
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5.3 Status and Interrupt
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at the PCI bus
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0 = interrupt masked
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6. LAYER 1
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6.1 General Description
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6.3 BERT
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Figure 6-2. BERT Mux Diagram
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7. HDLC
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7.1 General Description
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7.2 HDLC Operation
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8. FIFO
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Figure 8-1. FIFO Example
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8.1.1 Receive High Watermark
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8.1.2 Transmit Low Watermark
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9.1 Introduction
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9.2 Receive Side
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9.2.1 Overview
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9.2.2 Packet Descriptors
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9.2.3 Free Queue
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Calculation
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9.2.4 Done Queue
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9.2.5 DMA Configuration RAM
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9.3 Transmit Side
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9.3.1 Overview
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9.3.2 Packet Descriptors
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9.3.3 Pending Queue
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9.3.4 Done Queue
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9.3.5 DMA Configuration RAM
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10. PCI BUS
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10.1.1 PCI Read Cycle
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Figure 10-2. PCI Bus Read
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10.1.2 PCI Write Cycle
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Figure 10-3. PCI Bus Write
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10.1.3 PCI Bus Arbitration
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10.1.4 PCI Initiator Abort
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10.1.5 PCI Target Retry
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10.1.7 PCI Target Abort
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10.2.1 Command Bits (PCMD0)
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10.2.2 Status Bits (PCMD0)
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10.2.3 Command Bits (PCMD1)
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10.2.4 Status Bits (PCMD1)
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Register Name: PLTH1
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PF TYPE1 TYPE0 MSI
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11. LOCAL BUS
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11.1 General Description
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DS3131 BOSS
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11.1.1 PCI Bridge Mode
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Setting
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11.1.2 Configuration Mode
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Intel Mode (LIM = 0)
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LRDYLRDY
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LRDY (LRDY = 0000)
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Motorola Mode (LIM = 1)
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12. JTAG
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12.1 JTAG Description
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Figure 12-1. Block Diagram
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12.4 Test Registers
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13. AC CHARACTERISTICS
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ABSOLUTE MAXIMUM RATINGS
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DC CHARACTERISTICS
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(continued)
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14. MECHANICAL DIMENSIONS
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14.1 272 PBGA Package
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15. APPLICATIONS
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15.3 ONET/SDH Applications
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