Rainbow-electronics DS3131 User Manual Page 52
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DS3131
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6.4 BERT Register Description
Figure 6-3. BERT Register Set
BERTC0: BERT Control 0 LSB
reserved TINV RINV PS2 PS1 PS0 LC RESYNC
MSB
IESYNC IEBED IEOF reserved RPL3 RPL2 RPL1 RPL0
BERTC1: BERT Control 1 LSB
EIB2 EIB1 EIB0 SBE reserved reserved reserved TC
MSB
Alternating Word Count
BERTRP0: BERT Repetitive Pattern Set 0 (lower word) LSB
BERT Repetitive Pattern Set (lower byte)
MSB
BERT Repetitive Pattern Set
BERTRP1: BERT Repetitive Pattern Set 1 (upper word) LSB
BERT Repetitive Pattern Set
MSB
BERT Repetitive Pattern Set (upper byte)
BERTBC0: BERT Bit Counter 0 (lower word) LSB
BERT 32-Bit Bit Counter (lower byte)
MSB
BERT 32-Bit Bit Counter
BERTBC1: BERT Bit Counter 0 (upper word) LSB
BERT 32-Bit Bit Counter
MSB
BERT 32-Bit Bit Counter (upper byte)
BERTEC0: BERT Error Counter 0/Status LSB
reserved RA1 RA0 RLOS BED BBCO BECO SYNC
MSB
BERT 24-Bit Error Counter (lower byte)
BERTEC1: BERT Error Counter 1 (upper word) LSB
BERT 24-Bit Error Counter
MSB
BERT 24-Bit Error Counter (upper byte)
- DS3131 BoSS 1
- 40-Port, Unchannelized 1
- TABLE OF CONTENTS 2
- 3 of 174 3
- LIST OF FIGURES 4
- LIST OF TABLES 5
- 1. MAIN FEATURES 6
- 2. DETAILED DESCRIPTION 7
- 8 of 174 8
- 9 of 174 9
- Figure 2-1. Block Diagram 10
- 11 of 174 11
- Table 2-A. Restrictions 12
- 13 of 174 13
- 3. SIGNAL DESCRIPTION 14
- 3.1 Overview/Signal List 14
- Signal Naming Convention 14
- Figure 3-1. Signal Floorplan 19
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- 22 of 174 22
- 3.4 JTAG Signal Description 23
- 24 of 174 24
- 25 of 174 25
- 3.6 PCI Extension Signals 26
- 27 of 174 27
- 4. MEMORY MAP 28
- 4.1 Introduction 28
- 29 of 174 29
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- 31 of 174 31
- 32 of 174 32
- 4.7 BERT Registers (5xx) 33
- 4.10 FIFO Registers (9xx) 34
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- 5.3 Status and Interrupt 39
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- at the PCI bus 43
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- 0 = interrupt masked 45
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- 6. LAYER 1 47
- 6.1 General Description 47
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- 50 of 174 50
- 6.3 BERT 51
- Figure 6-2. BERT Mux Diagram 51
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- 7. HDLC 59
- 7.1 General Description 59
- 7.2 HDLC Operation 59
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- 63 of 174 63
- 64 of 174 64
- 8. FIFO 65
- Figure 8-1. FIFO Example 66
- 8.1.1 Receive High Watermark 67
- 8.1.2 Transmit Low Watermark 67
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- 73 of 174 73
- 9.1 Introduction 74
- 75 of 174 75
- 9.2 Receive Side 76
- 9.2.1 Overview 76
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- 79 of 174 79
- 9.2.2 Packet Descriptors 80
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- 9.2.3 Free Queue 82
- Calculation 83
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- 9.2.4 Done Queue 87
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- 9.2.5 DMA Configuration RAM 93
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- 9.3 Transmit Side 97
- 9.3.1 Overview 97
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- 9.3.2 Packet Descriptors 105
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- 9.3.3 Pending Queue 107
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- 9.3.4 Done Queue 111
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- 9.3.5 DMA Configuration RAM 116
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- 10. PCI BUS 121
- 10.1.1 PCI Read Cycle 122
- Figure 10-2. PCI Bus Read 122
- 10.1.2 PCI Write Cycle 123
- Figure 10-3. PCI Bus Write 123
- 10.1.3 PCI Bus Arbitration 124
- 10.1.4 PCI Initiator Abort 124
- 10.1.5 PCI Target Retry 125
- 10.1.7 PCI Target Abort 126
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- 128 of 174 128
- 10.2.1 Command Bits (PCMD0) 129
- 10.2.2 Status Bits (PCMD0) 130
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- 132 of 174 132
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- 10.2.3 Command Bits (PCMD1) 134
- 10.2.4 Status Bits (PCMD1) 135
- Register Name: PLTH1 136
- PF TYPE1 TYPE0 MSI 137
- 11. LOCAL BUS 138
- 11.1 General Description 138
- DS3131 BOSS 139
- 11.1.1 PCI Bridge Mode 141
- Setting 141
- 11.1.2 Configuration Mode 143
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- Intel Mode (LIM = 0) 149
- LRDYLRDY 149
- LRDY (LRDY = 0000) 149
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- Motorola Mode (LIM = 1) 154
- 12. JTAG 155
- 12.1 JTAG Description 155
- Figure 12-1. Block Diagram 155
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- 12.4 Test Registers 160
- 13. AC CHARACTERISTICS 161
- ABSOLUTE MAXIMUM RATINGS 161
- DC CHARACTERISTICS 161
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- (continued) 166
- 14. MECHANICAL DIMENSIONS 169
- 14.1 272 PBGA Package 169
- 15. APPLICATIONS 170
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- 172 of 174 172
- 173 of 174 173
- 15.3 ONET/SDH Applications 174
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