Rainbow-electronics ADC08D1000 User Manual

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ADC08D1000
High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D
Converter
General Description
NOTE: This product is currently in development. ALL
specifications are design targets and are subject to
change.
The ADC08D1000 is a dual, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 1.3 GSPS. Consuming
a typical 1.6 Watts at 1 GSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and
interpolating architecture, the fully differential comparator
design, the innovative design of the internal sample-and-
hold amplifier and the self-calibration scheme enable a very
flat response of all dynamic parameters beyond Nyquist,
producing a high 7.5 ENOB with a 500 MHz input signal and
a 1 GHz sample rate while providing a 10
-18
B.E.R. Output
formatting is offset binary and the LVDS digital outputs are
compliant with IEEE 1596.3-1996, with the exception of a
reduced common mode voltage of 0.8V.
Each converter has a 1:2 demultiplexer that feeds two LVDS
buses and reduces the output data rate on each bus to half
the sampling rate. The two converters can be interleaved
and used as a single 2 GSPS ADC.
The converter typically consumes less than 20 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the indus-
trial (-40˚C T
A
+85˚C) temperature range.
Features
n Internal Sample-and-Hold
n Single +1.9V
±
0.1V Operation
n Choice of SDR or DDR output clocking
n Interleave Mode for 2x Sampling Rate
n Multiple ADC Synchronization Capability
n Guaranteed No Missing Codes
n Serial Interface for Extended Control
n Fine Adjustment of Input Full-Scale Range and Offset
n Duty Cycle Corrected Sample Clock
Key Specifications
n Resolution 8 Bits
n Max Conversion Rate 1 GSPS (min)
n Bit Error Rate 10
-18
(typ)
n ENOB
@
500 MHz Input 7.5 Bits (typ)
n DNL
±
0.25 LSB (typ)
n Power Consumption
Operating 1.6 W (typ)
Power Down Mode 20 mW (typ)
Applications
n Direct RF Down Conversion
n Digital Oscilloscopes
n Satellite Set-top boxes
n Communications Systems
n Test Instrumentation
Block Diagram
20097453
ADVANCE INFORMATION
January 2005
High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter
© 2005 National Semiconductor Corporation DS200974 www.national.com
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Summary of Contents

Page 1 - Converter

ADC08D1000High Performance, Low Power, Dual 8-Bit, 1 GSPS A/DConverterGeneral DescriptionNOTE: This product is currently in development. – ALLspecific

Page 2 - Pin Configuration

Converter Electrical Characteristics (Continued)[Note: This product is currently in development. As such, the parameters specified in this section are

Page 3

Converter Electrical Characteristics (Continued)[Note: This product is currently in development. As such, the parameters specified in this section are

Page 4

Converter Electrical Characteristics (Continued)20097404Note 7: To guarantee accuracy, it is required that VAand VDRbe well bypassed. Each supply pin

Page 5

Specification DefinitionsAPERTURE (SAMPLING) DELAY is that time required afterthe fall of the clock input for the sampling switch to open. TheSample/H

Page 6

Specification Definitions (Continued)SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed indB, of the rms value of the input signal at the output to t

Page 7 - Package Thermal Resistance

Timing Diagrams20097414FIGURE 3. ADC08D1000 Timing — SDR Clocking20097415FIGURE 4. ADC08D1000 Timing — DDR ClockingADC08D1000www.national.com15

Page 8

Timing Diagrams (Continued)20097419FIGURE 5. Serial Interface Timing20097420FIGURE 6. Clock Reset Timing in DDR Mode20097423FIGURE 7. Clock Reset Timi

Page 9

Timing Diagrams (Continued)20097424FIGURE 8. Clock Reset Timing in SDR Mode with OUTEDGE High20097425FIGURE 9. Self Calibration and On-Command Calibra

Page 10

1.0 Functional DescriptionThe ADC08D1000 is a versatile A/D Converter with an inno-vative architecture permitting very high speed operation. Thecontro

Page 11

1.0 Functional Description (Continued)controls are disabled. These pins are OutV (pin 3), OutEdge/DDR (pin 4), FSR (pin 14) and CalDly/DES (pin 127).

Page 12

Ordering InformationExtended Commercial TemperatureRange (-40˚C<TA<+85˚C)NS PackageADC08D1000CIYB 128-Pin Exposed Pad LQFPADC08D1000EVAL Evaluat

Page 13 - Specification Definitions

1.0 Functional Description (Continued)1.1.6 The LVDS OutputsThe data outputs, the Out Of Range (OR) and DCLK, areLVDS. Output current sources provide

Page 14 - Transfer Characteristic

1.0 Functional Description (Continued)The default state of the Extended Control Mode is set uponpower-on reset (internally performed by the device) an

Page 15 - Timing Diagrams

1.0 Functional Description (Continued)Bit 10 nDE: DDR Enable. When this bit is set to 0b,data bus clocking follows the DDR (DualData Rate) mode whereb

Page 16 - Timing Diagrams (Continued)

1.0 Functional Description (Continued)Q-Channel Full-Scale Voltage AdjustAddr: Bh (1011b) W only (0x807F)D15 D14 D13 D12 D11 D10 D9 D8(MSB) Adjust Val

Page 17

1.0 Functional Description (Continued)DES Fine AdjustAddr: Fh (1111b) W only (0x007F)D15 D14 D13 D12 D11 D10 D9 D8(MSB) FAMD7 D6 D5 D4 D3 D2 D1 D0(LSB

Page 18 - 1.0 Functional Description

2.0 Applications Information(Continued)reduced to 75% of the values indicated. In the EnhancedControl Mode, these values will be determined by the ful

Page 19

2.0 Applications Information(Continued)2.2.2 Out Of Range (OR) IndicationWhen the conversion result is clipped the Out of Rangeoutput is activated suc

Page 20

2.0 Applications Information(Continued)The calibration process will be not be performed if the CALpin is high at power up. In this case, the calibrati

Page 21

2.0 Applications Information(Continued)2.4.6 Power Down FeatureThe Power Down pins (PD and PDQ) allow theADC08D1000 to be entirely powered down (PD) o

Page 22

2.0 Applications Information(Continued)power down current because not all of the ADC is powereddown. The device current will be normal after the input

Page 23

Pin Descriptions and Equivalent CircuitsPin FunctionsPin No. Symbol Equivalent Circuit Description3 OutV / SCLKOutput Voltage Amplitude and Serial Int

Page 24 - 2.0 Applications Information

2.0 Applications Information(Continued)ADC08D1000. Any external component (e.g., a filter capaci-tor) connected between the converter’s input and grou

Page 25

2.0 Applications Information(Continued)Failure to provide adequate heat removal. As described inSection 2.6.2, it is important to provide adequate hea

Page 26

Physical Dimensions inches (millimeters) unless otherwise notedNOTES: UNLESS OTHERWISE SPECIFIEDREFERENCE JEDEC REGISTRATION MS-026, VARIATION BFB.128

Page 27

Pin Descriptions and Equivalent Circuits (Continued)Pin FunctionsPin No. Symbol Equivalent Circuit Description1819CLK+CLK-LVDS Clock input pins for th

Page 28

Pin Descriptions and Equivalent Circuits (Continued)Pin FunctionsPin No. Symbol Equivalent Circuit Description83/7884/7785/7686/7589/7290/7191/7092/69

Page 29

Pin Descriptions and Equivalent Circuits (Continued)Pin FunctionsPin No. Symbol Equivalent Circuit Description40, 51,62, 73,88, 99,110, 121VDROutput D

Page 30

Absolute Maximum Ratings(Notes 1, 2)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distri

Page 31

Converter Electrical Characteristics (Continued)[Note: This product is currently in development. As such, the parameters specified in this section are

Page 32 - NS Package Number VNX128A

Converter Electrical Characteristics (Continued)[Note: This product is currently in development. As such, the parameters specified in this section are

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