Rainbow-electronics ATmega128L User Manual

1Features• High-performance, Low-power AVR® 8-bit Microcontroller• Advanced RISC Architecture– 133 Powerful Instructions – Most Single Clock Cycle Exe

10ATmega128(L)2467B–09/01• Bit 7 - I: Global Interrupt EnableThe global interrupt enable bit must be set for the interrupts to be enabled. The individ

100ATmega128(L)2467B–09/01Note: 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, thecompare match is ignored, but the set

101ATmega128(L)2467B–09/01Asynchronous Operation of the Timer/CounterAsynchronous Status Register – ASSR• Bit 3 - AS0: Asynchronous Timer/Counter0When

102ATmega128(L)2467B–09/01• The oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock to the TOSC1 pin may resul

103ATmega128(L)2467B–09/01read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after wakin

104ATmega128(L)2467B–09/01Timer/Counter Prescaler Figure 44. Prescaler for Timer/Counter0The clock source for Timer/Counter0 is named clkT0S. clkT0S

105ATmega128(L)2467B–09/01• Bit 1 - PSR0: Prescaler Reset Timer/Counter0When this bit is written to one, the Timer/Counter0 prescaler will be reset. T

106ATmega128(L)2467B–09/0116-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)The 16-bit Timer/Counter unit allows accurate program execution timi

107ATmega128(L)2467B–09/01Figure 45. 16-bit Timer/Counter Block DiagramNote: Refer to Figure 1 on page 2, Table 30 on page 69, and Table 39 on page

108ATmega128(L)2467B–09/01The double buffered Output Compare Registers (OCRnA/B/C) are compared with theTimer/Counter value at all time. The result of

109ATmega128(L)2467B–09/01• WGMn3 is added to TCCRnB.Interrupt flag and mask bits for output compare unit C are added.The 16-bit Timer/Counter has imp

11ATmega128(L)2467B–09/01Figure 4. AVR CPU General Purpose Working RegistersMost of the instructions operating on the Register file have direct acces

110ATmega128(L)2467B–09/01It is important to notice that accessing 16-bit registers are atomic operations. If an inter-rupt occurs between the two ins

111ATmega128(L)2467B–09/01The following code examples show how to do an atomic write of the TCNTn registercontents. Writing any of the OCRnA/B/C or IC

112ATmega128(L)2467B–09/01Figure 46. Counter Unit Block DiagramSignal description (internal signals):Count Increment or decrement TCNTn by 1.Directio

113ATmega128(L)2467B–09/01Input Capture Unit The Timer/Counter incorporates an input capture unit that can capture external eventsand give them a time

114ATmega128(L)2467B–09/01written to the ICRn register. When writing the ICRn register the high byte must be writtento the ICRnH I/O location before t

115ATmega128(L)2467B–09/01Output Compare Units The 16-bit comparator continuously compares TCNTn with the output compare register(OCRnx). If TCNT equa

116ATmega128(L)2467B–09/01sequence. The synchronization prevents the occurrence of odd-length, non-symmetricalPWM pulses, thereby making the output gl

117ATmega128(L)2467B–09/01internal OCnx register, not the OCnx pin. If a system reset occur, the OCnx register isreset to “0”.Figure 49. Compare Matc

118ATmega128(L)2467B–09/01inverted PWM). For non-PWM modes the COMnx1:0 bits control whether the outputshould be set, cleared or toggle at a compare m

119ATmega128(L)2467B–09/01counter is running with none or a low prescaler value must be done with care since theCTC mode does not have the double buff

12ATmega128(L)2467B–09/01Stack Pointer The stack is mainly used for storing temporary data, for storing local variables and forstoring return addresse

120ATmega128(L)2467B–09/01Figure 51. Fast PWM Mode, Timing DiagramThe Timer/Counter overflow flag (TOVn) is set each time the counter reaches TOP. In

121ATmega128(L)2467B–09/01setting (or clearing) the OCnx register at the compare match between OCRnx andTCNTn, and clearing (or setting) the OCnx regi

122ATmega128(L)2467B–09/01Figure 52. Phase Correct PWM Mode, Timing DiagramThe Timer/Counter overflow flag (TOVn) is set each time the counter reache

123ATmega128(L)2467B–09/01match between OCRnx and TCNTn when the counter decrements. The PWM frequencyfor the output when using phase correct PWM can

124ATmega128(L)2467B–09/01Figure 53. Phase and Frequency Correct PWM Mode, Timing DiagramThe Timer/Counter overflow flag (TOVn) is set at the same ti

125ATmega128(L)2467B–09/01decrements. The PWM frequency for the output when using phase and frequencycorrect PWM can be calculated by the following eq

126ATmega128(L)2467B–09/01Figure 55. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8)Figure 56 shows the count sequence cl

127ATmega128(L)2467B–09/01Figure 57. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)16-bit Timer/Counter Register DescriptionTimer/Counter

128ATmega128(L)2467B–09/01Table 59 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to thefast PWM modeNote: A special case occurs w

129ATmega128(L)2467B–09/01Note: A special case occurs when OCRnA/OCRnB/OCRnC equals TOP andCOMnA1/COMnB1//COMnC1 is set. See “Phase Correct PWM Mode”

13ATmega128(L)2467B–09/01Instruction Execution TimingThis section describes the general access timing concepts for instruction execution. TheAVR CPU i

130ATmega128(L)2467B–09/01Note: 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and

131ATmega128(L)2467B–09/01• Bit 6 - ICESn: Input Capture Edge SelectThis bit selects which edge on the Input Capture Pin (ICPn) that is used to trigge

132ATmega128(L)2467B–09/01Timer/Counter 3 Control Register C – TCCR3C• Bit 7- FOCnA: Force Output Compare for Channel A• Bit 6- FOCnB: Force Output Co

133ATmega128(L)2467B–09/01Output Compare Register 1 A – OCR1AH and OCR1ALOutput Compare Register 1 B – OCR1BH and OCR1BLOutput Compare Register 1 C –

134ATmega128(L)2467B–09/01Input Capture Register 1 – ICR1H and ICR1LInput Capture Register 3 – ICR3H and ICR3LThe input capture is updated with the co

135ATmega128(L)2467B–09/01Extended Timer/Counter Interrupt Mask Register – ETIMSKNote: This register is not available in ATmega103 compatibility mode.

136ATmega128(L)2467B–09/01Timer/Counter Interrupt Flag Register – TIFRNote: This register contains flag bits for several timer/counters, but only time

137ATmega128(L)2467B–09/01ICF3 is automatically cleared when the Input Capture 3 interrupt vector is executed.Alternatively, ICF3 can be cleared by wr

138ATmega128(L)2467B–09/01Timer/Counter3, Timer/Counter2, and Timer/Counter1 PrescalersTimer/Counter3, Timer/Counter1, and Timer/Counter0 share the sa

139ATmega128(L)2467B–09/01Each half period of the external clock applied must be longer than one system clockcycle to ensure correct sampling. The ext

14ATmega128(L)2467B–09/01When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interruptsare disabled. The user software can

140ATmega128(L)2467B–09/018-bit Timer/Counter2 with PWMTimer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. Themain featur

141ATmega128(L)2467B–09/01inactive when no clock source is selected. The output from the clock select logic isreferred to as the timer clock (clkT2).T

142ATmega128(L)2467B–09/01clear Clear TCNT2 (set all bits to zero).clkTnTimer/counter clock, referred to as clkT0 in the following.top Signalize that

143ATmega128(L)2467B–09/01Figure 62. Output Compare Unit, Block DiagramThe OCR2 register is double buffered when using any of the pulse width modulat

144ATmega128(L)2467B–09/01compare (FOC2) strobe bits in normal mode. The OC2 register keeps its value evenwhen changing between waveform generation mo

145ATmega128(L)2467B–09/01A change of the COM21:0 bits state will have effect at the first compare match after thebits are written. For non-PWM modes,

146ATmega128(L)2467B–09/01An interrupt can be generated each time the counter value reaches the TOP value byusing the OCF2 flag. If the interrupt is e

147ATmega128(L)2467B–09/01Figure 65. Fast PWM Mode, Timing DiagramThe Timer/Counter overflow flag (TOV2) is set each time the counter reaches Max If

148ATmega128(L)2467B–09/01cleared on the compare match between TCNT2 and OCR2 while upcounting, and set onthe compare match while downcounting. In inv

149ATmega128(L)2467B–09/01The N variable represents the prescale factor (1, 8, 64, 256, or 1024).The extreme values for the OCR2 register represent sp

15ATmega128(L)2467B–09/01Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is 4 clock cyclesminimum. After 4

150ATmega128(L)2467B–09/01Figure 69. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8)Figure 70 shows the setting of OCF2 an

151ATmega128(L)2467B–09/018-bit Timer/Counter Register DescriptionTimer/Counter Control Register – TCCR2• Bit 7 - FOC2: Force Output CompareThe FOC2 b

152ATmega128(L)2467B–09/01When OC2 is connected to the pin, the function of the COM21:0 bits depends on theWGM21:0 bit setting. Table 65 shows the COM

153ATmega128(L)2467B–09/01If external pin modes are used for the Timer/Counter2, transitions on the T2 pin willclock the counter even if the pin is co

154ATmega128(L)2467B–09/01• Bit 6- TOIE2: Timer/Counter2 Overflow Interrupt EnableWhen the TOIE2 bit is written to one, and the I-bit in the Status Re

155ATmega128(L)2467B–09/01Output Compare Modulator (OCM1C2)Overview The Output Compare Modulator (OCM) allows generation of waveforms modulated witha

156ATmega128(L)2467B–09/01When the modulator is enabled the type of modulation (logical AND or OR) can beselected by the PORTB7 register. Note that th

157ATmega128(L)2467B–09/01Serial Peripheral Interface – SPIThe Serial Peripheral Interface (SPI) allows high-speed synchronous data transferbetween th

158ATmega128(L)2467B–09/01When configured as a Master, the SPI interface has no automatic control of the SS line.This must be handled by user software

159ATmega128(L)2467B–09/01The following code examples show how to initialize the SPI as a master and how to per-form a simple transmission. DDR_SPI in

16ATmega128(L)2467B–09/01AVR ATmega128 MemoriesThis section describes the different memories in the ATmega128. The AVR architecturehas two main memory

160ATmega128(L)2467B–09/01The following code examples show how to initialize the SPI as a slave and how to per-form a simple reception.Note: 1. The ex

161ATmega128(L)2467B–09/01will immediately reset the send and receive logic, and drop any partially received data inthe shift register.Master Mode Whe

162ATmega128(L)2467B–09/01• Bit 3 - CPOL: Clock PolarityWhen this bit is written to one, SCK is high when idle. When CPOL is written to zero,SCK is lo

163ATmega128(L)2467B–09/01SPIF bit is cleared by first reading the SPI status register with SPIF set, then accessingthe SPI Data Register (SPDR).• Bit

164ATmega128(L)2467B–09/01Figure 76. SPI Transfer Format with CPHA = 0Figure 77. SPI Transfer Format with CPHA = 1Bit 1Bit 6LSBMSBSCK (CPOL = 0)mode

165ATmega128(L)2467B–09/01USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter(USART) is a highly flexible serial communic

166ATmega128(L)2467B–09/01Figure 78. USART Block DiagramNote: Refer to Figure 1 on page 2, Table 36 on page 73, and Table 39 on page 76 for USARTpin

167ATmega128(L)2467B–09/01• Transmit Buffer Functionality• Receiver OperationHowever, the receive buffering has two improvements that will affect the

168ATmega128(L)2467B–09/01xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.xcko Clock output to XCK pin (Internal Signa

169ATmega128(L)2467B–09/01External Clock External clocking is used by the synchronous slave modes of operation. The descriptionin this section refers

17ATmega128(L)2467B–09/01SRAM Data Memory The ATmega128 supports two different configurations for the SRAM data memory aslisted in Table 1.Figure 9 sh

170ATmega128(L)2467B–09/01plete frame is transmitted, it can be directly followed by a new frame, or thecommunication line can be set to an idle (high

171ATmega128(L)2467B–09/01that the TXC flag must be cleared before each transmission (before UDR is written) if itis used for this purpose.The followi

172ATmega128(L)2467B–09/01Sending Frames with 5 to 8 Data BitA data transmission is initiated by loading the transmit buffer with the data to be trans

173ATmega128(L)2467B–09/01Sending Frames with 9 Data BitIf 9 bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit inUCSRB

174ATmega128(L)2467B–09/01interrupt-driven data transmission is used, the data register empty Interrupt routine musteither write new data to UDR in or

175ATmega128(L)2467B–09/01The following code example shows a simple USART receive function based on pollingof the Receive Complete (RXC) flag. When us

176ATmega128(L)2467B–09/01Receiving Frames with 9 Data BitsIf 9 bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit inUCSRB

177ATmega128(L)2467B–09/01The receive function example reads all the I/O registers into the register file before anycomputation is done. This gives an

178ATmega128(L)2467B–09/01The UPE bit is set if the next character that can be read from the receive buffer had aparity error when received and the pa

179ATmega128(L)2467B–09/01Figure 82. Start Bit SamplingWhen the clock recovery logic detects a high (idle) to low (start) transition on the RxDline,

18ATmega128(L)2467B–09/01The five different addressing modes for the data memory cover: Direct, Indirect with Dis-placement, Indirect, Indirect with P

180ATmega128(L)2467B–09/01Figure 84. Stop Bit Sampling and Next Start Bit SamplingThe same majority voting is done to the stop bit as done for the ot

181ATmega128(L)2467B–09/01The recommendations of the maximum receiver baud rate error was made under theassumption that the receiver and transmitter e

182ATmega128(L)2467B–09/01frames. When the frame type bit (the first stop or the 9th bit) is one, the frame containsan address. When the frame type bi

183ATmega128(L)2467B–09/01location. Reading the UDR register location will return the contents of the receive databuffer register (RXB). For 5-, 6- or

184ATmega128(L)2467B–09/01• Bit 2 - UPE: Parity ErrorThis bit is set if the next character in the receive buffer had a Parity Error when receivedand t

185ATmega128(L)2467B–09/01• Bit 1 - RXB8: Receive Data Bit 8RXB8 is the 9th data bit of the received character when operating with serial frames with9

186ATmega128(L)2467B–09/01• Bit 2:1 - UCSZ1:0: Character SizeThe UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits(charac

187ATmega128(L)2467B–09/01Examples of Baud Rate SettingFor standard crystal and resonator frequencies, the most commonly used baud rates forasynchrono

188ATmega128(L)2467B–09/0128.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0%38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0%57.6k 3 0.0% 7 0.0%

189ATmega128(L)2467B–09/01Table 85. Examples of UBRR Settings for Commonly Used Oscillator Frequencies Baud Rate (bps)fosc = 16.0000 MHz fosc = 18.43

19ATmega128(L)2467B–09/01Figure 10. On-chip Data SRAM Access CyclesEEPROM Data Memory The ATmega128 contains 4K bytes of data EEPROM memory. It is or

190ATmega128(L)2467B–09/01Two-wire Serial InterfaceFeatures • Simple yet Powerful and Flexible Communication Interface, only Two Bus Lines Needed• Bot

191ATmega128(L)2467B–09/01allowing the pull-up resistors to pull the line high. Note that all AVR devices connected tothe TWI bus must be powered in o

192ATmega128(L)2467B–09/01Address Packet Format All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 addressbits, one READ/

193ATmega128(L)2467B–09/01Figure 89. Data Packet FormatCombining Address and Data Packets Into a TransmissionA transmission basically consists of a S

194ATmega128(L)2467B–09/01• Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial clocks from all ma

195ATmega128(L)2467B–09/01Figure 92. Arbitration Between two MastersNote that arbitration is not allowed between:• A REPEATED START condition and a d

196ATmega128(L)2467B–09/01Overview of the TWI ModuleThe TWI module is comprised of several submodules, as shown in Figure 93. All regis-ters drawn in

197ATmega128(L)2467B–09/01TWI Control Register (TWCR). When in transmitter mode, the value of the received(N)ACK bit can be determined by the value in

198ATmega128(L)2467B–09/01• Bits 7..0 - TWI Bit Rate RegisterTWBR selects the division factor for the bit rate generator. The bit rate generator is af

199ATmega128(L)2467B–09/01• Bit 3 - TWWC: TWI Write Collision FlagThe TWWC bit is set when attempting to write to the TWI Data Register – TWDR whenTWI

2ATmega128(L)2467B–09/01Pin Configurations Figure 1. Pinout ATmega128Overview The ATmega128 is a low-power CMOS 8-bit microcontroller based on the AV

20ATmega128(L)2467B–09/01• Bits 11..0 - EEAR11..0: EEPROM AddressThe EEPROM Address Registers – EEARH and EEARL specify the EEPROM addressin the 4K by

200ATmega128(L)2467B–09/01data is lost in the transition from Master to Slave. Handling of the ACK bit is controlledautomatically by the TWI logic, th

201ATmega128(L)2467B–09/01Figure 94. Interfacing the Application to the TWI in a Typical Transmission1. The first step in a TWI transmission is to tr

202ATmega128(L)2467B–09/01Subsequently, a specific value must be written to TWCR, instructing the TWI hardware to transmit the data packet present in

203ATmega128(L)2467B–09/01Note: For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be repl

204ATmega128(L)2467B–09/01Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter(MT), Master Receiver (

205ATmega128(L)2467B–09/01Figure 95. Data Transfer in Master Transmitter ModeA START condition is sent by writing the following value to TWCR:TWEN mu

206ATmega128(L)2467B–09/01After a repeated START condition (state $10) the 2-wire Serial Interface can access thesame slave again, or a new slave with

207ATmega128(L)2467B–09/01Figure 96. Formats and States in the Master Transmitter ModeMaster Receiver Mode In the master receiver mode, a number of d

208ATmega128(L)2467B–09/01Figure 97. Data Transfer in Master Receiver ModeA START condition is sent by writing the following value to TWCR:TWEN must

209ATmega128(L)2467B–09/01Figure 98. Formats and States in the Master Receiver ModeTable 88. Status Codes for Master Receiver ModeStatus Code(TWSR)P

21ATmega128(L)2467B–09/01The EEPROM can not be programmed during a CPU write to the Flash memory. Thesoftware must check that the Flash programming is

210ATmega128(L)2467B–09/01Slave Receiver Mode In the slave receiver mode, a number of data bytes are received from a master transmit-ter (see Figure 9

211ATmega128(L)2467B–09/01set up with a long start-up time, the SCL line may be held low for a long time, blockingother data transmissions.Note that t

212ATmega128(L)2467B–09/01Figure 100. Formats and States in the Slave Receiver ModeSlave Transmitter Mode In the slave transmitter mode, a number of

213ATmega128(L)2467B–09/01The upper 7 bits are the address to which the 2-wire Serial Interface will respond whenaddressed by a master. If the LSB is

214ATmega128(L)2467B–09/01Figure 102. Formats and States in the Slave Transmitter ModeTable 90. Status Codes for Slave Transmitter ModeStatus Code(T

215ATmega128(L)2467B–09/01Miscellaneous States There are two status codes that do not correspond to a defined TWI state, see Table 91.Status $F8 indic

216ATmega128(L)2467B–09/01Multi-master Systems and ArbitrationIf multiple masters are connected to the same bus, transmissions may be initiated simul-

217ATmega128(L)2467B–09/01Figure 105. Possible Status Codes Caused by ArbitrationOwnAddress / General CallreceivedArbitration lost in SLATWI bus will

218ATmega128(L)2467B–09/01Analog Comparator The analog comparator compares the input values on the positive pin AIN0 and nega-tive pin AIN1. When the

219ATmega128(L)2467B–09/01• Bit 7 - ACD: Analog Comparator DisableWhen this bit is written logic one, the power to the analog comparator is switched o

22ATmega128(L)2467B–09/01The next code examples show assembly and C functions for reading the EEPROM. Theexamples assume that interrupts are controlle

220ATmega128(L)2467B–09/01Analog Comparator Multiplexed InputIt is possible to select any of the ADC7..0 pins to replace the negative input to the ana

221ATmega128(L)2467B–09/01Analog to Digital ConverterFeatures • 10-bit Resolution• 0.5 LSB Integral Non-linearity• ±2 LSB Absolute Accuracy• TBD - 260

222ATmega128(L)2467B–09/01Figure 107. Analog to Digital Converter Block SchematicADC CONVERSIONCOMPLETE IRQ8-BIT DATA BUS15 0ADC MULTIPLEXERSELECT (A

223ATmega128(L)2467B–09/01Operation The ADC converts an analog input voltage to a 10-bit digital value through successiveapproximation. The minimum va

224ATmega128(L)2467B–09/01Prescaling and Conversion TimingFigure 108. ADC PrescalerBy default, the successive approximation circuitry requires an inp

225ATmega128(L)2467B–09/01Figure 109. ADC Timing Diagram, First Conversion (Single Conversion Mode)Figure 110. ADC Timing Diagram, Single Conversion

226ATmega128(L)2467B–09/01Differential Gain Channels When using differential gain channels, certain aspects of the conversion need to betaken into con

227ATmega128(L)2467B–09/01In Single Conversion mode, always select the channel before starting the conversion.The channel selection may be changed one

228ATmega128(L)2467B–09/01Note that the ADC will not be automatically turned off when entering other sleep modesthan idle mode and ADC noise reduction

229ATmega128(L)2467B–09/01Figure 113. ADC Power ConnectionsOffset Compensation SchemesThe gain stage has a built-in offset cancellation circuitry tha

23ATmega128(L)2467B–09/01Preventing EEPROM CorruptionDuring periods of low VCC, the EEPROM data can be corrupted because the supply volt-age is too lo

230ATmega128(L)2467B–09/01Figure 114. Offset Error• Gain error: After adjusting for offset, the gain error is found as the deviation of the last tran

231ATmega128(L)2467B–09/01Figure 116. Integral Non-Linearity (INL)• Differential Non-Linearity (DNL): The maximum deviation of the actual code width

232ATmega128(L)2467B–09/01where VIN is the voltage on the selected input pin and VREF the selected voltage refer-ence (see Table 96 on page 233 and Ta

233ATmega128(L)2467B–09/01Example: ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result) Voltage on ADC3 is 300 mV, voltage on A

234ATmega128(L)2467B–09/01regardless of any ongoing conversions. For a complete description of this bit, see “TheADC Data Register – ADCL and ADCH” on

235ATmega128(L)2467B–09/01ADC Control and Status Register A – ADCSRA• Bit 7 - ADEN: ADC EnableWriting this bit to one enables the ADC. By writing it t

236ATmega128(L)2467B–09/01The ADC Data Register – ADCL and ADCHADLAR = 0:ADLAR = 1:When an ADC conversion is complete, the result is found in these tw

237ATmega128(L)2467B–09/01Special Function IO Register – SFIOR• Bit 4 - ADHSM: ADC High Speed ModeWriting this bit to one enables the ADC High Speed M

238ATmega128(L)2467B–09/01JTAG Interface and On-chip Debug SystemFeatures• JTAG (IEEE std. 1149.1 Compliant) Interface• Boundary-scan Capabilities Acc

239ATmega128(L)2467B–09/01• TDO: Test Data Out. Serial output data from Instruction register or Data Register.The IEEE std. 1149.1 also specifies an o

24ATmega128(L)2467B–09/01I/O Memory The I/O space definition of the ATmega128 is shown in “Register Summary” on page323.All ATmega128 I/Os and periphe

240ATmega128(L)2467B–09/01Figure 120. TAP Controller State DiagramTAP Controller The TAP controller is a 16-state finite state machine that controls

241ATmega128(L)2467B–09/01is left by setting TMS high. While the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out

242ATmega128(L)2467B–09/01• 2 single Program Memory break-points + 1 Data Memory break point with mask “range break point”.A debugger, like the AVR St

243ATmega128(L)2467B–09/01to this location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – isset to indicate to the debugger th

244ATmega128(L)2467B–09/01IEEE 1149.1 (JTAG) Boundary-scanFeatures • JTAG (IEEE std. 1149.1 Compliant) Interface• Boundary-scan Capabilities According

245ATmega128(L)2467B–09/01Capture-DR controller state. The Bypass register can be used to shorten the scan chainon a system when the other devices are

246ATmega128(L)2467B–09/01Figure 122. Reset RegisterBoundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic

247ATmega128(L)2467B–09/01• Shift-DR: The IDCODE scan chain is shifted by the TCK input.SAMPLE_PRELOAD; $2 Mandatory JTAG instruction for pre-loading

248ATmega128(L)2467B–09/01Scanning the Digital Port Pins Figure 123 shows the Boundary-scan Cell for a bidirectional port pin with pull-up func-tion.

249ATmega128(L)2467B–09/01Figure 124. General Port Pin Schematic diagramBoundary-scan and the Two-wire InterfaceThe 2 Two-wire Interface pins SCL and

25ATmega128(L)2467B–09/01Figure 11. External Memory with Sector SelectNote: ATmega128 in non ATmega103 compatibility mode: Memory Configuration A is

250ATmega128(L)2467B–09/01Figure 125. Additional Scan Signal for the Two-wire InterfaceScanning the RESET Pin The RESET pin accepts 5V active low log

251ATmega128(L)2467B–09/01Figure 127. Boundary-scan Cells for Oscillators and Clock OptionsTable 102 summaries the scan registers for the external cl

252ATmega128(L)2467B–09/01Figure 128. Analog comparatorFigure 129. General Boundary-scan Cell used for Signals for Comparator and ADCACBGBANDGAPREFE

253ATmega128(L)2467B–09/01Scanning the ADC Figure 130 shows a block diagram of the ADC with all relevant control and observe sig-nals. The Boundary-sc

254ATmega128(L)2467B–09/01Table 104. Boundary-scan Signals for the ADC Signal NameDirection as Seenfrom theADC DescriptionRecommen-ded Input when not

255ATmega128(L)2467B–09/01G10 Input Enable 10x gain 0 0G20 Input Enable 20x gain 0 0GNDEN Input Ground the negative input to comparator when true00HOL

256ATmega128(L)2467B–09/01Note: Incorrect setting of the switches in Figure 130 will make signal contention and may dam-age the part. There are severa

257ATmega128(L)2467B–09/01sidered since serial scanning of the Boundary-scan register usually takes considerablylonger time.Figure 131. ADC Timing Di

258ATmega128(L)2467B–09/01Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clockfrequency. As the algorithm keeps HOL

259ATmega128(L)2467B–09/01200 COMP ADC199 PRIVATE_SIGNAL1(1)198 ACLK197 ACTEN196 ADHSM195 ADCBGEN194 ADCEN193 AMPEN192 DAC_9191 DAC_8190 DAC_7189 DAC_

26ATmega128(L)2467B–09/01The control bits for the External Memory Interface are located in three registers, theMCU Control Register – MCUCR, the Exter

260ATmega128(L)2467B–09/01186 DAC_3 ADC185 DAC_2184 DAC_1183 DAC_0182 EXTCH181 G10180 G20179 GNDEN178 HOLD177 IREFEN176 MUXEN_7175 MUXEN_6174 MUXEN_51

261ATmega128(L)2467B–09/01159 PE0.Data Port E158 PE0.Control157 PE0.Pullup_Enable156 PE1.Data155 PE1.Control154 PE1.Pullup_Enable153 PE2.Data152 PE2.C

262ATmega128(L)2467B–09/01123 PB4.Data Port B122 PB4.Control121 PB4.Pullup_Enable120 PB5.Data119 PB5.Control118 PB5.Pullup_Enable117 PB6.Data116 PB6.C

263ATmega128(L)2467B–09/0192 PD0.Data Port D91 PD0.Control90 PD0.Pullup_Enable89 PD1.Data88 PD1.Control87 PD1.Pullup_Enable86 PD2.Data85 PD2.Control84

264ATmega128(L)2467B–09/0162 PC0.Data Port C61 PC0.Control60 PC0.Pullup_Enable59 PC1.Data58 PC1.Control57 PC1.Pullup_Enable56 PC2.Data55 PC2.Control54

265ATmega128(L)2467B–09/01Note: 1. PRIVATE_SIGNAL1 should always scanned in as zero.Boundary-scan Description Language FilesBoundary-scan Description

266ATmega128(L)2467B–09/01Boot Loader Support – Read-While-Write Self-ProgrammingThe Boot Loader Support provides a real Read-While-Write self-program

267ATmega128(L)2467B–09/01Note that the user software can never read any code that is located inside the RWWsection during a Boot Loader software oper

268ATmega128(L)2467B–09/01Figure 133. Memory Sections(1)Note: 1. The parameters in the figure above are given in Table on page 277.Boot Loader Lock

269ATmega128(L)2467B–09/01Note: 1. “1” means unprogrammed, “0” means programmedNote: 1. “1” means unprogrammed, “0´means programmedEntering the Boot L

27ATmega128(L)2467B–09/01The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keepercan be disabled and enabled in software as de

270ATmega128(L)2467B–09/01Store Program Memory Control Register – SPMCRThe Store Program Memory Control Register contains the control bits needed to c

271ATmega128(L)2467B–09/01the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear uponcompletion of a page erase, or if no SPM

272ATmega128(L)2467B–09/01Figure 134. Addressing the Flash During SPM(1)Note: 1. The different variables used in Figure 134 are listed in Table 114 o

273ATmega128(L)2467B–09/01Performing Page Erase by SPMTo execute page erase, set up the address in the Z pointer, write “X0000011” to SPMCRand execute

274ATmega128(L)2467B–09/01See Table 109 and Table 110 for how the different settings of the Boot Loader Bitsaffect the Flash access.If bits 5..2 in R0

275ATmega128(L)2467B–09/01Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits thatare unprogrammed, will be read as one.P

276ATmega128(L)2467B–09/01ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)call Do_spm; transfer data from RAM to Flash page bufferldi looplo, low(PA

277ATmega128(L)2467B–09/01spm; restore SREG (to enable interrupts if originally enabled)out SREG, temp2retATmega128 Boot Loader ParametersIn Table 113

278ATmega128(L)2467B–09/01Notes: 1. The Z-register is only 15 bits wide. Bit 16 is located in the RAMPZ register in the I/Omap.2. Z0: should be zero f

279ATmega128(L)2467B–09/01Memory ProgrammingProgram and Data Memory Lock BitsThe ATmega128 provides six Lock bits which can be left unprogrammed (“1”)

28ATmega128(L)2467B–09/01Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1)Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower

280ATmega128(L)2467B–09/01Notes: 1. Program the fuse bits before programming the Lock bits.2. “1” means unprogrammed, “0´means programmedFuse Bits The

281ATmega128(L)2467B–09/01Notes: 1. The SPIEN fuse is not accessible in serial programming mode.2. The CKOPT fuse functionality depends on the setting

282ATmega128(L)2467B–09/01Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device.This code can be rea

283ATmega128(L)2467B–09/01Table 121. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O FunctionRDY/BSYPD1 O0: Device is busy programming,

284ATmega128(L)2467B–09/01Parallel ProgrammingEnter Programming Mode The following algorithm puts the device in parallel programming mode:1. Apply 4.5

285ATmega128(L)2467B–09/013. Set DATA to “1000 0000”. This is the command for Chip Erase.4. Give XTAL1 a positive pulse. This loads the command.5. Giv

286ATmega128(L)2467B–09/01H. Program Page1. Set BS1 = “0”2. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSYgoes

287ATmega128(L)2467B–09/01Figure 137. Programming the Flash WaveformsNote: “XX” is don’t care. The letters refer to the programming description above

288ATmega128(L)2467B–09/01Figure 138. Programming the EEPROM WaveformsReading the Flash The algorithm for reading the Flash memory is as follows (ref

289ATmega128(L)2467B–09/01Programming the Fuse High BitsThe algorithm for programming the Fuse high bits is as follows (refer to “Programmingthe Flash

29ATmega128(L)2467B–09/01Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1)Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower

290ATmega128(L)2467B–09/01Figure 139. Mapping Between BS1, BS2 and the Fuse- and Lock Bits During ReadReading the Signature Bytes The algorithm for r

291ATmega128(L)2467B–09/01Figure 141. Parallel Programming Timing, Loading Sequence with TimingRequirementsNote: The timing requirements shown in Fig

292ATmega128(L)2467B–09/01Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse Bits and Write LockBits commands.2. tWLRH_CE is val

293ATmega128(L)2467B–09/01Figure 143. Serial Programming and VerifyNote: If the device is clocked by the internal oscillator, it is no need to connec

294ATmega128(L)2467B–09/01ing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all 4 bytes of the instruction

295ATmega128(L)2467B–09/01least tWD_EEPROM before programming the next byte. See Table 129 for tWD_EEPROMvalue.Figure 144. .Serial Programming Wavefo

296ATmega128(L)2467B–09/01Note: a = address high bitsb = address low bitsH = 0 - Low byte, 1 - High Byteo = data outi = data inx = don’t careWrite Fus

297ATmega128(L)2467B–09/01Serial Programming CharacteristicsFigure 145. Serial Programming TimingNote: 2 tCLCL for fck < 12 MHz, 3 tCLCL for fck &

298ATmega128(L)2467B–09/01Figure 146. State Machine Sequence for Changing the Instruction WordAVR_RESET ($C) The AVR specific public JTAG instruction

299ATmega128(L)2467B–09/01PROG_COMMANDS ($5) The AVR specific public JTAG instruction for entering programming commands via theJTAG port. The 15-bit P

3ATmega128(L)2467B–09/01Block DiagramFigure 2. Block DiagramPROGRAMCOUNTERINTERNALOSCILLATORWATCHDOGTIMERSTACKPOINTERPROGRAMFLASHMCU CONTROLREGISTERS

30ATmega128(L)2467B–09/01• Bit 6..4 - SRL2, SRL1, SRL0: Wait-state Sector LimitIt is possible to configure different wait-states for different externa

300ATmega128(L)2467B–09/01When the contents of the register is equal to the programming enable signature, pro-gramming via the JTAG port is enabled. T

301ATmega128(L)2467B–09/01Figure 148. Programming Command RegisterTDITDOSTROBESADDRESS/DATAFlashEEPROMFusesLock Bits

302ATmega128(L)2467B–09/01Table 132. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte,

303ATmega128(L)2467B–09/015c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx5d. Read Data Byte 0110011_bbbbbbbb0110010_000000000110011_000000

304ATmega128(L)2467B–09/01Notes: 1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which i

305ATmega128(L)2467B–09/01Figure 149. State Machine Sequence for Changing/Reading the Data WordVirtual Flash Page Load RegisterThe Virtual Flash Page

306ATmega128(L)2467B–09/01Figure 150. Virtual Flash Page Load RegisterVirtual Flash Page Read RegisterThe Virtual Flash Page Read register is a virtu

307ATmega128(L)2467B–09/01Entering Programming Mode 1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset register.2. Enter instruction PROG_EN

308ATmega128(L)2467B–09/017. Write the page using programming instruction 2g.8. Poll for Flash write complete using programming instruction 2h, or wai

309ATmega128(L)2467B–09/01Programming the Fuses 1. Enter JTAG instruction PROG_COMMANDS.2. Enable Fuse write using programming instruction 6a.3. Load

31ATmega128(L)2467B–09/01• Bit 0 - Res: Reserved BitThis is a reserved bit and will always read as zero. When writing to this address location,write t

310ATmega128(L)2467B–09/01Electrical CharacteristicsAbsolute Maximum Ratings*DC CharacteristicsOperating Temperature...

311ATmega128(L)2467B–09/01Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low2. “Min” means the lowest value where t

312ATmega128(L)2467B–09/01External Clock Drive WaveformsFigure 152. External Clock Drive WaveformsExternal Clock DriveNote: R should be in the range

313ATmega128(L)2467B–09/012-wire Serial Interface CharacteristicsTable 135 describes the requirements for devices connected to the 2-wire Serial Bus.

314ATmega128(L)2467B–09/015. This requirement applies to all ATmega128 2-wire Serial Interface operation. Otherdevices connected to the 2-wire Serial

315ATmega128(L)2467B–09/01Figure 154. SPI Interface Timing Requirements (Master Mode)Figure 155. SPI Interface Timing Requirements (Slave Mode)MOSI(

316ATmega128(L)2467B–09/01ADC Characteristics - Preliminary DataNote: 1. Values are guidelines only. Actual values are TBD.2. Minimum for AVCC is 2.7

317ATmega128(L)2467B–09/01External Data Memory TimingNotes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the ext

318ATmega128(L)2467B–09/01Table 140. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0Symbol Parameter4 MHz Oscillator Vari

319ATmega128(L)2467B–09/01Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.2. This

32ATmega128(L)2467B–09/01Using all 64KB Locations of External MemorySince the external memory is mapped after the internal memory as shown in Figure 1

320ATmega128(L)2467B–09/01Figure 156. External Memory Timing (SRWn1 = 0, SRWn0 = 0Figure 157. External Memory Timing (SRWn1 = 0, SRWn0 = 1)ALET1 T2

321ATmega128(L)2467B–09/01Figure 158. External Memory Timing (SRWn1 = 1, SRWn0 = 0)Figure 159. External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1)Note:

322ATmega128(L)2467B–09/01ATmega128 Typical Characteristics – Preliminary DataThe following charts show typical behavior. These figures are not tested

323ATmega128(L)2467B–09/01Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page($FF) Reserved - - - - - - - -.. Reserved

324ATmega128(L)2467B–09/01($61) DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 83($60) Reserved - - - - - - - -$3F ($5F) SREG I T H S V N Z C 9$3E ($5E)

325ATmega128(L)2467B–09/01Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory ad

326ATmega128(L)2467B–09/01Instruction Set Summary Mnemonics Operands Description Operation Flags #ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Ad

327ATmega128(L)2467B–09/01Mnemonics Operands Description Operation Flags #ClocksBRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 N

328ATmega128(L)2467B–09/01Mnemonics Operands Description Operation Flags #ClocksSEV Set Twos Complement Overflow. V ← 1V1CLV Clear Twos Complement Ove

329ATmega128(L)2467B–09/01Ordering InformationSpeed (MHz) Power Supply Ordering Code Package Operation Range8 2.7 - 5.5V ATmega128-8AC 64A Commercial(

33ATmega128(L)2467B–09/01System Clock and Clock OptionsClock Systems and their DistributionFigure 17 presents the principal clock systems in the AVR a

330ATmega128(L)2467B–09/01Packaging Information64APIN 1 ID0.80(0.0315) BSC16.25(0.640)SQSQ15.75(0.620)0.45(0.018)0.30(0.012)14.10(0.555)13.90(0.547)0.

© Atmel Corporation 2001.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa

34ATmega128(L)2467B–09/01Asynchronous Timer Clock – clkASYThe Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clockeddirectly fro

35ATmega128(L)2467B–09/01For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and 16MHz with CKOPT programmed. C1 and C2 should alwa

36ATmega128(L)2467B–09/01Notes: 1. These options should only be used when not operating close to the maximum fre-quency of the device, and only if fre

37ATmega128(L)2467B–09/01Note: 1. These options should only be used if frequency stability at start-up is not importantfor the application.External RC

38ATmega128(L)2467B–09/01Calibrated Internal RC OscillatorThe calibrated internal RC oscillator provides a fixed 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0MHz

39ATmega128(L)2467B–09/01External Clock To drive the device from an external clock source, XTAL1 should be driven as shown inFigure 20. To run the dev

4ATmega128(L)2467B–09/01The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are directly conne

40ATmega128(L)2467B–09/01• Bit 7 - XDIVEN: XTAL Divide EnableWhen the XDIVEN bit is written one, the clock frequency of the CPU and all peripherals(cl

41ATmega128(L)2467B–09/01Power Management and Sleep ModesSleep modes enable the application to shut down unused modules in the MCU, therebysaving powe

42ATmega128(L)2467B–09/01Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enterIdle Mode, stopping the CPU but a

43ATmega128(L)2467B–09/01asynchronous timer should be considered undefined after wake-up in Power-save Modeif AS0 is 0.This sleep mode basically halts

44ATmega128(L)2467B–09/01Minimizing Power ConsumptionThere are several issues to consider when trying to minimize the power consumption inan AVR contr

45ATmega128(L)2467B–09/01System Control and ResetResetting the AVR During reset, all I/O registers are set to their initial values, and the program st

46ATmega128(L)2467B–09/01Figure 21. Reset LogicNotes: 1. Values are guidelines only. Actual values are TBD.2. The Power-on Reset will not work unless

47ATmega128(L)2467B–09/01Power-on Reset A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detec-tion level is defined in

48ATmega128(L)2467B–09/01Figure 24. External Reset During OperationBrown-out Detection ATmega128 has an on-chip brown-out detection (BOD) circuit for

49ATmega128(L)2467B–09/01Figure 26. Watchdog Reset During OperationMCU Control and Status Register – MCUCSRThe MCU Control and Status Register provid

5ATmega128(L)2467B–09/01The ATmega128 is 100% pin compatible with ATmega103, and can replace theATmega103 on current Printed Circuit Boards. The appli

50ATmega128(L)2467B–09/01Voltage Reference Enable Signals and Start-up TimeThe voltage reference has a start-up time that may influence the way it sho

51ATmega128(L)2467B–09/01Figure 27. Watchdog TimerWatchdog Timer Control Register – WDTCR• Bits 7..5 - Res: Reserved BitsThese bits are reserved bits

52ATmega128(L)2467B–09/011. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one

53ATmega128(L)2467B–09/01Timed Sequences for Changing the Configuration of the Watch Dog TimerThe sequence for changing configuration differs slightly

54ATmega128(L)2467B–09/01Interrupts This chapter describes the specifics of the interrupt handling as performed inATmega128. For a general explanation

55ATmega128(L)2467B–09/01Notes: 1. When the BOOTRST fuse is programmed, the device will jump to the Boot Loaderaddress at reset, see “Boot Loader Supp

56ATmega128(L)2467B–09/01The most typical and general program setup for the Reset and Interrupt VectorAddresses in ATmega128 is:Address Labels Code Co

57ATmega128(L)2467B–09/01When the BOOTRST fuse is unprogrammed, the boot section size set to 8K bytes andthe IVSEL bit in the MCUCR register is set be

58ATmega128(L)2467B–09/01Moving Interrupts Between Application and Boot SpaceThe General Interrupt Control Register controls the placement of the inte

59ATmega128(L)2467B–09/01• Bit 0 - IVCE: Interrupt Vector Change EnableThe IVCE bit must be written to logic one to enable change of the IVSEL bit. IV

6ATmega128(L)2467B–09/01Port C also serves the functions of special features of the ATmega128 as listed on page72. In ATmega103 compatibility mode, Po

60ATmega128(L)2467B–09/01I/O-PortsIntroduction All AVR ports have true Read-Modify-Write functionality when used as general digitalI/O ports. This mea

61ATmega128(L)2467B–09/01Ports as General Digital I/OThe ports are bi-directional I/O ports with optional internal pull-ups. Figure 29 shows afunction

62ATmega128(L)2467B–09/01When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,PORTxn} = 0b11), an intermediate state with e

63ATmega128(L)2467B–09/01Figure 30. Synchronization when Reading an Externally Applied Pin ValueConsider the clock period starting shortly after the

64ATmega128(L)2467B–09/01Figure 31. Synchronization when Reading a Software Assigned Pin ValueThe following code example shows how to set port B pins

65ATmega128(L)2467B–09/01Note: 1. For the assembly program, two temporary registers are used to minimize the timefrom pull-ups are set on pins 0, 1, 6

66ATmega128(L)2467B–09/01Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure32 shows ho

67ATmega128(L)2467B–09/01The following subsections shortly describes the alternate functions for each port, andrelates the overriding signals to the a

68ATmega128(L)2467B–09/01• Bit 2 - PUD: Pull-up disableWhen this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxnand

69ATmega128(L)2467B–09/01Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 30.Note: 1. OC1C not applicable in

7ATmega128(L)2467B–09/01XTAL2 Output from the inverting oscillator amplifier.AVCC This is the supply voltage pin for Port F and the A/D Converter. It

70ATmega128(L)2467B–09/01• OC1B, Bit 6OC1B, Output Compare matchB output: The PB6 pin can serve as an external outputfor the Timer/Counter1 output com

71ATmega128(L)2467B–09/01Note: 1. See “Output Compare Modulator (OCM1C2)” on page 155 for details. OC1C doesnot exist in ATmega103 compatibility mode.

72ATmega128(L)2467B–09/01Alternate Functions of Port C In ATmega103 compatibility mode, Port C is output only. The Port C has an alternatefunction as

73ATmega128(L)2467B–09/01Note: 1. XMM = 0 in ATmega103 compatibility mode.Alternate Functions of Port D The Port D pins with alternate functions are s

74ATmega128(L)2467B–09/01• IC1 - Port D, Bit 4IC1 - Input Capture Pin1: The PD4 pin can act as an input capture pin forTimer/Counter1.• INT3/TXD1 - Po

75ATmega128(L)2467B–09/01 Note: 1. When enabled, the Two-wire Serial Interface enables Slew-Rate controls on the out-put pins PD0 and PD1. This is not

76ATmega128(L)2467B–09/01Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 39.Note: 1. IC3, T3, OC3C, OC3B, OC

77ATmega128(L)2467B–09/01OC3A, Output Compare matchA output: The PE3 pin can serve as an external outputfor the Timer/Counter3 output compareA. The pi

78ATmega128(L)2467B–09/01 Alternate Functions of Port F The Port F has an alternate function as analog input for the ADC as shown in Table 42.If some

79ATmega128(L)2467B–09/01• TMS, ADC5 - Port F, Bit 5ADC5, Analog to Digital Converter, Channel 5.TMS, JTAG Test Mode Select: This pin is used for navi

8ATmega128(L)2467B–09/01AVR CPU CoreIntroduction This chapter discusses the AVR core architecture in general. The main function of theCPU core is to e

80ATmega128(L)2467B–09/01Alternate Functions of Port G In ATmega103 compatibility mode, only the alternate functions are the defaults for PortG, and P

81ATmega128(L)2467B–09/01Register Description for I/O PortsPort A Data Register – PORTAPort A Data Direction Register – DDRAPort A Input Pins Address

82ATmega128(L)2467B–09/01Port B Input Pins Address – PINBPort C Data Register – PORTCPort C Data Direction Register – DDRCPort C Input Pins Address –

83ATmega128(L)2467B–09/01Port E Data Direction Register – DDREPort E Input Pins Address – PINEPort F Data Register – PORTFPort F Data Direction Regist

84ATmega128(L)2467B–09/01External Interrupts The external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, theinterrupts will tr

85ATmega128(L)2467B–09/01Note: 1. n = 3, 2, 1or 0.When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing itsInterrupt Enable b

86ATmega128(L)2467B–09/01External Interrupt Mask Register – EIMSK• Bits 7..4 - INT7 - INT0: External Interrupt Request 7 - 0 EnableWhen an INT7- INT4

87ATmega128(L)2467B–09/018-bit Timer/Counter0 with PWM and Asynchronous OperationTimer/Counter0 is a general purpose, single channel, 8-bit Timer/Coun

88ATmega128(L)2467B–09/01The Timer/Counter can be clocked internally, via the prescaler, or asynchronouslyclocked from the TOSC1/2 pins, as detailed l

89ATmega128(L)2467B–09/01Signal description (internal signals):count Increment or decrement TCNT0 by 1.direction Selects between increment and decreme

9ATmega128(L)2467B–09/01an arithmetic operation, the Status Register is updated to reflect information about theresult of the operation.Program flow i

90ATmega128(L)2467B–09/01Figure 35. Output Compare Unit, Block DiagramThe OCR0 register is double buffered when using any of the pulse width modulati

91ATmega128(L)2467B–09/01The setup of the OC0 should be performed before setting the data direction register forthe port pin to output. The easiest wa

92ATmega128(L)2467B–09/01mode, refer to Table 54 on page 99, and for phase correct PWM refer to Table 55 onpage 100.A change of the COM01:0 bits state

93ATmega128(L)2467B–09/01Figure 37. CTC Mode, Timing DiagramAn interrupt can be generated each time the counter value reaches the TOP value byusing t

94ATmega128(L)2467B–09/01non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0slopes represent compare matches between O

95ATmega128(L)2467B–09/01Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 3) provides a high resolution phase correctPWM waveform generati

96ATmega128(L)2467B–09/01and TCNT0 when the counter decrements. The PWM frequency for the output whenusing phase correct PWM can be calculated by the

97ATmega128(L)2467B–09/01Figure 41. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)Figure 42 shows the setting of OCF0 in all modes except

98ATmega128(L)2467B–09/01Figure 43. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, withPrescaler (fclk_I/O/8)8-bit Timer/Counter Re

99ATmega128(L)2467B–09/01Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def-initions. However, the functionality an