Rainbow-electronics ATmega64M1 User Manual

Features• High Performance, Low Power AVR ® 8-bit Microcontroller• Advanced RISC Architecture– 131 Powerful Instructions - Most Single Clock Cycle Exe

108209A–AVR–08/09ATmega16M1/32M1/64M17. AVR CPU Core7.1 OverviewThis section discusses the AVR core architecture in general. The main function of the

1008209A–AVR–08/09ATmega16M1/32M1/64M115.9.2 TCCR0B – Timer/Counter Control Register B• Bit 7 – FOC0A: Force Output Compare AThe FOC0A bit is only act

1018209A–AVR–08/09ATmega16M1/32M1/64M1If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock thecounter even if t

1028209A–AVR–08/09ATmega16M1/32M1/64M1• Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt EnableWhen the OCIE0B bit is written to one, an

1038209A–AVR–08/09ATmega16M1/32M1/64M116. 16-bit Timer/Counter1 with PWM16.1 Features• True 16-bit Design (i.e., Allows 16-bit PWM)• Two independent O

1048209A–AVR–08/09ATmega16M1/32M1/64M1Figure 16-1. 16-bit Timer/Counter Block Diagram(1)Note: 1. Refer toTable on page 3 for Timer/Counter1 pin place

1058209A–AVR–08/09ATmega16M1/32M1/64M1The Input Capture Register can capture the Timer/Counter value at a given external (edge trig-gered) event on ei

1068209A–AVR–08/09ATmega16M1/32M1/64M1Note: 1. The example code assumes that the part specific header file is included.For I/O Registers located in ex

1078209A–AVR–08/09ATmega16M1/32M1/64M1The following code examples show how to do an atomic read of the TCNTn Register contents.Reading any of the OCRn

1088209A–AVR–08/09ATmega16M1/32M1/64M1The following code examples show how to do an atomic write of the TCNTn Register contents.Writing any of the OCR

1098209A–AVR–08/09ATmega16M1/32M1/64M116.5 Counter UnitThe main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter uni

118209A–AVR–08/09ATmega16M1/32M1/64M1ical ALU operation, two operands are output from the Register File, the operation is executed,and the result is s

1108209A–AVR–08/09ATmega16M1/32M1/64M1The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected bythe WGMn3:0 bits. TO

1118209A–AVR–08/09ATmega16M1/32M1/64M1tion mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRnRegister. When writing the I

1128209A–AVR–08/09ATmega16M1/32M1/64M1cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,the clearing o

1138209A–AVR–08/09ATmega16M1/32M1/64M1The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation(PWM) modes. For the No

1148209A–AVR–08/09ATmega16M1/32M1/64M116.8 Compare Match Output UnitThe Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator

1158209A–AVR–08/09ATmega16M1/32M1/64M1non-PWM modes refer to Table 16-1 on page 124. For fast PWM mode refer to Table 16-2 onpage 125, and for phase c

1168209A–AVR–08/09ATmega16M1/32M1/64M1Figure 16-6. CTC Mode, Timing DiagramAn interrupt can be generated at each time the counter value reaches the TO

1178209A–AVR–08/09ATmega16M1/32M1/64M1The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn orOCRnA. The minimu

1188209A–AVR–08/09ATmega16M1/32M1/64M1to be written anytime. When the OCRnA I/O location is written the value written will be put intothe OCRnA Buffer

1198209A–AVR–08/09ATmega16M1/32M1/64M10x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolu-tion in bits can be cal

128209A–AVR–08/09ATmega16M1/32M1/64M1specified in the Instruction Set Reference. This will in many cases remove the need for using thededicated compar

1208209A–AVR–08/09ATmega16M1/32M1/64M1implies that the length of the falling slope is determined by the previous TOP value, while thelength of the ris

1218209A–AVR–08/09ATmega16M1/32M1/64M1the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits canbe calculated using t

1228209A–AVR–08/09ATmega16M1/32M1/64M1Using the ICRn Register for defining TOP works well when using fixed TOP values. By usingICRn, the OCRnA Registe

1238209A–AVR–08/09ATmega16M1/32M1/64M1Figure 16-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8)Figure 16-12 shows the

1248209A–AVR–08/09ATmega16M1/32M1/64M1Figure 16-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)16.11 Register Description16.11.1 TCCR1A

1258209A–AVR–08/09ATmega16M1/32M1/64M1Table 16-2 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fastPWM mode.Note: 1. A spe

1268209A–AVR–08/09ATmega16M1/32M1/64M1Note: 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the funct

1278209A–AVR–08/09ATmega16M1/32M1/64M1When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in theTCCRnA and the TCCRnB Regi

1288209A–AVR–08/09ATmega16M1/32M1/64M1A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timeron Compare match

1298209A–AVR–08/09ATmega16M1/32M1/64M116.11.7 ICR1H and ICR1L – Input Capture Register 1The Input Capture is updated with the counter (TCNTn) value ea

138209A–AVR–08/09ATmega16M1/32M1/64M17.4 General Purpose Register FileThe Register File is optimized for the AVR Enhanced RISC instruction set. In ord

1308209A–AVR–08/09ATmega16M1/32M1/64M116.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register• Bit 7, 6 – Res: ReservedThese bits are reserved and will

1318209A–AVR–08/09ATmega16M1/32M1/64M117. Timer/Counter0 and Timer/Counter1 PrescalersThe “8-bit Timer/Counter0 with PWM” and the “16-bit Timer/Count

1328209A–AVR–08/09ATmega16M1/32M1/64M1Enabling and disabling of the clock input must be done when Tn/T0 has been stable for at leastone system clock c

1338209A–AVR–08/09ATmega16M1/32M1/64M117.4 Register Description17.4.1 GTCCR – General Timer/Counter Control Register• Bit 7 – TSM: Timer/Counter Synch

1348209A–AVR–08/09ATmega16M1/32M1/64M118. PSC – Power Stage Controller18.1 Features• PWM waveform generation function with 6 complementary programmabl

1358209A–AVR–08/09ATmega16M1/32M1/64M118.4 PSC DescriptionFigure 18-1. Power Stage Controller Block DiagramDATABUSPOCR_RB=PSC CounterWaveformGenerator

1368209A–AVR–08/09ATmega16M1/32M1/64M1The PSC is based on the use of a free-running 12-bit counter (PSC counter). This counter isable to count up to a

1378209A–AVR–08/09ATmega16M1/32M1/64M1Figure 18-3. Cycle Presentation in Centered ModeFigure 18-2 and Figure 18-3 graphically illustrate the values he

1388209A–AVR–08/09ATmega16M1/32M1/64M1Figure 18-4. PSCOUTnA & PSCOUTnB Basic Waveforms in One Ramp modeOn-Time A = (POCRnRAH/L - POCRnSAH/L) * 1/F

1398209A–AVR–08/09ATmega16M1/32M1/64M118.5.3.2 Center Aligned ModeIn center aligned mode, the center of PSCOUTnA and PSCOUTnB signals are centered.Fig

148209A–AVR–08/09ATmega16M1/32M1/64M1Figure 7-3. The X-, Y-, and Z-registersIn the different addressing modes these address registers have functions a

1408209A–AVR–08/09ATmega16M1/32M1/64M1Figure 18-7. Controlled Start and Stop Mechanism in Centered ModeNote: See “PCTL – PSC Control Register” on page

1418209A–AVR–08/09ATmega16M1/32M1/64M118.7 Overlap ProtectionThanks to Overlap Protection two outputs on a same module cannot be active at the same ti

1428209A–AVR–08/09ATmega16M1/32M1/64M118.8.1 Input DescriptionTable 18-1. Internal InputsTable 18-2. Block Inputs18.8.2 Output DescriptionTable 18-3.

1438209A–AVR–08/09ATmega16M1/32M1/64M1Table 18-4. Internal OutputsNote: 1. See “Analog Synchronization” on page 146.18.9 PSC InputFor detailed informa

1448209A–AVR–08/09ATmega16M1/32M1/64M1outputs. This way needs that CLKPSC is running. So thanks to PSC Asynchronous Output Con-trol bit (PAOCnA/B), PS

1458209A–AVR–08/09ATmega16M1/32M1/64M118.10 PSC Input Modes 001b to 10xb: Deactivate outputs without changing timing.Figure 18-12. PSC behaviour versu

1468209A–AVR–08/09ATmega16M1/32M1/64M118.12 Analog SynchronizationEach PSC module generates a signal to synchronize the ADC sample and hold; synchroni

1478209A–AVR–08/09ATmega16M1/32M1/64M118.15 InterruptsThis section describes the specifics of the interrupt handling as performed inATmega16M1/32M1/64

1488209A–AVR–08/09ATmega16M1/32M1/64M1When this bit is set, I/O pin affected to PSCOUT2B is connected to the PSC module 2 waveformgenerator B output a

1498209A–AVR–08/09ATmega16M1/32M1/64M1• Bit 1:0 – PSYNC0[1:0]: Synchronization Out for ADC SelectionSelect the polarity and signal source for generati

158209A–AVR–08/09ATmega16M1/32M1/64M17.5.1 SPH and SPL – Stack Pointer High and Stack Pointer Low Register7.6 Instruction Execution TimingThis section

1508209A–AVR–08/09ATmega16M1/32M1/64M118.16.6 POCRnRBH and POCRnRBL – PSC Output Compare RB RegisterNote : n = 0 to 2 according to module number.The O

1518209A–AVR–08/09ATmega16M1/32M1/64M1• Bit 1:0 – Res: ReservedThese bits are reserved and will always read as zero.18.16.8 PCTL – PSC Control Registe

1528209A–AVR–08/09ATmega16M1/32M1/64M1• Bit 6 – PISELn: PSC Module n Input SelectClear this bit to select PSCINn as module n input.Set this bit to sel

1538209A–AVR–08/09ATmega16M1/32M1/64M1• Bit 2 – PEVE1: PSC External Event 1 Interrupt EnableWhen this bit is set, an external event which can generate

1548209A–AVR–08/09ATmega16M1/32M1/64M119. SPI – Serial Peripheral Interface 19.1 Features• Full-duplex, Three-wire Synchronous Data Transfer• Master o

1558209A–AVR–08/09ATmega16M1/32M1/64M1The interconnection between Master and Slave CPUs with SPI is shown in Figure 19-2. The sys-tem consists of two

1568209A–AVR–08/09ATmega16M1/32M1/64M1When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overriddenaccording to Table

1578209A–AVR–08/09ATmega16M1/32M1/64M1Note: 1. The example code assumes that the part specific header file is included.The following code examples sho

1588209A–AVR–08/09ATmega16M1/32M1/64M1Note: 1. The example code assumes that the part specific header file is included.Assembly Code Example(1)SPI_Sla

1598209A–AVR–08/09ATmega16M1/32M1/64M119.3 SS Pin Functionality19.3.1 Slave ModeWhen the SPI is configured as a Slave, the Slave Select (SS) pin is al

168209A–AVR–08/09ATmega16M1/32M1/64M17.7 Reset and Interrupt HandlingThe AVR provides several different interrupt sources. These interrupts and the se

1608209A–AVR–08/09ATmega16M1/32M1/64M1Figure 19-3. SPI Transfer Format with CPHA = 0Figure 19-4. SPI Transfer Format with CPHA = 119.5 Register Descri

1618209A–AVR–08/09ATmega16M1/32M1/64M119.5.2 SPCR – SPI Control Register• Bit 7 – SPIE: SPI Interrupt EnableThis bit causes the SPI interrupt to be ex

1628209A–AVR–08/09ATmega16M1/32M1/64M119.5.3 SPSR – SPI Status Register• Bit 7 – SPIF: SPI Interrupt FlagWhen a serial transfer is complete, the SPIF

1638209A–AVR–08/09ATmega16M1/32M1/64M119.5.4 SPDR – SPI Data Register• Bits 7:0 - SPD7:0: SPI DataThe SPI Data Register is a read/write register used

1648209A–AVR–08/09ATmega16M1/32M1/64M120. CAN – Controller Area Network20.1 Features• Full CAN Controller• Fully Compliant with CAN Standard rev 2.0 A

1658209A–AVR–08/09ATmega16M1/32M1/64M1ically become receivers of the message with the highest priority and do not re-attempttransmission until the bus

1668209A–AVR–08/09ATmega16M1/32M1/64M120.3.2.2 CAN Extended FrameFigure 20-2. CAN Extended FramesA message in the CAN extended frame format is likely

1678209A–AVR–08/09ATmega16M1/32M1/64M1Figure 20-3. CAN Bit Construction20.3.3.2 Synchronization SegmentThe first segment is used to synchronize the va

1688209A–AVR–08/09ATmega16M1/32M1/64M120.3.3.8 Bit LengtheningAs a result of resynchronization, Phase Segment 1 may be lengthened or Phase Segment 2ma

1698209A–AVR–08/09ATmega16M1/32M1/64M1Figure 20-4. Bus Arbitration20.3.5 ErrorsThe CAN protocol signals any errors immediately as they occur. Three er

178209A–AVR–08/09ATmega16M1/32M1/64M1When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-cuted before any p

1708209A–AVR–08/09ATmega16M1/32M1/64M120.4 CAN ControllerThe CAN controller implemented into ATmega16M1/32M1/64M1 offers V2.0B Active.This full-CAN co

1718209A–AVR–08/09ATmega16M1/32M1/64M120.5 CAN Channel20.5.1 ConfigurationThe CAN channel can be in:• Enabled modeIn this mode:– the CAN channel (inte

1728209A–AVR–08/09ATmega16M1/32M1/64M1The total number of TQ in a bit time has to be programmed at least from 8 to 25.Figure 20-7. Sample and Transmis

1738209A–AVR–08/09ATmega16M1/32M1/64M120.5.3 Baud RateWith no baud rate prescaler (BRP[5..0]=0) the sampling point comes one time quantum tooearly. Th

1748209A–AVR–08/09ATmega16M1/32M1/64M120.6 Message ObjectsThe MOb is a CAN frame descriptor. It contains all information to handle a CAN frame. Thisme

1758209A–AVR–08/09ATmega16M1/32M1/64M12. The MOb is ready to send a data or a remote frame when the MOb configuration is set (CONMOB).3. Then, the CAN

1768209A–AVR–08/09ATmega16M1/32M1/64M11. MObs in frame buffer receive mode need to be initialized as MObs in standard receive mode.2. The MObs are rea

1778209A–AVR–08/09ATmega16M1/32M1/64M120.6.4 MOb PageEvery MOb is mapped into a page to save place. The page number is the MOb number. Thispage number

1788209A–AVR–08/09ATmega16M1/32M1/64M120.7.1 PrescalerAn 8-bit prescaler is initialized by CANTCON register. It receives the clkIO frequency divided b

1798209A–AVR–08/09ATmega16M1/32M1/64M1Figure 20-12. Line Error ModeNote: More than one REC/TEC change may apply during a given message transfer.20.8.2

188209A–AVR–08/09ATmega16M1/32M1/64M18. Memories8.1 OverviewThis section describes the different memories in the ATmega16M1/32M1/64M1. The AVR archi-t

1808209A–AVR–08/09ATmega16M1/32M1/64M1Figure 20-13. Error Detection Procedures in a Data Frame20.8.3 Error SettingThe CAN channel can detect some erro

1818209A–AVR–08/09ATmega16M1/32M1/64M1Figure 20-14. CAN Controller Interrupt Structure20.9.2 Interrupt BehaviorWhen an interrupt occurs, an interrupt

1828209A–AVR–08/09ATmega16M1/32M1/64M120.10 Register DescriptionFigure 20-15. Registers OrganizationGeneral ControlGeneral StatusGeneral InterruptBit

1838209A–AVR–08/09ATmega16M1/32M1/64M120.10.1 CANGCON – CAN General Control Register• Bit 7 – ABRQ: Abort RequestThis is not an auto resettable bit.–

1848209A–AVR–08/09ATmega16M1/32M1/64M1– 0 - standby mode: The on-going transmission (if exists) is normally terminated and the CAN channel is frozen (

1858209A–AVR–08/09ATmega16M1/32M1/64M1• Bit 2 – ENFG: Enable FlagThis flag does not generate an interrupt.– 0 - CAN controller disable: because an ena

1868209A–AVR–08/09ATmega16M1/32M1/64M1– 0 - no interrupt.– 1 - burst receive interrupt: set when the frame buffer receive is completed.• Bit 3 – SERG:

1878209A–AVR–08/09ATmega16M1/32M1/64M1• Bit 4 – ENTX: Enable Transmit Interrupt– 0 - interrupt disabled.– 1- transmit interrupt enabled.• Bit 3 – ENER

1888209A–AVR–08/09ATmega16M1/32M1/64M120.10.6 CANIE2 and CANIE1 – CAN Enable Interrupt MOb Registers• Bits 5:0 - IEMOB[5:0]: Interrupt Enable by MOb–

1898209A–AVR–08/09ATmega16M1/32M1/64M1• Bit 6:1 – BRP[5:0]: Baud Rate PrescalerThe period of the CAN controller system clock Tscl is programmable and

198209A–AVR–08/09ATmega16M1/32M1/64M18.3 SRAM Data MemoryFigure 8-2 shows how the ATmega16M1/32M1/64M1 SRAM Memory is organized.The ATmega16M1/32M1/64

1908209A–AVR–08/09ATmega16M1/32M1/64M120.10.10 CANBT3 – CAN Bit Timing Register 3• Bit 7– Res: ReservedThis bit is reserved for future use. For compat

1918209A–AVR–08/09ATmega16M1/32M1/64M120.10.12 CANTIML and CANTIMH – CAN Timer Registers• Bits 15:0 - CANTIM[15:0]: CAN Timer CountCAN timer counter r

1928209A–AVR–08/09ATmega16M1/32M1/64M1• Bit 3:0 – CGP[3:0]: CAN General Purpose BitsThese bits can be pre-programmed to match with the wanted configur

1938209A–AVR–08/09ATmega16M1/32M1/64M1• Bit 4 – BERR: Bit Error (Only in Transmission)This flag can generate an interrupt. It must be cleared using a

1948209A–AVR–08/09ATmega16M1/32M1/64M1These bits are not cleared once the communication is performed. The user must re-write theconfiguration to enabl

1958209A–AVR–08/09ATmega16M1/32M1/64M1• Bit 31:21 – IDT[10:0]: Identifier TagIdentifier field of the remote or data frame to send.This field is update

1968209A–AVR–08/09ATmega16M1/32M1/64M120.11.4 CANIDM1, CANIDM2, CANIDM3, and CANIDM4 – CAN Identifier Mask RegistersV2.0 part AV2.0 part BV2.0 part A•

1978209A–AVR–08/09ATmega16M1/32M1/64M1• Bit 2 – RTRMSK: Remote Transmission Request Mask– 0 - comparison true forced– 1 - bit comparison enabled.• Bit

1988209A–AVR–08/09ATmega16M1/32M1/64M1Table 20-2. Examples of CAN Baud Rate Settings for Commonly Frequencies fCLKIO(MHz)CANRate(Kbps)Description Segm

1998209A–AVR–08/09ATmega16M1/32M1/64M1Note: 1. See Section 20.5.3 “Baud Rate” on page 173.2. See Section • “Bit 0 – SMP: Sample Point(s)” on page 190

28209A–AVR–08/09ATmega16M1/32M1/64M11. Pin ConfigurationsFigure 1-1. ATmega16M1/32M1/64M1 TQFP32/QFN32 (7*7 mm) Package.123456782423222120191817(PCINT

208209A–AVR–08/09ATmega16M1/32M1/64M1Figure 8-3. On-chip Data SRAM Access Cycles8.4 EEPROM Data MemoryThe ATmega16M1/32M1/64M1 contains 512B/1K/2K byt

2008209A–AVR–08/09ATmega16M1/32M1/64M121. LIN / UART - Local Interconnect Network Controller or UART21.1 Features21.1.1 LIN•Hardware Implementation of

2018209A–AVR–08/09ATmega16M1/32M1/64M121.3 LIN Protocol21.3.1 Master and SlaveA LIN cluster consists of one master task and several slave tasks. A mas

2028209A–AVR–08/09ATmega16M1/32M1/64M121.3.3 Data TransportTwo types of data may be transported in a frame; signals or diagnostic messages.• SignalsSi

2038209A–AVR–08/09ATmega16M1/32M1/64M121.4.1 LIN OverviewThe LIN/UART controller is designed to match as closely as possible to the LIN software appli

2048209A–AVR–08/09ATmega16M1/32M1/64M121.4.3 LIN/UART Controller StructureFigure 21-4. LIN/UART Controller Block Diagram21.4.4 LIN/UART Command Overvi

2058209A–AVR–08/09ATmega16M1/32M1/64M121.4.5 Enable / DisableSetting the LENA bit in LINCR register enables the LIN/UART controller. To disable theLIN

2068209A–AVR–08/09ATmega16M1/32M1/64M121.4.6.2 Tx Header FunctionIn accordance with the LIN protocol, only the master task must enable this function.

2078209A–AVR–08/09ATmega16M1/32M1/64M121.4.6.4 Handling Data of LIN responseA FIFO data buffer is used for data of the LIN response. After setting all

2088209A–AVR–08/09ATmega16M1/32M1/64M121.5 LIN / UART Description21.5.1 ResetThe AVR core reset logic signal also resets the LIN/UART controller. Anot

2098209A–AVR–08/09ATmega16M1/32M1/64M1The LIN configuration is independent of the programmed LIN protocol.The listening mode connects the internal Tx

218209A–AVR–08/09ATmega16M1/32M1/64M18.4.2 Preventing EEPROM CorruptionDuring periods of low VCC, the EEPROM data can be corrupted because the supply

2108209A–AVR–08/09ATmega16M1/32M1/64M1When the busy signal is set, some registers are locked, user writing is not allowed:• “LIN Control Register” - L

2118209A–AVR–08/09ATmega16M1/32M1/64M1The new LBT[5..0] value will be used up to the end of the response. Then, the LBT[5..0] will bereset to 32 for t

2128209A–AVR–08/09ATmega16M1/32M1/64M121.5.7.2 Data Length in LIN 1.3• LRXDL and LTXDL fields are both hardware updated before setting LIDOK by decodi

2138209A–AVR–08/09ATmega16M1/32M1/64M1• The user initializes LTXDL field before setting the Tx Response command,• After setting the Tx Response comman

2148209A–AVR–08/09ATmega16M1/32M1/64M121.5.9 xxERR FlagsLERR bit of the LINSIR register is an logical ‘OR’ of all the bits of LINERR register (see Se

2158209A–AVR–08/09ATmega16M1/32M1/64M1Figure 21-12. LIN timing and frame time-out 21.5.11 Break-in-dataAccording to the LIN protocol, the LIN/UART con

2168209A–AVR–08/09ATmega16M1/32M1/64M121.5.13 InterruptsAs shown in Figure 21-13 on page 216, the four communication flags of the LINSIR register are

2178209A–AVR–08/09ATmega16M1/32M1/64M121.5.15 Data Management21.5.15.1 LIN FIFO Data BufferTo preserve register allocation, the LIN data buffer is see

2188209A–AVR–08/09ATmega16M1/32M1/64M110. LINDAT:- All bits are in R/W accessible,- Note that LAINC has no more effect on the auto-incrementation and

2198209A–AVR–08/09ATmega16M1/32M1/64M1• Bit 3 - LENA: Enable– 0 = Disable (both LIN and UART modes),– 1 = Enable (both LIN and UART modes).• Bit 2:0 -

228209A–AVR–08/09ATmega16M1/32M1/64M18.7 Register Description8.7.1 EEARH and EEARL – The EEPROM Address Registers• Bits 15:10 – Res: ReservedThese bit

2208209A–AVR–08/09ATmega16M1/32M1/64M1The user clears this bit by writing 1 in order to reset this interrupt. Resetting LERR alsoresets all LINERR bit

2218209A–AVR–08/09ATmega16M1/32M1/64M1– 1 = Transmit performed interrupt enabled.• Bit 0 - LENRXOK: Enable Receive Performed Interrupt– 0 = Receive pe

2228209A–AVR–08/09ATmega16M1/32M1/64M1This bit is cleared when LERR bit in LINSIR is cleared.• Bit 0 - LBERR: Bit Error Flag–0 = no error,– 1 = Bit er

2238209A–AVR–08/09ATmega16M1/32M1/64M1• Bits 7:4 - LTXDL[3:0]: LIN Transmit Data LengthIn LIN mode, this field gives the number of bytes to be transmi

2248209A–AVR–08/09ATmega16M1/32M1/64M1• Bits 7:4 - Res: ReservedThese bits are reserved for future use. For compatibility with future devices, they mu

2258209A–AVR–08/09ATmega16M1/32M1/64M122. ADC – Analog to Digital Converter22.1 Features• 10-bit Resolution• 0.5 LSB Integral Non-linearity• ± 2 LSB A

2268209A–AVR–08/09ATmega16M1/32M1/64M1Figure 22-1. Analog to Digital Converter Block SchematicMUX2 MUX1 MUX0MUX3REFS1 REFS0 ADLAR MUX4 ADPS2 ADPS1 ADP

2278209A–AVR–08/09ATmega16M1/32M1/64M122.2 OperationThe ADC converts an analog input voltage to a 10-bit digital value through successive approxi-mati

2288209A–AVR–08/09ATmega16M1/32M1/64M1Figure 22-2. ADC Auto Trigger LogicUsing the ADC Interrupt Flag as a trigger source makes the ADC start a new co

2298209A–AVR–08/09ATmega16M1/32M1/64M1When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversionstarts at the followi

238209A–AVR–08/09ATmega16M1/32M1/64M1EEWE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to0b00 unless the EEP

2308209A–AVR–08/09ATmega16M1/32M1/64M1Figure 22-6. ADC Timing Diagram, Auto Triggered ConversionFigure 22-7. ADC Timing Diagram, Free Running Conversi

2318209A–AVR–08/09ATmega16M1/32M1/64M1If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Specialcare must be t

2328209A–AVR–08/09ATmega16M1/32M1/64M1AREF pin is alternate function with ISRC Current Source output. When current source isselected, the AREF pin is

2338209A–AVR–08/09ATmega16M1/32M1/64M1to remove high frequency components with a low-pass filter before applying the signals asinputs to the ADC.Figur

2348209A–AVR–08/09ATmega16M1/32M1/64M122.6.3 Offset Compensation SchemesThe gain stage has a built-in offset cancellation circuitry that nulls the off

2358209A–AVR–08/09ATmega16M1/32M1/64M1Figure 22-11. Gain Error• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is th

2368209A–AVR–08/09ATmega16M1/32M1/64M1Figure 22-13. Differential Non-linearity (DNL)• Quantization Error: Due to the quantization of the input voltage

2378209A–AVR–08/09ATmega16M1/32M1/64M1(ADC9 in ADCH). If the bit is one, the result is negative, and if this bit is zero, the result is posi-tive. Fig

2388209A–AVR–08/09ATmega16M1/32M1/64M1Example 1:– ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result) – Voltage on ADC3 is 300

2398209A–AVR–08/09ATmega16M1/32M1/64M1The measured voltage has a linear relationship to the temperature as described in Table 22-3 onpage 239. The vol

248209A–AVR–08/09ATmega16M1/32M1/64M1When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft-ware can poll this bit

2408209A–AVR–08/09ATmega16M1/32M1/64M1Amplified conversions can be synchronized to PSC events (See “Synchronization SourceDescription in One Ramp Mode

2418209A–AVR–08/09ATmega16M1/32M1/64M1Figure 22-16. Amplifier synchronization timing diagramWith change on analog input signalValid sampleDelta V4th s

2428209A–AVR–08/09ATmega16M1/32M1/64M1Figure 22-17. Amplifier synchronization timing diagramADSC is set when the amplifier output is changing due to t

2438209A–AVR–08/09ATmega16M1/32M1/64M1Figure 22-18. Amplifiers block diagramAMP0TS1 AMP0TS0AMP0EN AMP0IS AMP0G1 AMP0G0AMP0CSR+-SAMPLINGAMP0+AMP0-Towar

2448209A–AVR–08/09ATmega16M1/32M1/64M122.10 Register DescriptionThe ADC of the ATmega16M1/32M1/64M1 is controlled through 3 different registers. The A

2458209A–AVR–08/09ATmega16M1/32M1/64M122.10.2 Bit 4: 0 – MUX[4:0]: ADC Channel Selection BitsThese 4 bits determine which analog inputs are connected

2468209A–AVR–08/09ATmega16M1/32M1/64M1• Bit 6 – ADSC: ADC Start Conversion BitSet this bit to start a conversion in single conversion mode or to start

2478209A–AVR–08/09ATmega16M1/32M1/64M1• Bit 6 – ISRCEN: Current Source EnableSet this bit to source a 100µA current to the AREF pin.Clear this bit to

2488209A–AVR–08/09ATmega16M1/32M1/64M1Consequently, in 10-bit configuration, the ADCL register must be read first before the ADCH. Nevertheless, to wo

2498209A–AVR–08/09ATmega16M1/32M1/64M1• Bit 6:0 – ADC10D..8D, ACMP0D, ACMP1D, ACMP3D, AMP0PD, AMP0ND, AMP1PD, AMP1ND, AMP2PD:ADC10..8, ACMP0, ACMP1, A

258209A–AVR–08/09ATmega16M1/32M1/64M1Assembly Code ExampleEEPROM_write:; Wait for completion of previous writesbic EECR,EEWErjmp EEPROM_write ; Set

2508209A–AVR–08/09ATmega16M1/32M1/64M122.10.9 AMP1CSR – Amplifier 1 Control and Status register• Bit 7 – AMP1EN: Amplifier 1 Enable Bit Set this bit t

2518209A–AVR–08/09ATmega16M1/32M1/64M1• Bit 3 – AMPCMP1: Amplifier 1 - Comparator 1 connectionSet this bit to connect the amplifier 1 to the comparato

2528209A–AVR–08/09ATmega16M1/32M1/64M1These 2 bits determine the gain of the amplifier 2.The different setting are shown in Table 22-12.To ensure an a

2538209A–AVR–08/09ATmega16M1/32M1/64M123. ISRC - Current Source23.1 Features• 100µA Constant current source• ± 2% Absolute AccuracyThe ATmega16M1/32M1

2548209A–AVR–08/09ATmega16M1/32M1/64M1ATmega16M1/32M1/64M1 proposes to have an external resistor used in conjunction with theCurrent Source. The devic

2558209A–AVR–08/09ATmega16M1/32M1/64M123.2.2 Voltage Reference for External DevicesAn external resistor used in conjunction with the Current Source ca

2568209A–AVR–08/09ATmega16M1/32M1/64M124. AC – Analog Comparator24.1 Features• 4 Analog Comparators• High Speed Clocked Comparators• +/-30mV Hysteresy

2578209A–AVR–08/09ATmega16M1/32M1/64M1Figure 24-1. Analog Comparator Block Diagram(1)(2)Notes: 1. ADC multiplexer output: see Table 22-5 on page 245.2

2588209A–AVR–08/09ATmega16M1/32M1/64M124.3 Use of ADC AmplifiersThanks to AMPCMP0 configuration bit, Comparator 0 positive input can be connected to A

2598209A–AVR–08/09ATmega16M1/32M1/64M124.4.2 AC1CON – Analog Comparator 1Control Register• Bit 7– AC1EN: Analog Comparator 1 Enable Bit Set this bit t

268209A–AVR–08/09ATmega16M1/32M1/64M1The next code examples show assembly and C functions for reading the EEPROM. The exam-ples assume that interrupts

2608209A–AVR–08/09ATmega16M1/32M1/64M1In case ICES1 bit (“TCCR1B – Timer/Counter1 Control Register B” on page 126) is set high, therising edge of AC1O

2618209A–AVR–08/09ATmega16M1/32M1/64M1• Bit 3 – Res: ReservedThis bit is reserved and will always read as zero.• Bit 2:0– AC2M[2:0]: Analog Comparator

2628209A–AVR–08/09ATmega16M1/32M1/64M1.• Bit 3 – Res: ReservedThis bit isreserved and will always read as zero.• Bit 2:0– AC3M[2:0]: Analog Comparator

2638209A–AVR–08/09ATmega16M1/32M1/64M1AC2IE in AC2CON register is set. Anyway, this bit is cleared by writing a logical one on it.This bit can also be

2648209A–AVR–08/09ATmega16M1/32M1/64M124.4.7 DIDR1 – Digital Input Disable Register 1• Bit 5, 2, 1: ACMP0D, ACMP1PD, ACMP3PD:ACMP0, ACMP1P, ACMP3P Dig

2658209A–AVR–08/09ATmega16M1/32M1/64M125. DAC – Digital to Analog Converter25.1 Features• 10 bits resolution• 8 bits linearity• +/- 0.5 LSB accuracy b

2668209A–AVR–08/09ATmega16M1/32M1/64M1Figure 25-1. Digital to Analog Converter Block Schematic25.3 OperationThe Digital to Analog Converter generates

2678209A–AVR–08/09ATmega16M1/32M1/64M125.4 Starting a ConversionThe DAC is configured thanks to the DACON register. As soon as the DAEN bit in DACON r

2688209A–AVR–08/09ATmega16M1/32M1/64M1• Bit 6:4 – DATS[2:0]: DAC Trigger Selection bitsThese bits are only necessary in case the DAC works in auto tri

2698209A–AVR–08/09ATmega16M1/32M1/64M125.5.2.1 DALA = 025.5.2.2 DALA = 1To work with the 10-bit DAC, two registers have to be updated. In order to avo

278209A–AVR–08/09ATmega16M1/32M1/64M19. System Clock and their Distribution9.1 Clock Systems and their DistributionFigure 9-1 presents the principal c

2708209A–AVR–08/09ATmega16M1/32M1/64M126. debugWIRE On-chip Debug System26.1 Features• Complete Program Flow Control• Emulates All On-chip Functions,

2718209A–AVR–08/09ATmega16M1/32M1/64M1When designing a system where debugWIRE will be used, the following observations must bemade for correct operati

2728209A–AVR–08/09ATmega16M1/32M1/64M127. Boot Loader Support – Read-While-Write Self-Programming • Features• Read-While-Write Self-Programming• Flexi

2738209A–AVR–08/09ATmega16M1/32M1/64M127.3 Read-While-Write and No Read-While-Write Flash SectionsWhether the CPU supports Read-While-Write or if the

2748209A–AVR–08/09ATmega16M1/32M1/64M1Figure 27-1. Read-While-Write vs. No Read-While-WriteRead-While-Write(RWW) SectionNo Read-While-Write (NRWW) Sec

2758209A–AVR–08/09ATmega16M1/32M1/64M1Figure 27-2. Memory SectionsNote: 1. The parameters in the figure above are given in Table 27-10 on page 285.27.

2768209A–AVR–08/09ATmega16M1/32M1/64M1Note: 1. “1” means unprogrammed, “0” means programmedNote: 1. “1” means unprogrammed, “0” means programmed27.5 E

2778209A–AVR–08/09ATmega16M1/32M1/64M1Note: 1. “1” means unprogrammed, “0” means programmed27.6 Addressing the Flash During Self-ProgrammingThe Z-poin

2788209A–AVR–08/09ATmega16M1/32M1/64M1Figure 27-3. Addressing the Flash During SPM(1)Note: 1. The different variables used in Figure 27-3 are listed i

2798209A–AVR–08/09ATmega16M1/32M1/64M127.7.1 Performing Page Erase by SPMTo execute Page Erase, set up the address in the Z-pointer, write “X0000011”

288209A–AVR–08/09ATmega16M1/32M1/64M19.1.4 PLL Clock – clkPLLThe PLL clock allows the fast peripherals to be clocked directly from a 64/32 MHz clock.

2808209A–AVR–08/09ATmega16M1/32M1/64M1the RWWSRE. See “Simple Assembly Code Example for a Boot Loader” on page 282 for anexample.27.7.7 Setting the Bo

2818209A–AVR–08/09ATmega16M1/32M1/64M1the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below.Refer to Table 2

2828209A–AVR–08/09ATmega16M1/32M1/64M11. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock bits to prevent any

2838209A–AVR–08/09ATmega16M1/32M1/64M1brne Wrloop; execute Page Writesubi ZL, low(PAGESIZEB) ;restore pointersbci ZH, high(PAGESIZEB) ;not required fo

2848209A–AVR–08/09ATmega16M1/32M1/64M127.7.14 ATmega16M1 - 16K - Flash Boot Loader ParametersIn Table 27-10 through Table 27-12, the parameters used i

2858209A–AVR–08/09ATmega16M1/32M1/64M127.7.15 ATmega32M1 - 32K - Flash Boot Loader ParametersIn Table 27-10 through Table 27-12, the parameters used i

2868209A–AVR–08/09ATmega16M1/32M1/64M127.7.16 ATmega64M1 - 64K - Flash Boot Loader ParametersIn Table 27-10 through Table 27-12, the parameters used i

2878209A–AVR–08/09ATmega16M1/32M1/64M127.8 Register Description27.8.1 SPMCSR – Store Program Memory Control and Status RegisterThe Store Program Memor

2888209A–AVR–08/09ATmega16M1/32M1/64M1destination register. See “Reading the Fuse and Lock Bits from Software” on page 280 fordetails.• Bit 2 – PGWRT:

2898209A–AVR–08/09ATmega16M1/32M1/64M128. Memory Programming28.1 Program And Data Memory Lock BitsThe ATmega16M1/32M1/64M1 provides six Lock bits whic

298209A–AVR–08/09ATmega16M1/32M1/64M19.3 Default Clock SourceThe device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default

2908209A–AVR–08/09ATmega16M1/32M1/64M1Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.2. “1” means unprogrammed,

2918209A–AVR–08/09ATmega16M1/32M1/64M1Note: 1. See Table 29-3 on page 313 for BODLEVEL Fuse decoding.28.3 PSC Output Behavior During ResetFor external

2928209A–AVR–08/09ATmega16M1/32M1/64M1Note: 1. See “Alternate Functions of Port C” on page 75 for description of RSTDISBL Fuse.2. The SPIEN Fuse is no

2938209A–AVR–08/09ATmega16M1/32M1/64M1Notes: 1. The default value of SUT1..0 results in maximum start-up time for the default clock source. See Table

2948209A–AVR–08/09ATmega16M1/32M1/64M128.6 Page Size28.7 Parallel Programming Parameters, Pin Mapping, and CommandsThis section describes how to paral

2958209A–AVR–08/09ATmega16M1/32M1/64M1Figure 28-1. Parallel ProgrammingTable 28-11. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O Func

2968209A–AVR–08/09ATmega16M1/32M1/64M128.8 Serial Programming Pin Mapping28.9 Parallel Programming28.9.1 Enter Programming ModeThe following algorithm

2978209A–AVR–08/09ATmega16M1/32M1/64M1If the rise time of the Vcc is unable to fulfill the requirements listed above, the following alterna-tive algor

2988209A–AVR–08/09ATmega16M1/32M1/64M14. Give XTAL1 a positive pulse. This loads the command.B. Load Address Low byte1. Set XA1, XA0 to “00”. This ena

2998209A–AVR–08/09ATmega16M1/32M1/64M1Figure 28-2. Addressing the Flash Which is Organized in Pages(1)Note: 1. PCPAGE and PCWORD are listed in Table 2

38209A–AVR–08/09ATmega16M1/32M1/64M11.1 Pin Descriptions Table 1-1. Pin out description QFN32 Pin Number Mnemonic Type Name, Function & Alternate

308209A–AVR–08/09ATmega16M1/32M1/64M1Notes: 1. The frequency ranges are preliminary values. Actual values are TBD.2. This option should not be used wi

3008209A–AVR–08/09ATmega16M1/32M1/64M15. E: Latch data (give PAGEL a positive pulse).K: Repeat 3 through 5 until the entire buffer is filled.L: Progra

3018209A–AVR–08/09ATmega16M1/32M1/64M128.9.8 Programming the Fuse Low BitsThe algorithm for programming the Fuse Low bits is as follows (refer to “Pro

3028209A–AVR–08/09ATmega16M1/32M1/64M11. A: Load Command “0010 0000”.2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is prog

3038209A–AVR–08/09ATmega16M1/32M1/64M11. A: Load Command “0000 1000”.2. B: Load Address Low Byte, 0x00.3. Set OE to “0”, and BS1 to “1”. The Calibrati

3048209A–AVR–08/09ATmega16M1/32M1/64M1Figure 28-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1)Not

3058209A–AVR–08/09ATmega16M1/32M1/64M1Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands.2. tW

3068209A–AVR–08/09ATmega16M1/32M1/64M128.10.1 Serial Programming AlgorithmWhen writing serial data to the ATmega16M1/32M1/64M1, data is clocked on the

3078209A–AVR–08/09ATmega16M1/32M1/64M128.10.3 Data Polling EEPROMWhen a new byte has been written and is being programmed into EEPROM, reading theaddr

3088209A–AVR–08/09ATmega16M1/32M1/64M1Note: a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x

3098209A–AVR–08/09ATmega16M1/32M1/64M129. Electrical Characteristics29.1 Absolute Maximum Ratings*29.2 DC CharacteristicsOperating Temperature...

318209A–AVR–08/09ATmega16M1/32M1/64M19.5 Calibrated Internal RC OscillatorBy default, the Internal RC OScillator provides an approximate 8.0 MHz clock

3108209A–AVR–08/09ATmega16M1/32M1/64M1Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low2. “Min” means the lowest v

3118209A–AVR–08/09ATmega16M1/32M1/64M15. Minimum VCC for Power-down is 2.5V.6. The Analog Comparator Propogation Delay equals 1 comparator clock plus

3128209A–AVR–08/09ATmega16M1/32M1/64M129.4 Clock Characteristics29.4.1 Calibrated Internal RC Oscillator Accuracy29.5 External Clock Drive Characteris

3138209A–AVR–08/09ATmega16M1/32M1/64M129.6 System and Reset CharacteristicsNotes: 1. Values are guidelines only2. Before rising, the supply has to be

3148209A–AVR–08/09ATmega16M1/32M1/64M129.7 PLL Characteristics.Note: While connected to external clock or external oscillator, PLL Input Frequency mus

3158209A–AVR–08/09ATmega16M1/32M1/64M1Figure 29-3. SPI Interface Timing Requirements (Master Mode)Figure 29-4. SPI Interface Timing Requirements (Slav

3168209A–AVR–08/09ATmega16M1/32M1/64M129.9 ADC Characteristics Table 29-4. ADC Characteristics - TA = -40°C to +85°C, VCC = 2.7V to 5.5V (unless othe

3178209A–AVR–08/09ATmega16M1/32M1/64M1Zero Error (Offset)Single Ended ConversionVCC = 4.5V, VREF = 4VADC clock = 1MHz-4 0 LSBSingle Ended ConversionVC

3188209A–AVR–08/09ATmega16M1/32M1/64M129.10 Parallel Programming CharacteristicsFigure 29-5. Parallel Programming Timing, Including some General Timin

3198209A–AVR–08/09ATmega16M1/32M1/64M1Figure 29-7. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1)Not

328209A–AVR–08/09ATmega16M1/32M1/64M19.6 PLL9.6.1 Internal PLLThe internal PLL in ATmega16M1/32M1/64M1 generates a clock frequency that is 64x multipl

3208209A–AVR–08/09ATmega16M1/32M1/64M1Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands.2. tW

3218209A–AVR–08/09ATmega16M1/32M1/64M130. Typical Characteristics – TBD

3228209A–AVR–08/09ATmega16M1/32M1/64M131. Register SummaryAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page(0xFF) Reserved – – – – – –

3238209A–AVR–08/09ATmega16M1/32M1/64M1(0xBE) Reserved – – – – – – – –(0xBD) Reserved – – – – – – – –(0xBC)(5)PIFR – – – – PEV2 PEV1 PEV0 PEOP page 153

3248209A–AVR–08/09ATmega16M1/32M1/64M1(0x7C) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 page 244(0x7B) ADCSRB ADHSM ISRCEN AREFEN – ADTS3 ADTS2 ADT

3258209A–AVR–08/09ATmega16M1/32M1/64M1Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/

3268209A–AVR–08/09ATmega16M1/32M1/64M132. Instruction Set SummaryMnemonics Operands Description Operation Flags #ClocksARITHMETIC AND LOGIC INSTRUCTIO

3278209A–AVR–08/09ATmega16M1/32M1/64M1BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2BRID k Branch if Interrupt Disable

3288209A–AVR–08/09ATmega16M1/32M1/64M1Note: 1. These Instructions are only available in “16K and 32K parts”POP Rd Pop Register from Stack Rd ← STACK N

3298209A–AVR–08/09ATmega16M1/32M1/64M133. Errata 33.1 Errata ATmega16M1The revision letter in this section refers to revisions of the ATmega16M1 devic

338209A–AVR–08/09ATmega16M1/32M1/64M1Figure 9-3. PCK Clocking System9.7 128 kHz Internal OscillatorThe 128 kHz internal Oscillator is a low power Osci

3308209A–AVR–08/09ATmega16M1/32M1/64M134. Ordering Information34.1 ATmega16M1Note: All packages are Pb free, fully LHFSpeed Power Supply Ordering Code

3318209A–AVR–08/09ATmega16M1/32M1/64M134.2 ATmega32M1Note: All packages are Pb free, fully LHFSpeed Power Supply Ordering Code Package Operation Range

3328209A–AVR–08/09ATmega16M1/32M1/64M134.3 ATmega64M1Note: All packages are Pb free, fully LHFSpeed Power Supply Ordering Code Package Operation Range

3338209A–AVR–08/09ATmega16M1/32M1/64M135. Packaging Information35.1 32A 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 32A, 32-lead,

3348209A–AVR–08/09ATmega16M1/32M1/64M135.2 32M1-A 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body

3358209A–AVR–08/09ATmega16M1/32M1/64M136. Datasheet Revision HistoryPlease note that the referring page numbers in this section are referred to this d

i8209A–AVR–08/09ATmega16M1/32M1/64M1Table of ContentsFeatures ...

ii8209A–AVR–08/09ATmega16M1/32M1/64M19.5 Calibrated Internal RC Oscillator ...319.6

iii8209A–AVR–08/09ATmega16M1/32M1/64M115 8-bit Timer/Counter0 with PWM ... 8615.1 Features ..

iv8209A–AVR–08/09ATmega16M1/32M1/64M118.8 Signal Description ...

348209A–AVR–08/09ATmega16M1/32M1/64M1When this clock source is selected, start-up times are determined by the SUT Fuses as shown inTable 9-9.When appl

v8209A–AVR–08/09ATmega16M1/32M1/64M122 ADC – Analog to Digital Converter ... 22522.1 Features ...

vi8209A–AVR–08/09ATmega16M1/32M1/64M127.1 Overview ...

vii8209A–AVR–08/09ATmega16M1/32M1/64M133.1 Errata ATmega16M1 ...329

8209A–AVR–08/09© 2009 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof AVR®, and others are registered trademarks o

358209A–AVR–08/09ATmega16M1/32M1/64M11. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero.2. Within four

368209A–AVR–08/09ATmega16M1/32M1/64M1When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator isstarted as PLL refer

378209A–AVR–08/09ATmega16M1/32M1/64M11001 Reserved1010 Reserved1011 Reserved1100 Reserved1101 Reserved1110 Reserved1111 ReservedTable 9-10. Clock Pres

388209A–AVR–08/09ATmega16M1/32M1/64M110. Power Management and Sleep Modes10.1 OverviewSleep modes enable the application to shut down unused modules i

398209A–AVR–08/09ATmega16M1/32M1/64M1setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This willreduce power consumptio

48209A–AVR–08/09ATmega16M1/32M1/64M13 PC1 I/OPSCIN1 (PSC Digital Input 1) OC1B (Timer 1 Output Compare B)SS_A (Alternate SPI Slave Select)PCINT9 (Pin

408209A–AVR–08/09ATmega16M1/32M1/64M1Module shutdown can be used in Idle mode and Active mode to significantly reduce the overallpower consumption. In

418209A–AVR–08/09ATmega16M1/32M1/64M1the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device willbe disabled. T

428209A–AVR–08/09ATmega16M1/32M1/64M1• Bit 1 – SE: Sleep EnableThe SE bit must be written to logic one to make the MCU enter the sleep mode when the S

438209A–AVR–08/09ATmega16M1/32M1/64M111. System Control and Reset11.1 Resetting the AVRDuring reset, all I/O Registers are set to their initial values

448209A–AVR–08/09ATmega16M1/32M1/64M1Figure 11-1. Reset Logic11.2.1 Power-on ResetA Power-on Reset (POR) pulse is generated by an On-chip detection ci

458209A–AVR–08/09ATmega16M1/32M1/64M1Figure 11-3. MCU Start-up, RESET Extended Externally11.2.2 External ResetAn External Reset is generated by a low

468209A–AVR–08/09ATmega16M1/32M1/64M1Figure 11-5. Brown-out Reset During Operation11.2.4 Watchdog ResetWhen the Watchdog times out, it will generate a

478209A–AVR–08/09ATmega16M1/32M1/64M11. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).2. When the bandgap reference is connected t

488209A–AVR–08/09ATmega16M1/32M1/64M1expires. This is typically used to prevent system hang-up in case of runaway code. The thirdmode, Interrupt and S

498209A–AVR–08/09ATmega16M1/32M1/64M1Note: 1. The example code assumes that the part specific header file is included.Note: If the Watchdog is acciden

58209A–AVR–08/09ATmega16M1/32M1/64M1Note: 1. Only for Atmega32M1/64M1.2. On the engineering samples, the ACMPN3 alternate function is not located on P

508209A–AVR–08/09ATmega16M1/32M1/64M1Note: 1. The example code assumes that the part specific header file is included.Note: The Watchdog Timer should

518209A–AVR–08/09ATmega16M1/32M1/64M111.5 Register Description11.5.1 MCUSR – MCU Status RegisterThe MCU Status Register provides information on which

528209A–AVR–08/09ATmega16M1/32M1/64M1and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is use-ful for keeping the Watc

538209A–AVR–08/09ATmega16M1/32M1/64M1.Table 11-2. Watchdog Timer Prescale SelectWDP3 WDP2 WDP1 WDP0Number of WDT Oscillator CyclesTypical Time-out at

548209A–AVR–08/09ATmega16M1/32M1/64M112. InterruptsThis section describes the specifics of the interrupt handling as performed inATmega16M1/32M1/64M1.

558209A–AVR–08/09ATmega16M1/32M1/64M1Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see “Boo

568209A–AVR–08/09ATmega16M1/32M1/64M10x01C jmp TIM1_OVF ; Timer1 Overflow Handler0x01E jmp TIM0_COMPA ; Timer0 Compare A Handler0x020 jmp TIM0_COMPB ;

578209A–AVR–08/09ATmega16M1/32M1/64M1Address Labels Code Comments.org 0x0020x002 jmp ANA_COMP_0 ; Analog Comparator 0 Handler0x004 jmp ANA_COMP_1 ; An

588209A–AVR–08/09ATmega16M1/32M1/64M112.2 Register Description12.2.1 MCUCR – MCU Control Register• Bit 1 – IVSEL: Interrupt Vector SelectWhen the IVSE

598209A–AVR–08/09ATmega16M1/32M1/64M1Assembly Code ExampleMove_interrupts:; Enable change of Interrupt Vectorsldi r16, (1<<IVCE)out MCUCR, r16

68209A–AVR–08/09ATmega16M1/32M1/64M12.1 Block DiagramFigure 2-1. Block DiagramThe AVR core combines a rich instruction set with 32 general purpose wor

608209A–AVR–08/09ATmega16M1/32M1/64M113. External InterruptsThe External Interrupts are triggered by the INT3:0 pins or any of the PCINT23:0 pins. Obs

618209A–AVR–08/09ATmega16M1/32M1/64M113.2 Register Description13.2.1 EICRA – External Interrupt Control Register AThe External Interrupt Control Regis

628209A–AVR–08/09ATmega16M1/32M1/64M113.2.3 EIFR – External Interrupt Flag Register• Bit 7:4 – Res: ReservedThese bits are reserved and will always re

638209A–AVR–08/09ATmega16M1/32M1/64M113.2.5 PCIFR – Pin Change Interrupt Flag Register• Bit 7:4 - Res: ReservedThese bits are reserved and will always

648209A–AVR–08/09ATmega16M1/32M1/64M113.2.7 PCMSK2 – Pin Change Mask Register 2• Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23:16Each PCINT23:16-bit

658209A–AVR–08/09ATmega16M1/32M1/64M114. I/O-Ports14.1 OverviewAll AVR ports have true Read-Modify-Write functionality when used as general digital I/

668209A–AVR–08/09ATmega16M1/32M1/64M114.2 Ports as General Digital I/OThe ports are bi-directional I/O ports with optional internal pull-ups. Figure 1

678209A–AVR–08/09ATmega16M1/32M1/64M1If PORTxn is written logic one when the pin is configured as an output pin, the port pin is drivenhigh (one). If

688209A–AVR–08/09ATmega16M1/32M1/64M1Figure 14-3. Synchronization when Reading an Externally Applied Pin valueConsider the clock period starting short

698209A–AVR–08/09ATmega16M1/32M1/64M1values are read back again, but as previously discussed, a nop instruction is included to be ableto read back the

78209A–AVR–08/09ATmega16M1/32M1/64M1The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports, CAN,LIN/UART and interrupt system

708209A–AVR–08/09ATmega16M1/32M1/64M114.3 Alternate Port FunctionsMost port pins have alternate functions in addition to being general digital I/Os. F

718209A–AVR–08/09ATmega16M1/32M1/64M1The following subsections shortly describe the alternate functions for each port, and relate theoverriding signal

728209A–AVR–08/09ATmega16M1/32M1/64M114.3.1 Alternate Functions of Port BThe Port B pins with alternate functions are shown in Table 14-3.The alternat

738209A–AVR–08/09ATmega16M1/32M1/64M1PCINT6, Pin Change Interrupt 6.•ADC6/INT2/ACMPN1/AMP2-/PCINT5 – Bit 5ADC6, Analog to Digital Converter, input cha

748209A–AVR–08/09ATmega16M1/32M1/64M1Table 14-4 and Table 14-5 relates the alternate functions of Port B to the overriding signalsshown in Figure 14-5

758209A–AVR–08/09ATmega16M1/32M1/64M114.3.2 Alternate Functions of Port CThe Port C pins with alternate functions are shown in Table 14-6.Note: 1. On

768209A–AVR–08/09ATmega16M1/32M1/64M1• ADC10/ACMP1/PCINT14 – Bit 6ADC10, Analog to Digital Converter, input channel 10.ACMP1, Analog Comparator 1 Posi

778209A–AVR–08/09ATmega16M1/32M1/64M1SS_A: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as aninput regardless o

788209A–AVR–08/09ATmega16M1/32M1/64M1Table 14-8. Overriding Signals for Alternate Functions in PC3..PC0Signal NamePC3/T1/RXCAN/ICP1B/PCINT11PC2/T0/TXC

798209A–AVR–08/09ATmega16M1/32M1/64M114.3.3 Alternate Functions of Port DThe Port D pins with alternate functions are shown in Table 14-9.The alternat

88209A–AVR–08/09ATmega16M1/32M1/64M12.2.5 Port D (PD7..PD0)Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for ea

808209A–AVR–08/09ATmega16M1/32M1/64M1ACMPN2, Analog Comparator 2 Negative Input. Configure the port pin as input with the internalpull-up switched off

818209A–AVR–08/09ATmega16M1/32M1/64M1OC1A, Output Compare Match A output: This pin can serve as an external output for theTimer/Counter1 Output Compar

828209A–AVR–08/09ATmega16M1/32M1/64M1 14.3.4 Alternate Functions of Port EThe Port E pins with alternate functions are shown in Table 14-12.Note: 1. O

838209A–AVR–08/09ATmega16M1/32M1/64M1XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequencycrystal Oscillator.

848209A–AVR–08/09ATmega16M1/32M1/64M114.4 Register Description14.4.1 MCUCR – MCU Control Register• Bit 4 – PUD: Pull-up DisableWhen this bit is writte

858209A–AVR–08/09ATmega16M1/32M1/64M114.4.8 PORTD – Port D Data Register14.4.9 DDRD – Port D Data Direction Register14.4.10 PIND – Port D Input Pins A

868209A–AVR–08/09ATmega16M1/32M1/64M115. 8-bit Timer/Counter0 with PWM15.1 Features• Two Independent Output Compare Units• Double Buffered Output Comp

878209A–AVR–08/09ATmega16M1/32M1/64M115.2.1 DefinitionsMany register and bit references in this section are written in general form. A lower case “n”r

888209A–AVR–08/09ATmega16M1/32M1/64M1Figure 15-2. Counter Unit Block DiagramSignal description (internal signals):count Increment or decrement TCNT0 b

898209A–AVR–08/09ATmega16M1/32M1/64M1Figure 15-3. Output Compare Unit, Block DiagramThe OCR0x Registers are double buffered when using any of the Puls

98209A–AVR–08/09ATmega16M1/32M1/64M13. DisclaimerTypical values contained in this datasheet are based on simulations and characterization ofother AVR

908209A–AVR–08/09ATmega16M1/32M1/64M1The setup of the OC0x should be performed before setting the Data Direction Register for theport pin to output. T

918209A–AVR–08/09ATmega16M1/32M1/64M1non-PWM modes refer to Table 15-2 on page 97. For fast PWM mode, refer to Table 15-3 onpage 97, and for phase cor

928209A–AVR–08/09ATmega16M1/32M1/64M1Figure 15-5. CTC Mode, Timing DiagramAn interrupt can be generated each time the counter value reaches the TOP va

938209A–AVR–08/09ATmega16M1/32M1/64M1PWM mode is shown in Figure 15-6. The TCNT0 value is in the timing diagram shown as a his-togram for illustrating

948209A–AVR–08/09ATmega16M1/32M1/64M1feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out-put Compare unit i

958209A–AVR–08/09ATmega16M1/32M1/64M1one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option isnot available for the

968209A–AVR–08/09ATmega16M1/32M1/64M1Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)Figure 15-10 shows the setting of OCF0B in

978209A–AVR–08/09ATmega16M1/32M1/64M115.9 Register Description15.9.1 TCCR0A – Timer/Counter Control Register A• Bits 7:6 – COM0A1:0: Compare Match Out

988209A–AVR–08/09ATmega16M1/32M1/64M1Table 15-4 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor-rect PWM mode.Note: 1.

998209A–AVR–08/09ATmega16M1/32M1/64M1Table 15-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor-rect PWM mode.Note: 1.