Rainbow-electronics ATtiny861_V User Manual

Features• High Performance, Low Power AVR® 8-Bit Microcontroller• Advanced RISC Architecture– 123 Powerful Instructions – Most Single Clock Cycle Exec

102588B–AVR–11/06ATtiny261/461/8615.3.1 SREG – AVR Status RegisterThe AVR Status Register – SREG – is defined as:• Bit 7 – I: Global Interrupt EnableT

1002588B–AVR–11/06ATtiny261/461/861Figure 16-9. Compare Match Output Unit, Schematic16.6.1 Compare Output Mode and Waveform GenerationThe Waveform Gen

1012588B–AVR–11/06ATtiny261/461/86116.7 Modes of OperationThe mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins,

1022588B–AVR–11/06ATtiny261/461/861toggle its logical level on each Compare Match by setting the Compare Output mode bits to tog-gle mode (COM1x1:0 =

1032588B–AVR–11/06ATtiny261/461/861Figure 16-11. Fast PWM Mode, Timing DiagramThe Timer/Counter Overflow Flag (TOV1) is set each time the counter reac

1042588B–AVR–11/06ATtiny261/461/86116.7.3 Phase and Frequency Correct PWM ModeThe Phase and Frequency Correct PWM Mode (PWMx = 1 and WGM10 = 1) provid

1052588B–AVR–11/06ATtiny261/461/861In the Phase and Frequency Correct PWM mode, the compare unit allows generation of PWMwaveforms on the OC1x pins. S

1062588B–AVR–11/06ATtiny261/461/861Output at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). TheTimer/Counter Overflow Flag

1072588B–AVR–11/06ATtiny261/461/861and, if the Override Enable bit is set, the Output Compare pin is allowed to be connected on theport pin. The Outpu

1082588B–AVR–11/06ATtiny261/461/861Figure 16-15. Timer/Counter Timing Diagram, with Prescaler (fclkT1/8)Figure 16-16. Timer/Counter Timing Diagram, Se

1092588B–AVR–11/06ATtiny261/461/861When the Fault Protection mode is enabled by the Fault Protection Enable (FPEN1) bit and achange of the logic level

112588B–AVR–11/06ATtiny261/461/8615.4 General Purpose Register FileThe Register File is optimized for the AVR Enhanced RISC instruction set. In order

1102588B–AVR–11/06ATtiny261/461/86116.10 Accessing 10-Bit RegistersIf 10-bit values are written to the TCNT1 and OCR1A/B/C/D registers, the 10-bit reg

1112588B–AVR–11/06ATtiny261/461/861It is important to notice that accessing 10-bit registers are atomic operations. If an interruptoccurs between the

1122588B–AVR–11/06ATtiny261/461/861The following code examples show how to do an atomic write of the TCNT1 register contents.Writing any of the OCR1A/

1132588B–AVR–11/06ATtiny261/461/86116.11 Register Description16.11.1 TCCR1A – Timer/Counter1 Control Register A• Bits 7,6 - COM1A1, COM1A0: Comparator

1142588B–AVR–11/06ATtiny261/461/861Table 16-8 shows the COM1A1:0 bit functionality when the PWM1A, WGM10 and WGM11 bitsare set to Phase and Frequency

1152588B–AVR–11/06ATtiny261/461/861that the Data Direction Register (DDR) bit corresponding to the OC1B pin must be set in order toenable the output d

1162588B–AVR–11/06ATtiny261/461/861value. The automatic action programmed in COM1A1 and COM1A0 takes place as if a comparematch had occurred, but no i

1172588B–AVR–11/06ATtiny261/461/861• Bits 3 .. 0 - CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0The Clock Select bits 3, 2, 1, and 0 define

1182588B–AVR–11/06ATtiny261/461/861• Bits 5,4 - COM1B1S, COM1B0S: Comparator B Output Mode, Bits 1 and 0These bits are the shadow bits of the COM1A1 a

1192588B–AVR–11/06ATtiny261/461/861• Bit 1 - FOC1D: Force Output Compare Match 1DThe FOC1D bit is only active when the PWM1D bit specify a non-PWM mod

122588B–AVR–11/06ATtiny261/461/861Figure 5-3. The X-, Y-, and Z-registersIn the different addressing modes these address registers have functions as f

1202588B–AVR–11/06ATtiny261/461/861• Bit 3 - FPAC1: Fault Protection Analog Comparator EnableWhen written logic one, this bit enables the Fault Protec

1212588B–AVR–11/06ATtiny261/461/861the Output Compare Override Enable Bit is cleared. Table 16-20 shows the Output CompareOverride Enable Bits and the

1222588B–AVR–11/06ATtiny261/461/861The Timer/Counter Output Compare Register A contains data to be continuously compared withTimer/Counter1. Actions o

1232588B–AVR–11/06ATtiny261/461/86116.11.11 OCR1D – Timer/Counter1 Output Compare Register DThe output compare register D is an 8-bit read/write regis

1242588B–AVR–11/06ATtiny261/461/86116.11.13 TIFR – Timer/Counter1 Interrupt Flag Register• Bit 7- OCF1D: Output Compare Flag 1DThe OCF1D bit is set (o

1252588B–AVR–11/06ATtiny261/461/861• Bits 7:4- DT1H3:DT1H0: Dead Time Value for OC1x OutputThe dead time value for the OC1x output. The dead time dela

1262588B–AVR–11/06ATtiny261/461/86117. USI – Universal Serial Interface17.1 Features• Two-wire Synchronous Data Transfer (Master or Slave)• Three-wire

1272588B–AVR–11/06ATtiny261/461/861The 4-bit counter can be both read and written via the data bus, and can generate an overflowinterrupt. Both the US

1282588B–AVR–11/06ATtiny261/461/861Figure 17-3. Three-wire Mode, Timing DiagramThe Three-wire mode timing is shown in Figure 17-3. At the top of the f

1292588B–AVR–11/06ATtiny261/461/861rjmp SPITransfer_looplds r16,USIDRretThe code is size optimized using only eight instructions (+ ret). The code exa

132588B–AVR–11/06ATtiny261/461/8615.6 Instruction Execution TimingThis section describes the general access timing concepts for instruction execution.

1302588B–AVR–11/06ATtiny261/461/86117.3.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave:init:ld

1312588B–AVR–11/06ATtiny261/461/861Figure 17-4. Two-wire Mode Operation, Simplified DiagramFigure 17-4 shows two USI units operating in Two-wire mode,

1322588B–AVR–11/06ATtiny261/461/8611. The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A). SDA

1332588B–AVR–11/06ATtiny261/461/86117.4 Alternative USI UsageWhen the USI unit is not used for serial communication, it can be set up to do alternativ

1342588B–AVR–11/06ATtiny261/461/86117.5.2 USIBR – USI Buffer RegisterThe content of the Serial Register is loaded to the USI Buffer Register when the

1352588B–AVR–11/06ATtiny261/461/861The 4-bit counter increments by one for each clock generated either by the external clock edgedetector, by a Timer/

1362588B–AVR–11/06ATtiny261/461/861Note: 1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively to avoid confusi

1372588B–AVR–11/06ATtiny261/461/861• Bit 1 – USICLK: Clock StrobeWriting a one to this bit location strobes the USI Data Register to shift one step an

1382588B–AVR–11/06ATtiny261/461/86118. AC – Analog ComparatorThe Analog Comparator compares the input values on the selectable positive pin (AIN0, AIN

1392588B–AVR–11/06ATtiny261/461/861• Bit 5 – ACO: Analog Comparator OutputThe output of the Analog Comparator is synchronized and then directly connec

142588B–AVR–11/06ATtiny261/461/861When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-abled. The user so

1402588B–AVR–11/06ATtiny261/461/86118-2. If ACME is cleared or ADEN is set, either AIN0, AIN1 or AIN2 is applied to the negativeinput to the Analog Co

1412588B–AVR–11/06ATtiny261/461/86118.2.1 ACSRB – Analog Comparator Control and Status Register B• Bit 7 – HSEL: Hysteresis SelectWhen this bit is wri

1422588B–AVR–11/06ATtiny261/461/86119. ADC – Analog to Digital Converter19.1 Features• 10-bit Resolution• 1.0 LSB Integral Non-linearity• ± 2 LSB Abso

1432588B–AVR–11/06ATtiny261/461/861Figure 19-1. Analog to Digital Converter Block Schematic19.3 OperationThe ADC converts an analog input voltage to a

1442588B–AVR–11/06ATtiny261/461/861If the same ADC input pin is selected as both the positive and negative input to the differentialgain amplifier, th

1452588B–AVR–11/06ATtiny261/461/861Figure 19-2. ADC Auto Trigger LogicUsing the ADC Interrupt Flag as a trigger source makes the ADC start a new conve

1462588B–AVR–11/06ATtiny261/461/861The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bitin ADCSRA. The prescale

1472588B–AVR–11/06ATtiny261/461/861Figure 19-6. ADC Timing Diagram, Auto Triggered ConversionFigure 19-7. ADC Timing Diagram, Free Running Conversion1

1482588B–AVR–11/06ATtiny261/461/861ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge afterADSC is written. The us

1492588B–AVR–11/06ATtiny261/461/861interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC convers

152588B–AVR–11/06ATtiny261/461/861When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-cuted before any pend

1502588B–AVR–11/06ATtiny261/461/86119.7.2 Analog Noise Canceling TechniquesDigital circuitry inside and outside the device generates EMI which might a

1512588B–AVR–11/06ATtiny261/461/861Figure 19-10. Gain Error• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the m

1522588B–AVR–11/06ATtiny261/461/861Figure 19-12. Differential Non-linearity (DNL)• Quantization Error: Due to the quantization of the input voltage in

1532588B–AVR–11/06ATtiny261/461/861155). The voltage on the positive pin must always be larger than the voltage on the negative pinor otherwise the vo

1542588B–AVR–11/06ATtiny261/461/861where ADCn are the ADC data registers, k is a fixed coefficient and TOS is the temperature sen-sor offset value det

1552588B–AVR–11/06ATtiny261/461/861Table 19-4. Input Channel SelectionsMUX5..0Single Ended InputPositive Differential InputNegative Differential Input

1562588B–AVR–11/06ATtiny261/461/861100000N/AADC0(PA0) ADC1(PA1) 20x/32x100001 ADC0(PA0) ADC1(PA1) 1x/8x100010 ADC1(PA1 ADC0(PA0) 20x/32x100011 ADC1(PA

1572588B–AVR–11/06ATtiny261/461/86119.10.2 ADCSRA – ADC Control and Status Register A• Bit 7 – ADEN: ADC EnableWriting this bit to one enables the ADC

1582588B–AVR–11/06ATtiny261/461/86119.10.3 ADCL and ADCH – The ADC Data Register19.10.3.1 ADLAR = 019.10.3.2 ADLAR = 1When an ADC conversion is comple

1592588B–AVR–11/06ATtiny261/461/861• Bits 7– BIN: Bipolar Input ModeThe gain stage is working in the unipolar mode as default, but the bipolar mode ca

162588B–AVR–11/06ATtiny261/461/8616. AVR MemoriesThis section describes the different memories in the ATtiny261/461/861. The AVR architecturehas two m

1602588B–AVR–11/06ATtiny261/461/86119.10.5 DIDR0 – Digital Input Disable Register 0• Bits 7:4,2:0 – ADC6D:ADC0D: ADC6:0 Digital Input DisableWhen this

1612588B–AVR–11/06ATtiny261/461/86120. debugWIRE On-chip Debug System20.1 Features• Complete Program Flow Control• Emulates All On-chip Functions, Bot

1622588B–AVR–11/06ATtiny261/461/861When designing a system where debugWIRE will be used, the following observations must bemade for correct operation:

1632588B–AVR–11/06ATtiny261/461/86121. Self-Programming the FlashThe device provides a Self-Programming mechanism for downloading and uploading progra

1642588B–AVR–11/06ATtiny261/461/861The page address must be written to PCPAGE. Other bits in the Z-pointer must be written tozero during this operatio

1652588B–AVR–11/06ATtiny261/461/86121.1.2 Reading the Fuse and Lock Bits from SoftwareIt is possible to read both the Fuse and Lock bits from software

1662588B–AVR–11/06ATtiny261/461/86121.1.4 Programming Time for Flash when Using SPMThe calibrated RC Oscillator is used to time Flash accesses. Table

1672588B–AVR–11/06ATtiny261/461/861• Bit 0 – SPMEN: Store Program Memory EnableThis bit enables the SPM instruction for the next four clock cycles. If

1682588B–AVR–11/06ATtiny261/461/86122. Memory ProgrammingThis section describes the different methods for Programming the ATtiny261/461/861 memories.2

1692588B–AVR–11/06ATtiny261/461/86122.2 Fuse BytesThe ATtiny261/461/861 has three Fuse bytes. Table 22-3, Table 22-4 and Table 22-5 describebriefly th

172588B–AVR–11/06ATtiny261/461/861When using register indirect addressing modes with automatic pre-decrement and post-incre-ment, the address register

1702588B–AVR–11/06ATtiny261/461/861Notes: 1. See ”System Clock Prescaler” on page 31 for details.2. The CKOUT Fuse allows the system clock to be outpu

1712588B–AVR–11/06ATtiny261/461/86122.5 Page Size22.6 Parallel Programming Parameters, Pin Mapping, and CommandsThis section describes how to parallel

1722588B–AVR–11/06ATtiny261/461/861Figure 22-1. Parallel ProgrammingTable 22-9. Pin Name Mapping Signal Name in Programming ModePin Name I/O FunctionW

1732588B–AVR–11/06ATtiny261/461/86122.7 Parallel Programming22.7.1 Enter Programming ModeThe following algorithm puts the device in parallel programmi

1742588B–AVR–11/06ATtiny261/461/86122.7.3 Chip EraseThe Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits arenot re

1752588B–AVR–11/06ATtiny261/461/861While the lower bits in the address are mapped to words within the page, the higher bits addressthe pages within th

1762588B–AVR–11/06ATtiny261/461/861Figure 22-3. Programming the Flash Waveforms(1)Note: 1. “XX” is don’t care. The letters refer to the programming de

1772588B–AVR–11/06ATtiny261/461/861Figure 22-4. Programming the EEPROM Waveforms22.7.6 Reading the FlashThe algorithm for reading the Flash memory is

1782588B–AVR–11/06ATtiny261/461/86122.7.9 Programming the Fuse High BitsThe algorithm for programming the Fuse High bits is as follows (refer to ”Prog

1792588B–AVR–11/06ATtiny261/461/86122.7.11 Programming the Lock BitsThe algorithm for programming the Lock bits is as follows (refer to ”Programming t

182588B–AVR–11/06ATtiny261/461/8616.3.1 EEPROM Read/Write AccessThe EEPROM Access Registers are accessible in the I/O space.The write access times for

1802588B–AVR–11/06ATtiny261/461/86122.7.13 Reading the Signature BytesThe algorithm for reading the Signature bytes is as follows (refer to ”Programmi

1812588B–AVR–11/06ATtiny261/461/86122.8 Serial DownloadingBoth the Flash and EEPROM memory arrays can be programmed using the serial SPI bus whileRESE

1822588B–AVR–11/06ATtiny261/461/86122.8.1 Serial Programming AlgorithmWhen writing serial data to the ATtiny261/461/861, data is clocked on the rising

1832588B–AVR–11/06ATtiny261/461/86122.8.2 Serial Programming Instruction setTable 22-15 on page 183 and Figure 22-8 on page 184 describes the Instruct

1842588B–AVR–11/06ATtiny261/461/861Notes: 1. Not all instructions are applicable for all parts.2. a = address3. Bits are programmed ‘0’, unprogrammed

1852588B–AVR–11/06ATtiny261/461/86123. Electrical Characteristics23.1 Absolute Maximum Ratings*23.2 DC CharacteristicsOperating Temperature...

1862588B–AVR–11/06ATtiny261/461/861Notes: 1. Typical values at 25 °C. Maximum values are characterized values and not test limits in production.2. “Ma

1872588B–AVR–11/06ATtiny261/461/86123.3 Speed GradesFigure 23-1. Maximum Frequency vs. VCCFigure 23-2. Maximum Frequency vs. VCC10 MHz4 MHz1.8V 2.7V 5

1882588B–AVR–11/06ATtiny261/461/86123.4 Clock Characteristics23.4.1 Calibrated Internal RC Oscillator AccuracyNotes: 1. Voltage range for ATtiny261V/4

1892588B–AVR–11/06ATtiny261/461/86123.5 System and Reset CharacteristicsNotes: 1. Values are guidelines only. Actual values are TBD.2. The Power-on Re

192588B–AVR–11/06ATtiny261/461/861The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator fre-quency is within the req

1902588B–AVR–11/06ATtiny261/461/86123.6 ADC Characteristics – Preliminary DataNote: 1. Values are preliminary.Table 23-5. ADC Characteristics, Single

1912588B–AVR–11/06ATtiny261/461/86123.7 Parallel Programming CharacteristicsFigure 23-4. Parallel Programming Timing, Including some General Timing Re

1922588B–AVR–11/06ATtiny261/461/861Figure 23-6. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1)Note:

1932588B–AVR–11/06ATtiny261/461/861Note: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands.Note: 1.

1942588B–AVR–11/06ATtiny261/461/86123.8 Serial Programming CharacteristicsFigure 23-7. Serial Programming WaveformsFigure 23-8. Serial Programming Tim

1952588B–AVR–11/06ATtiny261/461/86124. Typical CharacteristicsThe data contained in this section is largely based on simulations and characterization

1962588B–AVR–11/06ATtiny261/461/861Figure 24-2. Active Supply Current vs. Frequency (1 - 20 MHz)Figure 24-3. Active Supply Current vs. VCC (Internal R

1972588B–AVR–11/06ATtiny261/461/861Figure 24-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)Figure 24-5. Active Supply Current vs. VC

1982588B–AVR–11/06ATtiny261/461/86124.2 Idle Supply CurrentFigure 24-6. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz)Figure 24-7. Idle Supply

1992588B–AVR–11/06ATtiny261/461/861Figure 24-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)Figure 24-9. Idle Supply Current vs. VCC (I

22588B–AVR–11/06ATtiny261/461/8611. Pin ConfigurationsFigure 1-1. Pinout ATtiny261/461/861Note: The large center pad underneath the QFN/MLF package sh

202588B–AVR–11/06ATtiny261/461/861The next code examples show assembly and C functions for reading the EEPROM. The exam-ples assume that interrupts ar

2002588B–AVR–11/06ATtiny261/461/861Figure 24-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz)24.3 Supply Current of I/O modulesThe ta

2012588B–AVR–11/06ATtiny261/461/861Example Calculate the expected current consumption in idle mode with TIMER0, ADC, and USI enabledat VCC = 2.0V and

2022588B–AVR–11/06ATtiny261/461/86124.5 Pin Pull-upFigure 24-13. I/O Pin pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)Figure 24-14. I/O Pin

2032588B–AVR–11/06ATtiny261/461/861Figure 24-15. I/O Pin pull-up Resistor Current vs. Input Voltage (VCC = 5V)Figure 24-16. Reset Pull-up Resistor Cur

2042588B–AVR–11/06ATtiny261/461/861Figure 24-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)Figure 24-18. Reset Pull-up Resistor

2052588B–AVR–11/06ATtiny261/461/86124.6 Pin Driver StrengthFigure 24-19. I/O Pin Output Voltage vs. Sink Current (VCC = 3V)Figure 24-20. I/O Pin Outpu

2062588B–AVR–11/06ATtiny261/461/861Figure 24-21. I/O Pin Output Voltage vs. Source Current (VCC = 3V)Figure 24-22. I/O Pin Output Voltage vs. Source C

2072588B–AVR–11/06ATtiny261/461/86124.7 Pin Threshold and HysteresisFigure 24-23. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as ‘1’)Fi

2082588B–AVR–11/06ATtiny261/461/861Figure 24-25. I/O Pin Input Hysteresis vs. VCC Figure 24-26. Reset Input Threshold Voltage vs. VCC (VIH, Reset Read

2092588B–AVR–11/06ATtiny261/461/861Figure 24-27. Reset Input Threshold Voltage vs. VCC (VIL, Reset Read as ‘0’)Figure 24-28. Reset Pin input Hysteresi

212588B–AVR–11/06ATtiny261/461/8616.4 I/O MemoryThe I/O space definition of the ATtiny261/461/861 is shown in ”Register Summary” on page 218.All ATtin

2102588B–AVR–11/06ATtiny261/461/86124.8 BOD Threshold and Analog Comparator OffsetFigure 24-29. BOD Threshold vs. Temperature (BOD Level is 4.3V)Figur

2112588B–AVR–11/06ATtiny261/461/861Figure 24-31. BOD Threshold vs. Temperature (BOD Level is 1.8V)24.9 Internal Oscillator SpeedFigure 24-32. Watchdog

2122588B–AVR–11/06ATtiny261/461/861Figure 24-33. Calibrated 8.0 MHz RC Oscillator Frequency vs. VCC Figure 24-34. Calibrated 8.0 MHz RC Oscillator Fre

2132588B–AVR–11/06ATtiny261/461/861Figure 24-35. Calibrated 8.0 MHz RC Oscillator Frequency vs. OSCCAL Value 24.10 Current Consumption of Peripheral U

2142588B–AVR–11/06ATtiny261/461/861Figure 24-37. AREF External Reference Current vs. VCCFigure 24-38. Analog Comparator vs. VCCAREF EXTERNAL REFERENCE

2152588B–AVR–11/06ATtiny261/461/861Figure 24-39. Brownout Detector Current vs. VCC Figure 24-40. Programming Current vs. VCCBROWNOUT DETECTOR CURRENT

2162588B–AVR–11/06ATtiny261/461/861Figure 24-41. Watchdog Timer Current vs. VCC24.11 Current Consumption in Reset and Reset PulsewidthFigure 24-42. Re

2172588B–AVR–11/06ATtiny261/461/861Figure 24-43. Reset Supply Current vs. Frequency (1 - 20 MHz, Excluding Current Through the Reset Pull-up)Figure 24

2182588B–AVR–11/06ATtiny261/461/86125. Register SummaryAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page0x3F (0x5F) SREG I T H S V N Z

2192588B–AVR–11/06ATtiny261/461/861Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O m

222588B–AVR–11/06ATtiny261/461/8616.5.2 EEDR – EEPROM Data Register• Bits 7:0 – EEDR7:0: EEPROM DataFor the EEPROM write operation the EEDR Register c

2202588B–AVR–11/06ATtiny261/461/86126. Instruction Set SummaryMnemonics Operands Description Operation Flags #ClocksARITHMETIC AND LOGIC INSTRUCTIONSA

2212588B–AVR–11/06ATtiny261/461/861ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1ASR Rd Arithmetic Shift Right Rd(n) ← Rd(

2222588B–AVR–11/06ATtiny261/461/86127. Ordering InformationNotes: 1. This device can also be supplied in wafer form. Please contact your local Atmel s

2232588B–AVR–11/06ATtiny261/461/861Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed

2242588B–AVR–11/06ATtiny261/461/861Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed

2252588B–AVR–11/06ATtiny261/461/86128. Packaging Information28.1 32M1-A 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 32M1-A, 32-pa

2262588B–AVR–11/06ATtiny261/461/86128.2 20P3 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 20P3, 20-lead (0.300"/7.62 mm Wide)

2272588B–AVR–11/06ATtiny261/461/86128.3 20S2

2282588B–AVR–11/06ATtiny261/461/86129. Errata29.1 Errata ATtiny261The revision letter in this section refers to the revision of the ATtiny261 device.2

2292588B–AVR–11/06ATtiny261/461/86130. Datasheet Revision History30.1 Rev. 2588A – 11/0630.2 Rev. 2588A – 10/061. Updated ”Ordering Information” on pa

232588B–AVR–11/06ATtiny261/461/861• Bit 2 – EEMPE: EEPROM Master Program EnableThe EEMPE bit determines whether writing EEPE to one will have effect o

2302588B–AVR–11/06ATtiny261/461/861

i2588B–AVR–11/06ATtiny261/461/861Table of ContentsFeatures ...

ii2588B–AVR–11/06ATtiny261/461/8617.10 Clock Output Buffer ...

iii2588B–AVR–11/06ATtiny261/461/86114.6 Input Capture Unit ...

iv2588B–AVR–11/06ATtiny261/461/86119.6 Changing Channel or Reference Selection ...14719.7 ADC No

v2588B–AVR–11/06ATtiny261/461/86124.1 Active Supply Current ...1

2588B–AVR–11/06Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel

242588B–AVR–11/06ATtiny261/461/8617. System Clock and Clock Options7.1 Clock Systems and their DistributionFigure 7-1 presents the principal clock sys

252588B–AVR–11/06ATtiny261/461/8617.1.5 Internal PLL for Fast Peripheral Clock Generation - clkPCKThe internal PLL in ATtiny261/461/861 generates a cl

262588B–AVR–11/06ATtiny261/461/8617.2 Clock SourcesThe device has the following clock source options, selectable by Flash Fuse bits as shownbelow. The

272588B–AVR–11/06ATtiny261/461/861Figure 7-3. External Clock Drive ConfigurationWhen this clock source is selected, start-up times are determined by t

282588B–AVR–11/06ATtiny261/461/8617.6 Calibrated Internal RC OscillatorBy default, the Internal RC Oscillator provides an approximate 8.0 MHz clock. T

292588B–AVR–11/06ATtiny261/461/8617.7 128 kHz Internal OscillatorThe 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kH

32588B–AVR–11/06ATtiny261/461/8612. OverviewThe ATtiny261/461/861 is a low-power CMOS 8-bit microcontroller based on the AVR enhancedRISC architecture

302588B–AVR–11/06ATtiny261/461/861Figure 7-4. Crystal Oscillator ConnectionsThe Oscillator can operate in three different modes, each optimized for a

312588B–AVR–11/06ATtiny261/461/861Notes: 1. These options should only be used when not operating close to the maximum frequency of the device, and onl

322588B–AVR–11/06ATtiny261/461/8617.12 Register Description7.12.1 OSCCAL – Oscillator Calibration Register• Bits 7:0 – CAL7:0: Oscillator Calibration

332588B–AVR–11/06ATtiny261/461/861nous peripherals is reduced when a division factor is used. The division factors are given inTable 7-12.To avoid uni

342588B–AVR–11/06ATtiny261/461/8618. Power Management and Sleep ModesThe high performance and industry leading code efficiency makes the AVR microcont

352588B–AVR–11/06ATtiny261/461/8618.3 ADC Noise Reduction ModeWhen the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enter ADC No

362588B–AVR–11/06ATtiny261/461/8618.7.1 Analog to Digital ConverterIf enabled, the ADC will be enabled in all sleep modes. To save power, the ADC shou

372588B–AVR–11/06ATtiny261/461/861Refer to ”DIDR0 – Digital Input Disable Register 0” on page 160 or ”DIDR1 – Digital Input Dis-able Register 1” on pa

382588B–AVR–11/06ATtiny261/461/861• Bit 2- PRTIM0: Power Reduction Timer/Counter0Writing a logic one to this bit shuts down the Timer/Counter0 module.

392588B–AVR–11/06ATtiny261/461/8619. System Control and Reset9.0.1 Resetting the AVRDuring reset, all I/O Registers are set to their initial values, a

42588B–AVR–11/06ATtiny261/461/861The AVR core combines a rich instruction set with 32 general purpose working registers. All the32 registers are direc

402588B–AVR–11/06ATtiny261/461/8619.0.3 Power-on ResetA Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection levelis

412588B–AVR–11/06ATtiny261/461/861Figure 9-4. External Reset During Operation9.0.5 Brown-out DetectionATtiny261/461/861 has an On-chip Brown-out Detec

422588B–AVR–11/06ATtiny261/461/861Figure 9-6. Watchdog Reset During Operation9.1 Internal Voltage ReferenceATtiny261/461/861 features an internal band

432588B–AVR–11/06ATtiny261/461/861Figure 9-7. Watchdog Timer9.3 Timed Sequences for Changing the Configuration of the Watchdog TimerThe sequence for c

442588B–AVR–11/06ATtiny261/461/8619.4 Register Description9.4.1 MCUSR – MCU Status RegisterThe MCU Status Register provides information on which reset

452588B–AVR–11/06ATtiny261/461/861the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set aftereach interrupt.• Bit 4 –

462588B–AVR–11/06ATtiny261/461/861Table 9-3. Watchdog Timer Prescale SelectWDP3 WDP2 WDP1 WDP0Number of WDT Oscillator CyclesTypical Time-out at VCC =

472588B–AVR–11/06ATtiny261/461/861The following code example shows one assembly and one C function for turning off the WDT.The example assumes that in

482588B–AVR–11/06ATtiny261/461/86110. InterruptsThis section describes the specifics of the interrupt handling as performed in ATtiny261/461/861.For a

492588B–AVR–11/06ATtiny261/461/8610x0007 rjmp USI_START ; USI Start Handler0x0008 rjmp USI_OVF ; USI Overflow Handler0x0009 rjmp EE_RDY ; EEPROM Ready

52588B–AVR–11/06ATtiny261/461/8612.2.6 Port B (PB7..PB0)Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

502588B–AVR–11/06ATtiny261/461/86111. External InterruptsThe External Interrupts are triggered by the INT0 or INT1 pin or any of the PCINT15..0 pins.O

512588B–AVR–11/06ATtiny261/461/86111.1.2 GIMSK – General Interrupt Mask Register• Bit 7 – INT1: External Interrupt Request 1 EnableWhen the INT1 bit i

522588B–AVR–11/06ATtiny261/461/861Alternatively, the flag can be cleared by writing a logical one to it. This flag is always clearedwhen INT1 is confi

532588B–AVR–11/06ATtiny261/461/86112. I/O Ports12.1 OverviewAll AVR ports have true Read-Modify-Write functionality when used as general digital I/O p

542588B–AVR–11/06ATtiny261/461/861Note that enabling the alternate function of some of the port pins does not affect the use of theother pins in the p

552588B–AVR–11/06ATtiny261/461/861If PORTxn is written logic one when the pin is configured as an output pin, the port pin is drivenhigh (one). If POR

562588B–AVR–11/06ATtiny261/461/861Figure 12-3. Synchronization when Reading an Externally Applied Pin valueConsider the clock period starting shortly

572588B–AVR–11/06ATtiny261/461/861Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pi

582588B–AVR–11/06ATtiny261/461/86112.2.6 Unconnected PinsIf some pins are unused, it is recommended to ensure that these pins have a defined level. Ev

592588B–AVR–11/06ATtiny261/461/861Figure 12-5. Alternate Port Functions(1)Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the

62588B–AVR–11/06ATtiny261/461/8613. ResourcesA comprehensive set of development tools, application notes and datasheets are available fordownload on h

602588B–AVR–11/06ATtiny261/461/861Table 12-2 summarizes the function of the overriding signals. The pin and port indexes from Fig-ure 12-5 are not sho

612588B–AVR–11/06ATtiny261/461/86112.3.1 Alternate Functions of Port BThe Port B pins with alternate function are shown in Table 12-3.The alternate pi

622588B–AVR–11/06ATtiny261/461/861ADC8: ADC input Channel 8. Note that ADC input channel 8 uses analog power.PCINT13: Pin Change Interrupt source 13.•

632588B–AVR–11/06ATtiny261/461/861• Port B, Bit 0 - MOSI/ DI/ SDA/ OC1A/ PCINT8MOSI: SPI Master Data output, Slave Data input for SPI channel. When th

642588B–AVR–11/06ATtiny261/461/861Table 12-4 and Table 12-5 relate the alternate functions of Port B to the overriding signalsshown in Figure 12-5 on

652588B–AVR–11/06ATtiny261/461/86112.3.2 Alternate Functions of Port AThe Port A pins with alternate function are shown in Table 12-6.The alternate pi

662588B–AVR–11/06ATtiny261/461/861PCINT3: Pin Change Interrupt source 3.• Port A, Bit 2 - ADC2/INT1/USCK/SCL/PCINT2ADC2: Analog to Digital Converter,

672588B–AVR–11/06ATtiny261/461/861Table 12-8. Overriding Signals for Alternate Functions in PA3..PA0Signal NamePA3/A REF/PCINT3PA2/ADC2/INT1/USCK/SCL/

682588B–AVR–11/06ATtiny261/461/86112.4 Register Description12.4.1 MCUCR – MCU Control Register• Bit 6 – PUD: Pull-up DisableWhen this bit is written t

692588B–AVR–11/06ATtiny261/461/86113. Timer/Counter0 PrescalerThe Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1

72588B–AVR–11/06ATtiny261/461/8614. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of

702588B–AVR–11/06ATtiny261/461/861An external clock source can not be prescaled.Figure 13-2. Prescaler for Timer/Counter0Note: 1. The synchronization

712588B–AVR–11/06ATtiny261/461/861If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock thecounter even if the p

722588B–AVR–11/06ATtiny261/461/86114. Timer/Counter014.1 Features• Clear Timer on Compare Match (Auto Reload)• Input Capture unit• Four Independent In

732588B–AVR–11/06ATtiny261/461/86114.2.2 DefinitionsMany register and bit references in this section are written in general form. A lower case “n”repl

742588B–AVR–11/06ATtiny261/461/861internal clock source, selected by the Clock Select bits (CS02:0). When no clock source isselected (CS02:0 = 0) the

752588B–AVR–11/06ATtiny261/461/861Figure 14-2. CTC Mode, Timing Diagram An interrupt can be generated each time the counter value reaches the TOP valu

762588B–AVR–11/06ATtiny261/461/86114.6 Input Capture UnitThe Timer/Counter incorporates an Input Capture unit that can capture external events and giv

772588B–AVR–11/06ATtiny261/461/86114.6.1 Input Capture Trigger SourceThe default trigger source for the Input Capture unit is the Input Capture pin (I

782588B–AVR–11/06ATtiny261/461/861when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a log-ical one to its

792588B–AVR–11/06ATtiny261/461/861Figure 14-6. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)Figure 14-7 shows the setting of OCF0A and OCF

82588B–AVR–11/06ATtiny261/461/8615. AVR CPU Core5.1 OverviewThis section discusses the AVR core architecture in general. The main function of the CPU

802588B–AVR–11/06ATtiny261/461/86114.9 Accessing Registers in 16-bit ModeIn 16-bit mode (the TCW0 bit is set to one) the TCNT0H/L and OCR0A/B or TCNT0

812588B–AVR–11/06ATtiny261/461/861The following code examples show how to access the 16-bit timer registers assuming that nointerrupts updates the tem

822588B–AVR–11/06ATtiny261/461/861The following code examples show how to do an atomic read of the TCNT0 register contents.Reading any of the OCR0 reg

832588B–AVR–11/06ATtiny261/461/861The following code examples show how to do an atomic write of the TCNT0H/L register con-tents. Writing any of the OC

842588B–AVR–11/06ATtiny261/461/86114.10 Register Description14.10.1 TCCR0A – Timer/Counter0 Control Register A• Bit 7– TCW0: Timer/Counter0 WidthWhen

852588B–AVR–11/06ATtiny261/461/861Normal mode (counter) and Clear Timer on Compare Match (CTC) mode (see ”Modes of Oper-ation” on page 74).14.10.2 TCN

862588B–AVR–11/06ATtiny261/461/861In 16-bit mode the OCR0B register contains the high byte of the 16-bit Output Compare Regis-ter. To ensure that both

872588B–AVR–11/06ATtiny261/461/86114.10.7 TIFR – Timer/Counter0 Interrupt Flag Register• Bit 4– OCF0A: Output Compare Flag 0 AThe OCF0A bit is set whe

882588B–AVR–11/06ATtiny261/461/86115. Timer/Counter1 PrescalerFigure 15-1 shows the Timer/Counter1 prescaler that supports two clocking modes, a synch

892588B–AVR–11/06ATtiny261/461/86115.1 Register Description15.1.1 PLLCSR – PLL Control and Status Register• Bit 7- LSM: Low Speed ModeThe Low Speed mo

92588B–AVR–11/06ATtiny261/461/861Six of the 32 registers can be used as three 16-bit indirect address register pointers for DataSpace addressing – ena

902588B–AVR–11/06ATtiny261/461/861When this bit is set (one), the Timer/Counter prescaler (TCNT1 is unaffected) will be reset. Thebit will be cleared

912588B–AVR–11/06ATtiny261/461/86116. Timer/Counter116.1 Features• 10/8-Bit Accuracy• Three Independent Output Compare Units• Clear Timer on Compare M

922588B–AVR–11/06ATtiny261/461/861Figure 16-1. Timer/Counter1 Block Diagram16.2.1 SpeedThe maximum speed of the Timer/Counter1 is 64 MHz. However, if

932588B–AVR–11/06ATtiny261/461/861Timer/Counter TOP value, i.e. the clear on compare match value. The Timer/Counter1 HighByte Register (TC1H) is a 2-b

942588B–AVR–11/06ATtiny261/461/861Figure 16-2. Timer/Counter1 Synchronization Register Block Diagram.16.2.5 DefinitionsMany register and bit reference

952588B–AVR–11/06ATtiny261/461/86116.3 Counter UnitThe main part of the Timer/Counter1 is the programmable bi-directional counter unit. Figure 16-3 sh

962588B–AVR–11/06ATtiny261/461/86116.4 Output Compare UnitThe comparator continuously compares TCNT1 with the Output Compare Registers (OCR1A,OCR1B, O

972588B–AVR–11/06ATtiny261/461/861Figure 16-5. Effects of Unsynchronized OCR Latching16.4.1 Force Output CompareIn non-PWM waveform generation modes,

982588B–AVR–11/06ATtiny261/461/86116.5 Dead Time GeneratorThe Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving

992588B–AVR–11/06ATtiny261/461/861The length of the counting period is user adjustable by selecting the dead time prescaler settingby using the DTPS11