Rainbow-electronics T89C51CC01 User Manual

Rev. D – 17-Dec-0111. Features• 80C51 core architecture:– 256 bytes of on-chip RAM– 1 Kbytes of on-chip ERAM– 32 Kbytes of on-chip Flash memoryData Re

10T89C51CC01Rev. D – 17-Dec-01It is not obvious the last three instructions in this list are Read-Modify-Write instructions.These instructions read th

100T89C51CC01Rev. D – 17-Dec-01Table 60. CANIDT2 Register for V2.0 part BCANIDT2 for V2.0 part B(S:BDh)CAN Identifier Tag Registers 2No default value

101T89C51CC01Rev. D – 17-Dec-01Table 63. CANIDM1 Register for V2.0 part ACANIDM1 for V2.0 part A(S:C4h)CAN Identifier Mask Registers 1No default value

102T89C51CC01Rev. D – 17-Dec-01Table 66. CANIDM4 Register for V2.0 part ACANIDM4 for V2.0 part A(S:C7h)CAN Identifier Mask Registers 4Note: The ID Mas

103T89C51CC01Rev. D – 17-Dec-01Table 68. CANIDM2 Register for V2.0 part BCANIDM2 for V2.0 part B(S:C5h)CAN Identifier Mask Registers 2Note: The ID Mas

104T89C51CC01Rev. D – 17-Dec-01Table 70. CANIDM4 Register for V2.0 part BCANIDM4 for V2.0 part B(S:C7h)CAN Identifier Mask Registers 4Note: The ID Mas

105T89C51CC01Rev. D – 17-Dec-01Table 72. CANTCON RegisterCANTCON (S:A1h)CAN Timer ClockControlReset Value: 00hTable 73. CANTIMH RegisterCANTIMH (S:ADh

106T89C51CC01Rev. D – 17-Dec-01Table 75. CANSTMPH RegisterCANSTMPH (S:AFh Read Only)CAN Stamp Timer HighNo default value after resetTable 76. CANSTMPL

107T89C51CC01Rev. D – 17-Dec-01Table 78. CANTTCL RegisterCANTTCL(S:A4hReadOnly)CAN TTC Timer LowReset Value: 0000 0000b76543210TIMTTC 7 TIMTTC 6 TIMTT

108T89C51CC01Rev. D – 17-Dec-0116. ProgrammableCounter Array PCAThe PCA provides more timing capabilities with less CPU intervention than the standard

109T89C51CC01Rev. D – 17-Dec-01Figure 40. PCA Timer/CounterThe CMOD register includes three additional bits associated with the PCA.• The CIDL bit whi

11T89C51CC01Rev. D – 17-Dec-015. SFR Mapping The Special Function Registers (SFRs) of the T89C51CC01 fall into the followingcategories:Table 2. C51Cor

110T89C51CC01Rev. D – 17-Dec-01Each module in the PCA has a special function register associated with it (CCAPM0 formodule 0 ...). The CCAPM0:4 regist

111T89C51CC01Rev. D – 17-Dec-01Figure 42. PCA Capture Mode16.5 16-bit SoftwareTimer ModeThe PCA modules can be used as software timers by setting both

112T89C51CC01Rev. D – 17-Dec-0116.6 High Speed OutputModeIn this mode the CEX output (on port 1) associated with the PCA module will toggleeach time a

113T89C51CC01Rev. D – 17-Dec-01Figure 45. PCA PWM Mode16.8 PCA WatchdogTimerAn on-board watchdog timer is available with the PCA to improve system rel

114T89C51CC01Rev. D – 17-Dec-0116.9 PCA Registers Table 79. CMOD RegisterCMOD (S:D8h)PCA Counter Mode RegisterReset Value = 00XX X000b76543210CIDL WDT

115T89C51CC01Rev. D – 17-Dec-01Table 80. CCON RegisterCCON (S:D8h)PCA Counter Control RegisterReset Value = 00X0 0000b76543210CF CR - CCF4 CCF3 CCF2 C

116T89C51CC01Rev. D – 17-Dec-01Table 81. CCAPnH RegistersCCAP0H (S:FAh)CCAP1H (S:FBh)CCAP2H (S:FCh)CCAP3H (S:FDh)CCAP4H (S:FEh)PCA High ByteCompare/Ca

117T89C51CC01Rev. D – 17-Dec-01Table 83. CCAPMn RegistersCCAPM0 (S:DAh)CCAPM1 (S:DBh)CCAPM2 (S:DCh)CCAPM3 (S:DDh)CCAPM4 (S:DEh)PCA Compare/Capture Mod

118T89C51CC01Rev. D – 17-Dec-01Table 84. CH RegisterCH (S:F9h)PCA Counter Register HighvalueReset Value = 0000 00000bTable 85. CL RegisterCL (S:E9h)PC

119T89C51CC01Rev. D – 17-Dec-0117. Analog-to-DigitalConverter (ADC)This section describes the on-chip 10 bit analog-to-digital converter of theT89C51C

12T89C51CC01Rev. D – 17-Dec-01Table 5. Serial I/O Port SFRsTable 6. PCA SFRsT2CON C8hTimer/Counter 2controlTF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#T

120T89C51CC01Rev. D – 17-Dec-01Figure 46. ADC DescriptionFigure 47 shows the timing diagram of a complete conversion. For simplicity, the figuredepict

121T89C51CC01Rev. D – 17-Dec-01set, an interrupt occur when flag ADEOC is set (see Figure 49). Clear this flag for re-arming the interrupt.ThebitsSCH0

122T89C51CC01Rev. D – 17-Dec-0117.6 ADC Standby Mode When the ADC is not used, it is possible to set it in standby mode by clearing bit ADENin ADCON r

123T89C51CC01Rev. D – 17-Dec-0117.9 Registers Table 87. ADCF RegisterADCF (S:F6h)ADC ConfigurationReset Value=0000 0000bTable 88. ADCON RegisterADCON

124T89C51CC01Rev. D – 17-Dec-01Table 89. ADCLK RegisterADCLK (S:F2h)ADC Clock PrescalerReset Value: XXX0 0000bTable 90. ADDH RegisterADDH (S:F5h Read

125T89C51CC01Rev. D – 17-Dec-0118. Interrupt System18.1 Introduction The CAN Controller has a total of 10 interrupt vectors: two external interrupts (

126T89C51CC01Rev. D – 17-Dec-01Each of the interrupt sources can be individually enabled or disabled by setting or clear-ing a bit in the Interrupt En

127T89C51CC01Rev. D – 17-Dec-0118.2 Registers Table 89. IEN0 RegisterIEN0 (S:A8h)Interrupt Enable RegisterReset Value: 0000 0000bbit addressable765432

128T89C51CC01Rev. D – 17-Dec-01Table 90. IEN1 RegisterIEN1 (S:E8h)Interrupt Enable RegisterReset Value: xxxx x000bbit addressable76543210- - - - ETIM

129T89C51CC01Rev. D – 17-Dec-01Table 91. IPL0 RegisterIPL0 (S:B8h)Interrupt Enable RegisterReset Value: X000 0000bbit addressable76543210- PPC PT2 PS

13T89C51CC01Rev. D – 17-Dec-01Table 7. Interrupt SFRsTable 8. ADC SFRsCCAP0HCCAP1HCCAP2HCCAP3HCCAP4HFAhFBhFChFDhFEhPCA CompareCapture Module 0 HPCA Co

130T89C51CC01Rev. D – 17-Dec-01Table 92. IPL1 RegisterIPL1 (S:F8h)Interrupt Priority Low Register 1Reset Value: XXXX X000bbit addressable76543210- - -

131T89C51CC01Rev. D – 17-Dec-01Table 93. IPL0 RegisterIPH0 (B7h)Interrupt High Priority RegisterReset Value: X000 0000b76543210- PPCH PT2H PSH PT1H PX

132T89C51CC01Rev. D – 17-Dec-01Table 94. IPH1 RegisterIPH1 (S:FFh)Interrupt high priority Register 1Reset Value = XXXX X000b76543210- - - - POVRH PADC

133T89C51CC01Rev. D – 17-Dec-0119. Electrical Characteristics19.1 Absolute MaximumRatings(1)19.2 DC Parameters for Standard VoltageTA =-40°Cto+85°C; V

134T89C51CC01Rev. D – 17-Dec-01Notes: 1. Operating ICCis measured with all output pins disconnected; XTAL1 driven withTCLCH,TCHCL= 5 ns (see Figure 61

135T89C51CC01Rev. D – 17-Dec-01Figure 58. ICCTest Condition, Active ModeFigure 59. ICCTest Condition, Idle ModeFigure 60. ICCTest Condition, Power-Dow

136T89C51CC01Rev. D – 17-Dec-01Figure 61. Clock Signal Waveform for ICCTests in Active and Idle Modes19.3 DC Parameters for A/D ConverterTable 94. DC

137T89C51CC01Rev. D – 17-Dec-0119.4.2 External ProgramMemory Characteristics Table 95. Symbol DescriptionTable 96. AC Parameters for a Fix Clock (F= 4

138T89C51CC01Rev. D – 17-Dec-01Table 97. AC Parameters for a Variable Clock19.4.3 External ProgramMemory Read CycleSymbol TypeStandardClock X2 Clock X

139T89C51CC01Rev. D – 17-Dec-0119.4.4 External Data MemoryCharacteristicsTable 98. Symbol DescriptionTable 99. AC Parameters for a Variable Clock (F=4

14T89C51CC01Rev. D – 17-Dec-01Table 9. CAN SFRsMnemonicAddName 76543210CANGCON ABh CAN General Control ABRQ OVRQ TTC SYNCTTCAUT-BAUDTEST ENA GRESCANGS

140T89C51CC01Rev. D – 17-Dec-01Table 100. AC Parameters for a Variable Clock19.4.5 External Data MemoryWrite CycleSymbol TypeStandardClock X2 Clock X

141T89C51CC01Rev. D – 17-Dec-0119.4.6 External Data MemoryRead Cycle19.4.7 Serial Port Timing -Shift Register ModeTable 101. Symbol Description (F= 40

142T89C51CC01Rev. D – 17-Dec-01Table 103. AC Parameters for a Variable Clock19.4.8 Shift Register TimingWaveforms19.4.9 External Clock DriveCharacteri

143T89C51CC01Rev. D – 17-Dec-0119.4.11 AC TestingInput/Output WaveformsAC inputs during testing are driven at VCC- 0.5 for a logic “1” and 0.45V for a

144T89C51CC01Rev. D – 17-Dec-01This diagram indicates when signals are clocked internally. The time it takes the signalsto propagate to the pins, howe

145T89C51CC01Rev. D – 17-Dec-0119.5.14 Flash Memory Table 105. Timing Symbol DefinitionsTable 106. Memory AC TimingVDD= 5 V +/- 10% , TA= -40 to +85°C

146T89C51CC01Rev. D – 17-Dec-0120. Ordering InformationTable 106. Possible order entriesPart Number Boot LoaderTemperatureRange Package PackingT89C51C

iT89C51CC01Rev. D – 17-Dec-01Table of Contents1. Features ...

iiT89C51CC01Rev. D – 17-Dec-0114.1 WatchDog Programming ... 6814.2 WatchDog Time

© Atmel Corporation 2001.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa

15T89C51CC01Rev. D – 17-Dec-01Table 10. Other SFRsCANCONH B3h CAN Control Channel CONCH1 CONCH0 RPLV IDE DLC3 DLC2 DLC1 DLC0CANMSG A3h CAN Message Dat

16T89C51CC01Rev. D – 17-Dec-01Table 11. SFR’s mappingReservedNotes: 1. These registers are bit-addressable.Sixteen addresses in the SFR space are both

17T89C51CC01Rev. D – 17-Dec-016. Clock The T89C51CC01 core needs only 6 clock periods per machine cycle. This feature,called”X2”, provides the followi

18T89C51CC01Rev. D – 17-Dec-01Figure 5. Clock CPU Generation DiagramXTAL1XTAL2PDPCON.1CPU Core10÷ 2PERIPHCLOCKClockPeripheral Clock SymbolCPUCLOCKCPU

19T89C51CC01Rev. D – 17-Dec-01Figure 6. Mode Switching WaveformsNote: In order to prevent any incorrect operation while operating in the X2 mode, user

2T89C51CC01Rev. D – 17-Dec-012. Description The T89C51CC01 is the first member of the CANaryTMfamily of 8-bit microcontrollersdedicated to CAN network

20T89C51CC01Rev. D – 17-Dec-01Notes: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bithas no effect.Reset Va

21T89C51CC01Rev. D – 17-Dec-017. Data Memory The T89C51CC01 provides data memory access in two different spaces:1. The internal space mapped in three

22T89C51CC01Rev. D – 17-Dec-017.1 Internal Space7.1.1 Lower 128 Bytes RAM The lower 128 bytes of RAM (see Figure 2) are accessible from address 00h to

23T89C51CC01Rev. D – 17-Dec-017.2 External Space7.2.1 Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as

24T89C51CC01Rev. D – 17-Dec-01For simplicity, the accompanying figures depict the bus cycle waveforms in idealizedform and do not provide precise timi

25T89C51CC01Rev. D – 17-Dec-01Figure 7. Dual Data Pointer Implementation7.3.2 Application Software can take advantage of the additional data pointers

26T89C51CC01Rev. D – 17-Dec-017.4 Registers Table 3. PSW RegisterPSW (S:8Eh)Program Status Word Register.Reset Value= 0000 0000bTable 4. AUXR Register

27T89C51CC01Rev. D – 17-Dec-01Reset Value= X00X 1100bNot bit addressableTable 5. AUXR1 RegisterAUXR1 (S:A2h)Auxiliary Control Register 1.Reset Value=

28T89C51CC01Rev. D – 17-Dec-018. EEPROM DataMemoryThe 2k byte on-chip EEPROM memory block is located at addresses 0000h to 07FFh ofthe XRAM/ERAM memor

29T89C51CC01Rev. D – 17-Dec-018.4 Examples ;*F*************************************************************************;* NAME: api_rd_eeprom_byte;* D

3T89C51CC01Rev. D – 17-Dec-014. Pin ConfigurationPLCC44P1.3 / AN3 / CEX0P1.2 / AN2 / ECIP1.1 / AN1 / T2EXP1.0 / AN 0 / T2VAREFVAGNDRESETVSSVCCXTAL1XTA

30T89C51CC01Rev. D – 17-Dec-018.5 Registers Table 6. EECON RegisterEECON (S:0D2h)EEPROM Control RegisterReset Value= XXXX XX00bNot bit addressable7654

31T89C51CC01Rev. D – 17-Dec-019. Program/CodeMemoryThe T89C51CC01 implement 32 Kbytes of on-chip program/code memory. Figure 8shows the partitioning o

32T89C51CC01Rev. D – 17-Dec-01Figure 9. External Code Memory Interface StructureTable 7. External Code Memory Interface Signals9.1.2 External Bus Cycl

33T89C51CC01Rev. D – 17-Dec-01Figure 10. External Code Fetch Waveforms9.2 FLASH MemoryArchitectureT89C51CC01 features two on-chip flash memories:• Fla

34T89C51CC01Rev. D – 17-Dec-019.2.1 FM0 MemoryArchitectureThe flash memory is made up of 4 blocks (see Figure 11):3. The memory array (user space) 32

35T89C51CC01Rev. D – 17-Dec-019.3 Overview of FM0operationsThe CPU interfaces to the flash memory through the FCON register and AUXR1register.These re

36T89C51CC01Rev. D – 17-Dec-01Table 10. Programming spacesNote: The sequence 5xh and Axh must be executing without instructions between them other-wis

37T89C51CC01Rev. D – 17-Dec-01Figure 12. Column Latches Loading ProcedureNote: The last page address used when loading the column latch is the one use

38T89C51CC01Rev. D – 17-Dec-01• Launch the programming by writing the data sequence 52h followed by A2h inFCON register (only from FM1).The end of the

39T89C51CC01Rev. D – 17-Dec-01Figure 14. Hardware Programming Procedure9.3.7 Reading the FLASHSpacesUser The following procedure is used to read the U

4T89C51CC01Rev. D – 17-Dec-01P1.2/AN2P1.4/AN4 P1.0/AN0P1.3/AN3P1.5/AN5P1.1/AN1NCP1.6/AN6NCP1.7/AN7EANCNC NC RESETNC P0.6P0.5P0.7PSENNCNCVDDVSSVAGNDVAR

40T89C51CC01Rev. D – 17-Dec-01Figure 15. Reading Procedure9.3.8 Flash Protection fromParallel ProgrammingThe three lock bits in Hardware Security Byte

41T89C51CC01Rev. D – 17-Dec-019.4 RegistersFCON RegisterFCON (S:D1h)FLASH Control RegisterReset Value= 0000 0000b76543210FPL3 FPL2 FPL1 FPL0 FPS FMOD1

42T89C51CC01Rev. D – 17-Dec-0110. In-System-Programming (ISP)With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flashtechnolo

43T89C51CC01Rev. D – 17-Dec-0110.2 Boot Process10.2.1 Software boot processexampleMany algorithms can be used for the software boot process. Before de

44T89C51CC01Rev. D – 17-Dec-01Figure 17. Hardware Boot Process Algorithm10.3 Application-Programming-InterfaceSeveral Application Program Interface (A

45T89C51CC01Rev. D – 17-Dec-01Table 12. List of API10.4 XROW Bytes Table 13. Xrow mappingAPI CALL DescriptionPROGRAM DATA BYTE Write a byte in flash m

46T89C51CC01Rev. D – 17-Dec-0110.5 Hardware SecurityByteTable 14. Hardware Security byteDefault value after erasing chip: FFhNote: Only the 4 MSB bits

47T89C51CC01Rev. D – 17-Dec-0111. Serial I/O Port The T89C51CC01 I/O serial port is compatible with the I/O serial port in the 80C52.It provides both

48T89C51CC01Rev. D – 17-Dec-01valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on thestop bit instead of the last dat

49T89C51CC01Rev. D – 17-Dec-0111.3 Given Address Each device has an individual address that is specified in the SADDR register; theSADEN register is a

5T89C51CC01Rev. D – 17-Dec-01Table 1. Pin DescriptionPin Name Type DescriptionVSS GND Circuit ground.VCC Supply Voltage.VAREF Reference Voltage for AD

50T89C51CC01Rev. D – 17-Dec-01For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate withall of the slaves, the mast

51T89C51CC01Rev. D – 17-Dec-01Table 16. SADEN RegisterSADEN (S:B9h)Slave Address Mask RegisterReset Value = 0000 0000bNot bit addressableTable 17. SAD

52T89C51CC01Rev. D – 17-Dec-01Table 19. PCON RegisterPCON (S:87h)Power Control RegisterReset Value = 00X1 0000bNot bit addressable76543210SMOD1 SMOD0

53T89C51CC01Rev. D – 17-Dec-0112. Timers/Counters The T89C51CC01 implements two general-purpose, 16-bit Timers/Counters. Such areidentified as Timer 0

54T89C51CC01Rev. D – 17-Dec-01Figure 22. Timer/Counter x (x= 0 or 1) in Mode 012.2.2 Mode 1 (16-bit Timer) Mode 1 configures Timer 0 as a 16-bit Timer

55T89C51CC01Rev. D – 17-Dec-0112.2.4 Mode 3 (Two 8-bitTimers)Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bitTimers

56T89C51CC01Rev. D – 17-Dec-0112.3.1 Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg-ist

57T89C51CC01Rev. D – 17-Dec-0112.5 Registers Table 20. TCON RegisterTCON (S:88h)Timer/Counter Control RegisterReset Value= 0000 0000b76543210TF1 TR1 T

58T89C51CC01Rev. D – 17-Dec-01Table 21. TMOD RegisterTMOD (S:89h)Timer/Counter Mode ControlRegister.Reset Value= 0000 0000b76543210GATE1 C/T1# M11 M01

59T89C51CC01Rev. D – 17-Dec-01Table 22. TH0 RegisterTH0 (S:8Ch)Timer 0 High Byte Register.Reset Value= 0000 0000bTable 23. TL0 RegisterTL0 (S:8Ah)Time

6T89C51CC01Rev. D – 17-Dec-01P3.0:7 I/OPort 3:Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them ar

60T89C51CC01Rev. D – 17-Dec-01Table 25. TL1 RegisterTL1 (S:8Bh)Timer 1 Low Byte Register.Reset Value= 0000 0000b76543210BitNumberBitMnemonic Descripti

61T89C51CC01Rev. D – 17-Dec-0113. Timer 2 The T89C51CC01 timer 2 is compatible with timer 2 in the 80C52.It is a 16-bit timer/counter: the count is ma

62T89C51CC01Rev. D – 17-Dec-01Figure 27. Auto-Reload Mode Up/Down Counter13.2 ProgrammableClock-OutputIn clock-out mode, timer 2 operates as a 50%-dut

63T89C51CC01Rev. D – 17-Dec-01It is possible to use timer 2 as a baud rate generator and a clock generator simulta-neously. For this configuration, th

64T89C51CC01Rev. D – 17-Dec-0113.3 Registers Table 26. T2CON RegisterT2CON (S:C8h)Timer 2 Control RegisterReset Value = 0000 0000bBit addressable76543

65T89C51CC01Rev. D – 17-Dec-01Table 27. T2MOD RegisterT2MOD (S:C9h)Timer 2 Mode Control RegisterReset Value = XXXX XX00bNot bit addressableTable 28. T

66T89C51CC01Rev. D – 17-Dec-01Table 29. TL2 RegisterTL2 (S:CCh)Timer 2 Low Byte RegisterReset Value = 0000 0000bNot bit addressableTable 30. RCAP2H Re

67T89C51CC01Rev. D – 17-Dec-0114. WatchDog Timer T89C51CC01 contains a powerful programmable hardware WatchDog Timer (WDT)that automatically resets th

68T89C51CC01Rev. D – 17-Dec-0114.1 WatchDogProgrammingThe three lower bits (S0, S1, S2) located into WDTPRG register permit to program theWDT duration

69T89C51CC01Rev. D – 17-Dec-01interrupt is pulled high. It is suggested that the WDT be reset during the interrupt servicefor the interrupt used to ex

7T89C51CC01Rev. D – 17-Dec-014.2 I/O Configurations Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. ACPU &quo

70T89C51CC01Rev. D – 17-Dec-01Table 35. WDTRST RegisterWDTRST (S:A6h Write only)WatchDog Timer EnableregisterReset Value = 1111 1111bNote: The WDRST r

71T89C51CC01Rev. D – 17-Dec-0115. Atmel CANControllerThe Atmel CAN Controller provides all the features required to implement the serialcommunication

72T89C51CC01Rev. D – 17-Dec-0115.2 CAN ControllerMailbox and RegistersOrganizationThe pagination allows management of the 321 registers including 300(

73T89C51CC01Rev. D – 17-Dec-0115.2.1 Working on messageobjectsThe Page message object register (CANPAGE) is used to select one of the 15 messageobject

74T89C51CC01Rev. D – 17-Dec-0115.3.1 Buffer mode Any message object can be used to define one buffer, including non-consecutive mes-sage objects, and

75T89C51CC01Rev. D – 17-Dec-01Figure 33. CAN Controller interrupt structureTo enable a transmission interrupt:• Enable General CAN IT in the interrupt

76T89C51CC01Rev. D – 17-Dec-01To enable an interrupt on general error:• Enable General CAN IT in the interrupt system register,• Enable interrupt on e

77T89C51CC01Rev. D – 17-Dec-01Figure 35. General structure of a bit periodexample of bit timing determination for CAN baudrate of 500kbit/s:Fosc = 12

78T89C51CC01Rev. D – 17-Dec-0115.6 Fault Confinement With respect to fault confinement, a unit may be in one of the three following status:• error act

79T89C51CC01Rev. D – 17-Dec-0115.7 Acceptance filter Upon a reception hit (i.e., a good comparison between the ID+RTR+RB+IDE receivedand an ID+RTR+RB+

8T89C51CC01Rev. D – 17-Dec-01Figure 1. Port 1, Port 3 and Port 4 StructureNote: The internal pull-up can be disabled on P1 when analog function is sel

80T89C51CC01Rev. D – 17-Dec-0115.8 Data and RemoteframeDescription of the different steps for:•Dataframe,• Remote frame, with automatic reply,• Remote

81T89C51CC01Rev. D – 17-Dec-0115.9 Time TriggerCommunication (TTC)and Message StampingThe T89C51CC01 has a programmable 16-bit Timer (CANTIMH&CANT

82T89C51CC01Rev. D – 17-Dec-0115.10 CAN Autobaud andListening modeTo activate the Autobaud feature, the AUTOBAUD bit in the CANGCON register mustbe se

83T89C51CC01Rev. D – 17-Dec-01// Enable the CAN macroCANGCON = 02h2. Configure message object 3 in reception to receive only standard (11-bit identi-f

84T89C51CC01Rev. D – 17-Dec-01// Find the first message object which generate an interrupt in CANSIT1 andCANSIT2// Select the corresponding message ob

85T89C51CC01Rev. D – 17-Dec-0115.12 CAN SFR’s Table 37. CAN SFR’s with reset values0/8(1)1/9 2/A 3/B 4/C 5/D 6/E 7/FF8hIPL1xxxx x000CH0000 0000CCAP0H0

86T89C51CC01Rev. D – 17-Dec-0115.13 Registers Table 38. CANGCON RegisterCANGCON (S:ABh)CAN General Control RegisterReset Value: 0000 0x00b7654 3210ABR

87T89C51CC01Rev. D – 17-Dec-01Table 39. CANGSTA RegisterCANGSTA (S:AAh)CAN General Status RegisterNote: 1. These fields are Read Only.Reset Value: x0x

88T89C51CC01Rev. D – 17-Dec-01Table 40. CANGIT RegisterCANGIT (S:9Bh)CAN General InterruptNote: 1. These fields are Read Only.Reset Value: 0x00 0000b7

89T89C51CC01Rev. D – 17-Dec-01Table 41. CANTEC RegisterCANTEC (S:9Ch Read Only)CAN Transmit Error CounterReset Value: 00hTable 42. CANREC RegisterCANR

9T89C51CC01Rev. D – 17-Dec-01Figure 3. Port 2 StructureNotes: 1. Port 2 is precluded from use as general purpose I/O Ports when as address/data busdri

90T89C51CC01Rev. D – 17-Dec-01Note: see Figure 33Reset Value: xx00 000xbTable 44. CANEN1 RegisterCANEN1 (S:CEh Read Only)CAN Enable message objectRegi

91T89C51CC01Rev. D – 17-Dec-01Table 45. CANEN2 RegisterCANEN2 (S:CFh Read Only)CAN Enable message objectRegisters 2Reset Value: 0000 0000bTable 46. CA

92T89C51CC01Rev. D – 17-Dec-01Table 47. CANSIT2 RegisterCANSIT2 (S:BBh Read Only)CAN Status Interrupt messageobject Registers 2Reset Value: 0000 0000b

93T89C51CC01Rev. D – 17-Dec-01Table 49. CANIE2 RegisterCANIE2 (S:C3h)CAN Enable Interrupt messageobject Registers 2Reset Value: 0000 0000bTable 50. CA

94T89C51CC01Rev. D – 17-Dec-01Table 51. CANBT2 RegisterCANBT2 (S:B5h)CAN Bit Timing Registers 2Note: The CAN controller bit timing registers must be a

95T89C51CC01Rev. D – 17-Dec-01Table 52. CANBT3 RegisterCANBT3 (S:B6h)CAN Bit Timing Registers 3Note: The CAN controller bit timing registers must be a

96T89C51CC01Rev. D – 17-Dec-01Table 53. CANPAGE RegisterCANPAGE (S:B1h)CAN message object PageRegisterReset Value: 0000 0000bTable 54. CANCONCH Regist

97T89C51CC01Rev. D – 17-Dec-01No default value after resetTable 55. CANSTCH RegisterCANSTCH (S:B2h)CAN message object StatusRegister3-0 DLC3:0Data len

98T89C51CC01Rev. D – 17-Dec-01Note: See Figure 33.No default value after reset.Table 56. CANIDT1 Register for V2.0 part ACANIDT1 for V2.0 part A(S:BCh

99T89C51CC01Rev. D – 17-Dec-01Table 58. CANIDT3 Register for V2.0 part ACANIDT3 for V2.0 part A(S:BEh)CAN Identifier Tag Registers 3No default value a