Rainbow-electronics AT84AD004 User Manual

1 5390A–BDC–06/04Features• Dual ADC with 8-bit Resolution• 500 Msps Sampling Rate per Channel, 1 Gsps in Interlaced Mode• Single or 1:2 Demultiplexed

10AT84AD004 5390A–BDC–06/04Note: One analog input on both cores, clock I samples the analog input on the rising and falling edges. The calibration ph

11 AT84AD004 5390A–BDC–06/04Table 5. Switching PerformancesParameter Symbol Min Typ Max UnitSwitching Performance and Characteristics - See “Timing

12AT84AD004 5390A–BDC–06/04Timing DiagramsFigure 4. Timing Diagram, ADC I or ADC Q, 1:2 DMUX Mode, Clock I for ADC I, Clock Q for ADC QFigure 5. 1:

13 AT84AD004 5390A–BDC–06/04Figure 6. 1:2 DMUX Mode, Clock I = ADC I, Clock I = ADC QCLKOI (= CLKI/4)CLKI CLKOI (= CLKI/2)VINTANN + 1N + 2N + 3Pipel

14AT84AD004 5390A–BDC–06/04Figure 7. 1:1 DMUX Mode, Clock I = ADC I, Clock I = ADC QDOIB[0:7] and DOQB[0:7] are high impedance CLKOQ is high impedan

15 AT84AD004 5390A–BDC–06/04Figure 8. 1:2 DMUX Mode, Clock I = ADC I, Clock IN = ADC QCLKI CLKOI (= CLKI/2)VINTANN + 1N + 4N + 6Pipeline delay = 4 c

16AT84AD004 5390A–BDC–06/04Figure 9. 1:1 DMUX Mode, Clock I = ADC I, Clock IN = ADC QFigure 10. 1:1 DMUX Mode, Decimation Mode Test (1:16 Factor)No

17 AT84AD004 5390A–BDC–06/04Figure 11. Data Ready ResetFigure 12. Data Ready Reset 1:1 DMUX ModeNote: The Data Ready Reset is taken into account on

18AT84AD004 5390A–BDC–06/04Figure 13. Data Ready Reset 1:2 DMUX ModeNotes: 1. In 1:2 DMUX, Fs/2 mode: The Data Ready Reset is taken into account onl

19 AT84AD004 5390A–BDC–06/04Functions DescriptionTable 6. Description of FunctionsName Function VCCAPositive analog power supplyVCCDPositive digita

2AT84AD004 5390A–BDC–06/04Description The AT84AD004 is a monolithic dual 8-bit analog-to-digital converter, offering low 1.4W power consumption and e

20AT84AD004 5390A–BDC–06/04Digital Output Coding (Nominal Settings)Pin DescriptionTable 7. Digital Output Coding (Nominal Setting) Differential Anal

21 AT84AD004 5390A–BDC–06/04CLKQN 128Inverted phase (-) clock input signal (CLKQ)DDRB 126 Synchronous data ready reset I and QDDRBN 127 Inverted phas

22AT84AD004 5390A–BDC–06/04Figure 14. AT84AD004 Pinout (Top View)CLKOIN 122 Inverted phase (-) output clock channel ICLKOQ 132Output clock in-phase

23 AT84AD004 5390A–BDC–06/04Typical Characterization ResultsNominal conditions (unless otherwise specified):•VCCA = 3.3V; VCCD = 3.3V; VCCO = 2.25V•V

24AT84AD004 5390A–BDC–06/04Typical Crosstalk Figure 16. Crosstalk (Fs = 500 Msps)Note: Measured on the AT84AD004TD-EB Evaluation Board.Typical DC, I

25 AT84AD004 5390A–BDC–06/04Figure 18. Typical DNL (Fs = 50 Msps, Fin = 1 MHz, Saturated Input)Typical Dynamic Performances Versus Sampling Frequenc

26AT84AD004 5390A–BDC–06/04Figure 21. THD Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2)Figure 22. SNR Versus Sampling Frequency in N

27 AT84AD004 5390A–BDC–06/04Figure 24. SFDR Versus Input Frequency (Fs = 500 Msps)Figure 25. THD Versus Input Frequency (Fs = 500 Msps)Figure 26.

28AT84AD004 5390A–BDC–06/04Typical Signal Spectrum Figure 27. Fs = 500 Msps and Fin = 20 MHz (1:2 DMUX, Fs/4 DR Type FiSDA = -35 ps, ISA = -50 ps)Fi

29 AT84AD004 5390A–BDC–06/04Figure 29. Fs = 500 Msps and Fin = 500 MHz (1:2 DMUX, Fs/4 DR Type FiSDA = -35 ps, ISA = -50 ps)Note: The spectra are gi

3 AT84AD004 5390A–BDC–06/04Figure 1. Simplified Block DiagramDOIRIDOIRINDOIRQDOIRQNCLKIClock BufferDivider2 to16DRDAILVDSClockBuffer2CLKIODDRB16DOAI

30AT84AD004 5390A–BDC–06/04Typical Performance Sensitivity Versus Power Supplies and TemperatureFigure 31. ENOB Versus VCCA (Fs = 500 Msps, Fin = 25

31 AT84AD004 5390A–BDC–06/04Figure 33. THD Versus VCCA (Fs = 500 Msps, Fin = 250 MHz, 1:2 DMUX, Fs/4 DR Type, ISA = -50 ps)Figure 34. SNR Versus VC

32AT84AD004 5390A–BDC–06/04Figure 35. ENOB Versus Junction Temperature (Fs = 500 Msps, Fin = 250 MHz, 1:2 DMUX, Fs/4 DR Type, ISA = -50 ps)Figure 36

33 AT84AD004 5390A–BDC–06/04Figure 37. THD Versus Junction Temperature (Fs = 500 Msps, Fin = 250 MHz, 1:2 DMUX, Fs/4 DR Type, ISA = -50 ps)Figure 38

34AT84AD004 5390A–BDC–06/04Test and Control Features3-wire Serial Interface Control SettingTable 9. 3-wire Serial Interface Control SettingsMode Cha

35 AT84AD004 5390A–BDC–06/043-wire Serial Interface and Data DescriptionThe 3-wire bus is activated with the control bit mode set to 1. The length of

36AT84AD004 5390A–BDC–06/04Notes: 1. The Internal Settling Adjustment could change independently of the two analog sampling times (TA channels I and

37 AT84AD004 5390A–BDC–06/04Table 11. 3-wire Serial Interface Data Setting Description Setting for Address: 000 D15 D14 D13 D12 D11 D10 D9(1)D8 D7 D

38AT84AD004 5390A–BDC–06/04Notes: 1. D9 must be set to “0”2. Mode standby channel I: use analog input I Vini, Vinib and Clocki.3. Mode standby channe

39 AT84AD004 5390A–BDC–06/04• A minimum of one clock cycle with “sldn” returned at 1 is requested to close the write procedure and make the interface

4AT84AD004 5390A–BDC–06/04Typical ApplicationsFigure 2. Satellite Receiver ApplicationBandpassAmplifier11..12 GHz Local OscillatorBandpassAmplifier1

40AT84AD004 5390A–BDC–06/04Calibration Description The AT84AD004 offers the possibility of reducing offset and gain matching between the two ADC core

41 AT84AD004 5390A–BDC–06/04The calibration phase is necessary when using the AT84AD004 in interlace mode, where one analog input is sampled at both

42AT84AD004 5390A–BDC–06/04Example:Address = 110Data =One should then obtain 01010101 on Port B and 10101010 on Port A.When the dynamic mode is chose

43 AT84AD004 5390A–BDC–06/04The VBE diode’s forward voltage in relation to the junction temperature (in steady-state conditions) is shown in Figure 4

44AT84AD004 5390A–BDC–06/04Figure 45. Simplified Data Ready Reset Buffer ModelFigure 46. Analog Input ModelVCCD/2100Ω VCCDGNDDDDRBDDRBN100Ω50Ω50

45 AT84AD004 5390A–BDC–06/04Figure 47. Data Output Buffer ModelDefinitions of TermsVCCOGNDODOAIO, DOAI7 DOBIO, DOBI7DOAION, DOAI7NDOBION, DOBI7NTabl

46AT84AD004 5390A–BDC–06/04ORTOvervoltage Recovery TimeThe time to recover a 0.2% accuracy at the output, after a 150% full-scale step applied on the

47 AT84AD004 5390A–BDC–06/04TRDR Data Ready Reset DelayThe delay between the falling edge of the Data Ready output asynchronous reset signal (DDRB) a

48AT84AD004 5390A–BDC–06/04Using the AT84AD004 Dual 8-bit 500 Msps ADCDecoupling, Bypassing and Grounding of Power SuppliesThe following figures show

49 AT84AD004 5390A–BDC–06/04Analog Input ImplementationThe analog inputs of the dual ADC have been designed with a double pad implementa-tion as illu

5 AT84AD004 5390A–BDC–06/04Figure 3. Dual Channel Digital Oscilloscope ApplicationNote: Absolute maximum ratings are limiting values (referenced to

50AT84AD004 5390A–BDC–06/04Figure 52. Termination Method for the ADC Analog Inputs in AC Coupling ModeClock Implementation The ADC features two diff

51 AT84AD004 5390A–BDC–06/04Figure 54. Single-ended Termination Method for Clock I or Clock QOutput Termination in 1:1 RatioWhen using the integrate

52AT84AD004 5390A–BDC–06/04Figure 55. Example of Termination for Channel I Used in DMUX 1:1 Ratio (Port B Unused)Note: If the outputs are to be used

53 AT84AD004 5390A–BDC–06/04Figure 56. Dual ADC and ASIC/FPGA Load Block DiagramNote: The demultiplexers may be internal to the ASIC/FPGA system.Por

54AT84AD004 5390A–BDC–06/04Thermal CharacteristicsSimplified Thermal Model for LQFP 144 20 x 20 x 1.4 mmThe following model has been extracted from

55 AT84AD004 5390A–BDC–06/04Thermal Resistance from Junction to AmbientThe thermal resistance from the junction to ambient is 25.2°C/W typical.Note:

56AT84AD004 5390A–BDC–06/04Ordering InformationPart Number Package Temperature Range Screening CommentsAT84XAD004TD LQFP 144 Ambient PrototypePrototy

57 AT84AD004 5390A–BDC–06/04Packaging InformationFigure 58. Package TypeNote: Thermally enhanced package: LQFP 144, 20 x 20 x 1.4 mm.DA1A2ACC0.250.1

Printed on recycled paper.5390A–BDC–06/040MDisclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly co

6AT84AD004 5390A–BDC–06/04Electrical Operating CharacteristicsUnless otherwise specified: •VCCA = 3.3V; VCCD = 3.3V; VCCO = 2.25V•VINI - VINB or VINQ

7 AT84AD004 5390A–BDC–06/04Supply current (2 input clocks, 1:2 DMUX mode) - Analog - Digital - OutputICCAICCDICCO150290180180350215mASupply current

8AT84AD004 5390A–BDC–06/04Note: The gain setting is 0 dB, one clock input, no standby mode [full power mode], 1:1 DMUX, calibration off.Note: The gai

9 AT84AD004 5390A–BDC–06/04Notes: 1. Differential input [-1 dBFS analog input level], gain setting is 0 dB, two input clock signals, no standby mode,