Rainbow-electronics ATA6625 User Manual

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Features
Supply Voltage up to 40V
Operating Voltage V
S
= 5V to 27V
Typically 10 µA Supply Current During Sleep Mode
Typically 57 µA Supply Current in Silent Mode
Linear Low-drop Voltage Regulator:
Normal, Fail-safe, and Silent Mode
ATA6623: V
CC
= 3.3V ±2%
ATA6625: V
CC
= 5.0V ±2%
Sleep Mode: V
CC
is Switched Off
V
CC
Undervoltage Detection with Reset Open Drain Output NRES (4 ms Reset Time)
Voltage Regulator is Short-circuit and Over-temperature Protected
LIN Physical Layer According to LIN Specification Revision 2.0 and SAEJ2602-2
Wake-up Capability via LIN Bus (90 µs Dominant)
TXD Time-out Timer
Bus Pin is Overtemperature and Short-circuit Protected versus GND and Battery
Advanced EMC and ESD Performance
ESD HBM 8 kV at Pins LIN and VS Following STM5.1
Interference and Damage Protection According to ISO/CD7637
Package: SO8
1. Description
ATA6623/ATA6625 is a fully integrated LIN transceiver, designed according to the LIN
specification 2.0, with a low-drop voltage regulator (3.3V/5V/50 mA). The combination
of voltage regulator and bus transceiver makes it possible to develop simple, but pow-
erful, slave nodes in LIN Bus systems. ATA6623/ATA6625 is designed to handle the
low-speed data communication in vehicles (for example, in convenience electronics).
Improved slope control at the LIN driver ensures secure data communication up to
20 kBaud with an RC oscillator for the protocol handling. The bus output is designed
to withstand high voltage. Sleep mode (voltage regulator switched off) and Silent
mode (communication off; V
CC
voltage on) guarantee minimized current consumption.
LIN Bus
Transceiver
with Integrated
Voltage
Regulator
ATA6623
ATA6625
4957E–AUTO–10/07
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Summary of Contents

Page 1 - 1. Description

Features• Supply Voltage up to 40V• Operating Voltage VS = 5V to 27V• Typically 10 µA Supply Current During Sleep Mode• Typically 57 µA Supply Current

Page 2

104957E–AUTO–10/07ATA6623/ATA66255. Fail-safe Features• During a short-circuit at LIN to VBattery, the output limits the output current to IBUS_LIM. D

Page 3

114957E–AUTO–10/07ATA6623/ATA66256. Voltage RegulatorFigure 6-1. VCC Voltage Regulator: Ramp Up and Undervoltage The voltage regulator needs an extern

Page 4

124957E–AUTO–10/07ATA6623/ATA6625Figure 6-2. Power Dissipation: Save Operating Area versus VCC Output Current and Supply Voltage VS at Different Ambie

Page 5

134957E–AUTO–10/07ATA6623/ATA66257. Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage t

Page 6

144957E–AUTO–10/07ATA6623/ATA66258. Electrical Characteristics5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values ref

Page 7

154957E–AUTO–10/07ATA6623/ATA66255 NRES Open Drain Output Pin5.1 Low level output voltageVS≥ 5.5VINRES=1mAINRES= 250 µANRES VNRESLVNRESL0.20.14VVAA5.2

Page 8

164957E–AUTO–10/07ATA6623/ATA66257.7Load regulation maximum5mA < IVCC < 50 mA VCC VCCload0.5 2 % A7.8 Output current limitation VS > 5.5V VCC

Page 9

174957E–AUTO–10/07ATA6623/ATA66259 LIN Bus Receiver9.1Center of receiver thresholdVBUS_CNT =(Vth_dom + Vth_rec)/2LIN VBUS_CNT0.475 × VS0.5 × VS0.525

Page 10 - ATA6623/ATA6625

184957E–AUTO–10/07ATA6623/ATA6625Figure 8-1. Definition of Bus Timing Characteristics 11Receiver Electrical AC Parameters of the LIN Physical LayerLIN

Page 11

194957E–AUTO–10/07ATA6623/ATA6625Figure 8-2. Application Circuit 3GND2EN6TXD5RXDVCC+100 nF100 nF220 pF10 kΩ10 µF22 µF8NRES7Short circuit andovertemper

Page 12

24957E–AUTO–10/07ATA6623/ATA6625Figure 1-1. Block Diagram 2. Pin ConfigurationFigure 2-1. Pinning SO8 3GND2EN6TXD5RXDVCC8NRES7Short circuit andovertem

Page 13

204957E–AUTO–10/07ATA6623/ATA662510. Package Information9. Ordering InformationExtended Type Number Package RemarksATA6623-TAPY SO8 3.3V LIN system ba

Page 14

214957E–AUTO–10/07ATA6623/ATA662511. Revision HistoryPlease note that the following page numbers referred to in this section refer to the specific rev

Page 15

4957E–AUTO–10/07Headquarters InternationalAtmel Corporation2325 Orchard ParkwaySan Jose, CA 95131USATel: 1(408) 441-0311Fax: 1(408) 487-2600Atmel Asia

Page 16

34957E–AUTO–10/07ATA6623/ATA66253. Functional Description3.1 Physical Layer CompatibilitySince the LIN physical layer is independent from higher LIN l

Page 17

44957E–AUTO–10/07ATA6623/ATA66253.7 Input Pin (TXD)In Normal mode the TXD pin is the microcontroller interface to control the state of the LIN output.

Page 18

54957E–AUTO–10/07ATA6623/ATA66254. Mode of OperationFigure 4-1. Mode of Operation Unpowered ModeVBatt = 0Va: VS > 5Vb: VS < 4Vc: Bus wake-up eve

Page 19

64957E–AUTO–10/07ATA6623/ATA66254.1 Normal ModeThis is the normal transmitting and Receiving mode of the LIN Interface, in accordance with LINspecific

Page 20

74957E–AUTO–10/07ATA6623/ATA6625Figure 4-2. Switch to Silent Mode Figure 4-3. LIN Wake-up Waveform Diagram from Silent Mode Delay time silent modetd_s

Page 21

84957E–AUTO–10/07ATA6623/ATA66254.3 Sleep ModeA falling edge at EN while TXD is low switches the IC into Sleep mode. The TXD Signal has tobe logic low

Page 22

94957E–AUTO–10/07ATA6623/ATA6625Figure 4-5. LIN Wake-up Diagram from Sleep Mode 4.4 Fail-safe ModeAt system power-up the device automatically switches

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