Features• Supply Voltage up to 40V• Operating Voltage VS = 5V to 27V• Typically 10 µA Supply Current During Sleep Mode• Typically 57 µA Supply Current
104957E–AUTO–10/07ATA6623/ATA66255. Fail-safe Features• During a short-circuit at LIN to VBattery, the output limits the output current to IBUS_LIM. D
114957E–AUTO–10/07ATA6623/ATA66256. Voltage RegulatorFigure 6-1. VCC Voltage Regulator: Ramp Up and Undervoltage The voltage regulator needs an extern
124957E–AUTO–10/07ATA6623/ATA6625Figure 6-2. Power Dissipation: Save Operating Area versus VCC Output Current and Supply Voltage VS at Different Ambie
134957E–AUTO–10/07ATA6623/ATA66257. Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage t
144957E–AUTO–10/07ATA6623/ATA66258. Electrical Characteristics5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values ref
154957E–AUTO–10/07ATA6623/ATA66255 NRES Open Drain Output Pin5.1 Low level output voltageVS≥ 5.5VINRES=1mAINRES= 250 µANRES VNRESLVNRESL0.20.14VVAA5.2
164957E–AUTO–10/07ATA6623/ATA66257.7Load regulation maximum5mA < IVCC < 50 mA VCC VCCload0.5 2 % A7.8 Output current limitation VS > 5.5V VCC
174957E–AUTO–10/07ATA6623/ATA66259 LIN Bus Receiver9.1Center of receiver thresholdVBUS_CNT =(Vth_dom + Vth_rec)/2LIN VBUS_CNT0.475 × VS0.5 × VS0.525
184957E–AUTO–10/07ATA6623/ATA6625Figure 8-1. Definition of Bus Timing Characteristics 11Receiver Electrical AC Parameters of the LIN Physical LayerLIN
194957E–AUTO–10/07ATA6623/ATA6625Figure 8-2. Application Circuit 3GND2EN6TXD5RXDVCC+100 nF100 nF220 pF10 kΩ10 µF22 µF8NRES7Short circuit andovertemper
24957E–AUTO–10/07ATA6623/ATA6625Figure 1-1. Block Diagram 2. Pin ConfigurationFigure 2-1. Pinning SO8 3GND2EN6TXD5RXDVCC8NRES7Short circuit andovertem
204957E–AUTO–10/07ATA6623/ATA662510. Package Information9. Ordering InformationExtended Type Number Package RemarksATA6623-TAPY SO8 3.3V LIN system ba
214957E–AUTO–10/07ATA6623/ATA662511. Revision HistoryPlease note that the following page numbers referred to in this section refer to the specific rev
4957E–AUTO–10/07Headquarters InternationalAtmel Corporation2325 Orchard ParkwaySan Jose, CA 95131USATel: 1(408) 441-0311Fax: 1(408) 487-2600Atmel Asia
34957E–AUTO–10/07ATA6623/ATA66253. Functional Description3.1 Physical Layer CompatibilitySince the LIN physical layer is independent from higher LIN l
44957E–AUTO–10/07ATA6623/ATA66253.7 Input Pin (TXD)In Normal mode the TXD pin is the microcontroller interface to control the state of the LIN output.
54957E–AUTO–10/07ATA6623/ATA66254. Mode of OperationFigure 4-1. Mode of Operation Unpowered ModeVBatt = 0Va: VS > 5Vb: VS < 4Vc: Bus wake-up eve
64957E–AUTO–10/07ATA6623/ATA66254.1 Normal ModeThis is the normal transmitting and Receiving mode of the LIN Interface, in accordance with LINspecific
74957E–AUTO–10/07ATA6623/ATA6625Figure 4-2. Switch to Silent Mode Figure 4-3. LIN Wake-up Waveform Diagram from Silent Mode Delay time silent modetd_s
84957E–AUTO–10/07ATA6623/ATA66254.3 Sleep ModeA falling edge at EN while TXD is low switches the IC into Sleep mode. The TXD Signal has tobe logic low
94957E–AUTO–10/07ATA6623/ATA6625Figure 4-5. LIN Wake-up Diagram from Sleep Mode 4.4 Fail-safe ModeAt system power-up the device automatically switches
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