Rainbow-electronics U3745BM User Manual

1Features• Supply Voltage 4.5 V to 5.5 V• Operating Temperature Range -40°C to +85°C• Minimal External Circuitry Requirements, No RF Components on the

10U3745BM4663A–RKE–06/03Polling Circuit and Control LogicThe receiver is designed to consume less than 1 mA while being sensitive to signalsfrom a cor

11U3745BM4663A–RKE–06/03• USA Applications (fXTO = 4.90625 MHz, MODE = L, TClk = 2.0383 µs)• Europe Applications (fXTO = 6.76438 MHz, MODE = H, TClk =

12U3745BM4663A–RKE–06/03XSleepTemp = 1 implies the temporary extension factor. The extended sleep time is usedas long as every bit check is OK. If the

13U3745BM4663A–RKE–06/03Figure 8. Timing Diagram for a Completely Successful Bit Check Bit Check Mode In bit check mode, the incoming data stream is

14U3745BM4663A–RKE–06/03TLim_min = Lim_min ´ TXClkTLim_max = (Lim_max –1) ´ TXClkLim_min and Lim_max are defined by a 5-bit word each within the LIMIT

15U3745BM4663A–RKE–06/03Figure 12. Timing Diagram for Failed Bit Check (condition: CV_Lim ³ Lim_max) Duration of the Bit Check If no transmitter sign

16U3745BM4663A–RKE–06/03Figure 13. Synchronization of the Demodulator Output Figure 14. Debouncing of the Demodulator Output Figure 15. Steady L St

17U3745BM4663A–RKE–06/03this pulse, the sleep time TSleep elapses. The receiver remains in sleep mode as long asENABLE is held to ‘L’. If the receiver

18U3745BM4663A–RKE–06/03Table 2. Effect of Bit 1 and Bit 2 in Programming the RegistersTable 4 and the following illustrate the effect of the individ

19U3745BM4663A–RKE–06/03Table 5. Effect of the Configuration Word NBitcheckTable 6. Effect of the Configuration Bit VPOUTTable 7. Effect of the Con

2U3745BM4663A–RKE–06/03System Block Diagram Pin ConfigurationFigure 1. Pinning SO20 Demod.IF AmpLNA VCOPLL XTODatainterfaceU3745BM1...3µCPoweramp.XTO

20U3745BM4663A–RKE–06/03Table 9. Effect of the Configuration Word Lim_minTable 10. Effect of the Configuration Word Lim_maxConservation of the Regis

21U3745BM4663A–RKE–06/03• If the receiver is set back to polling mode via pin DATA, RM cannot be canceled by accident if t1 is applied according to th

22U3745BM4663A–RKE–06/03Figure 20. One-wire Connection to a Microcontroller To start programming, the serial data line DATA is pulled to ‘L’ for the

23U3745BM4663A–RKE–06/03Absolute Maximum RatingsParameters Symbol Min. Max. UnitSupply voltage VS6VPower dissipation Ptot450 mWJunction temperature Tj

24U3745BM4663A–RKE–06/03XTO operating frequencyXTO crystal frequency,appropriate load capacitance must be connected to XTAL6.764375 MHz4.90625 MHzfXTO

25U3745BM4663A–RKE–06/03Threshold voltage for reset VThRESET1.95 2.8 3.75 VDigital PortsData output- Saturation voltage LOW- Internal pull-up resistor

26U3745BM4663A–RKE–06/03Time for Bit checkAverage bit check time while pollingBR_Range0BR_Range1BR_Range2BR_Range3TBitcheck0.450.240.140.140.470.260.1

27U3745BM4663A–RKE–06/03Programming start pulse (Figure 16, Figure 19)BR_Range0BR_Range1BR_Range2BR_Range3after PORt1 21881104561290116563176317631763

28U3745BM4663A–RKE–06/03Package Information Ordering InformationExtended Type Number Package RemarksU3745BM-MFL SO20TubeU3745BM-MFLG3 SO20Taped and re

Printed on recycled paper.© Atmel Corporation 2003.Atmel Corporation makes no warranty for the use of its products, other than those expressly contai

3U3745BM4663A–RKE–06/03Pin DescriptionPin Symbol Function1 NC Not connected2 ASK ASK high3 CDEM Lower cut-off frequency data filter4 AVCC Analog power

4U3745BM4663A–RKE–06/03Block Diagram Demodulatorand data filterIF AmpIF Amp4th OrderLPF3 MHzLPF3 MHzDEMOD_OUTLimiter outRSSISensitivityreductionStandb

5U3745BM4663A–RKE–06/03RF Front EndThe RF front end of the receiver is a heterodyne configuration that converts the inputsignal into a 1-MHz IF signal

6U3745BM4663A–RKE–06/03To determine fLO, the construction of the IF filter must be considered at this point. Thenominal IF frequency is fIF= 1 MHz. To

7U3745BM4663A–RKE–06/03Figure 3. Input Matching Network with SAW Filter Figure 4. Input Matching Network without SAW Filter Please note that for all

8U3745BM4663A–RKE–06/03Analog Signal ProcessingIF Amplifier The signals coming from the RF front end are filtered by the fully integrated 4th-order IF

9U3745BM4663A–RKE–06/03The U3745BM is designed to operate with data coding where the DC level of the datasignal is 50%. This is valid for Manchester a