Rainbow-electronics AT90S2313 User Manual

1Features• Utilizes the AVR®RISC Architecture• AVR – High-performance and Low-power RISC Architecture– 118 Powerful Instructions – Most Single Clock C

10AT90S23130839I–AVR–06/02Program and DataAddressing ModesThe AT90S2313 AVR RISC microcontroller supports powerful and efficient addressingmodes for a

11AT90S23130839I–AVR–06/02Operand address is contained in 6 bits of the instruction word. n is the destination orsource register address.Data Direct F

12AT90S23130839I–AVR–06/02Data Indirect with Pre-decrementFigure 15. Data Indirect Addressing with Pre-decrementThe X-, Y-, or Z-register is decrement

13AT90S23130839I–AVR–06/02Indirect Program Addressing,IJMP and ICALLFigure 18. Indirect Program Memory AddressingProgram execution continues at addres

14AT90S23130839I–AVR–06/02Memory Access andInstruction ExecutionTimingThis section describes the general access timing concepts for instruction execut

15AT90S23130839I–AVR–06/02Figure 22. On-chip Data SRAM Access CyclesI/O Memory The I/O space definition of the AT90S2313 is shown in Table 1.System Cl

16AT90S23130839I–AVR–06/02Note: 1. Reserved and unused locations are not shown in the table.All AT90S2313 I/O and peripherals are placed in the I/O sp

17AT90S23130839I–AVR–06/02• Bit 5 – H: Half-carry FlagThe Half-carry Flag H indicates a Half-carry in some arithmetic operations. See theInstruction S

18AT90S23130839I–AVR–06/02Reset and InterruptHandlingThe AT90S2313 provides 10 different interrupt sources. These interrupts and the sepa-rate Reset V

19AT90S23130839I–AVR–06/02Reset Sources The AT90S2313 has three sources of reset:• Power-on Reset. The MCU is reset when the supply voltage is below t

2AT90S23130839I–AVR–06/02Description The AT90S2313 is a low-power CMOS 8-bit microcontroller based on the AVR RISCarchitecture. By executing powerful

20AT90S23130839I–AVR–06/02Power-on Reset A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Asshown in Figure 23, an inter

21AT90S23130839I–AVR–06/02External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longerthan 50 ns will generate a

22AT90S23130839I–AVR–06/02interrupt. Some of the Interrupt Flags can also be cleared by writing a logical “1” to theflag bit position(s) to be cleared

23AT90S23130839I–AVR–06/02General Interrupt FLAGRegister – GIFR• Bit 7 – INTF1: External Interrupt Flag1When an edge on the INT1 pin triggers an inter

24AT90S23130839I–AVR–06/02• Bit 3 – TICIE1: Timer/Counter1 Input Capture Interrupt EnableWhen the TICIE1 bit is set (one) and the I-bit in the Status

25AT90S23130839I–AVR–06/02• Bit 2 – Res: Reserved BitThis bit is a reserved bit in the AT90S2313 and always reads as zero.• Bit 1 – TOV0: Timer/Counte

26AT90S23130839I–AVR–06/02• Bit 4 – SM: Sleep ModeThis bit selects between the two available sleep modes. When SM is cleared (zero), Idlemode is selec

27AT90S23130839I–AVR–06/02Sleep Modes To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc-tion must be executed. If an

28AT90S23130839I–AVR–06/02The four different prescaled selections are: CK/8, CK/64, CK/256, and CK/1024, whereCK is the Oscillator clock. For the two

29AT90S23130839I–AVR–06/02Timer/Counter0 ControlRegister – TCCR0• Bits 7..3 – Res: Reserved BitsThese bits are reserved bits in the AT90S2313 and alwa

3AT90S23130839I–AVR–06/02selectable power-saving modes. The Idle mode stops the CPU while allowing theSRAM, Timer/Counters, SPI port and interrupt sys

30AT90S23130839I–AVR–06/0216-bit Timer/Counter1 Figure 30 shows the block diagram for Timer/Counter1.Figure 30. Timer/Counter1 Block DiagramThe 16-bit

31AT90S23130839I–AVR–06/02Timer/Counter1 can also be used as an 8-, 9-, or 10-bit Pulse Width Modulator. In thismode the counter and the OCR1 Register

32AT90S23130839I–AVR–06/02• Bits 1, 0 – PWM11, PWM10: Pulse Width Modulator Select BitsThese bits select PWM operation of Timer/Counter1 as specified

33AT90S23130839I–AVR–06/02• Bits 2,1,0 – CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0The Clock Select1 bits 2, 1, and 0 define the prescaling sour

34AT90S23130839I–AVR–06/02The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with readand write access. If Timer/Counter1 is wri

35AT90S23130839I–AVR–06/02The TEMP Register is also used when accessing TCNT1 and OCR1A. If the main pro-gram and interrupt routines perform access to

36AT90S23130839I–AVR–06/02During the time between the write and the latch operations, a read from OCR1A willread the contents of the temporary locatio

37AT90S23130839I–AVR–06/02Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator that runs at 1 MHz.This is the typical value

38AT90S23130839I–AVR–06/021. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” mustbe written to WDE even though it is set to

39AT90S23130839I–AVR–06/02EEPROM Read/WriteAccessThe EEPROM Access Registers are accessible in the I/O space.The write access time is in the range of

4AT90S23130839I–AVR–06/02Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier that canbe configured for us

40AT90S23130839I–AVR–06/02EEPROM Control Register –EECR• Bit 7..3 – Res: Reserved BitsThese bits are reserved bits in the AT90S2313 and will always re

41AT90S23130839I–AVR–06/02Prevent EEPROMCorruptionDuring periods of low VCC, the EEPROM data can be corrupted because the supply volt-age is too low f

42AT90S23130839I–AVR–06/02UART The AT90S2313 features a full duplex (separate Receive and Transmit Registers) Uni-versal Asynchronous Receiver and Tra

43AT90S23130839I–AVR–06/02tus Register (USR) is set. When this bit is set (one), the UART is ready to receive thenext character. At the same time as t

44AT90S23130839I–AVR–06/02found to be logical “1”s, the start bit is rejected as a noise spike and the receiver startslooking for the next 1-to-0 tran

45AT90S23130839I–AVR–06/02UART ControlThe UART I/O Data Register –UDRThe UDR Register is actually two physically separate registers sharing the same I

46AT90S23130839I–AVR–06/02• Bit 4 – FE: Framing ErrorThis bit is set if a Framing Error condition is detected (i.e., when the stop bit of an incom-ing

47AT90S23130839I–AVR–06/02• Bit 1 – RXB8: Receive Data Bit 8When CHR9 is set (one), RXB8 is the ninth data bit of the received character.• Bit 0 – TXB

48AT90S23130839I–AVR–06/02UART Baud Rate Register –UBRRThe UBRR Register is an 8-bit read/write register that specifies the UART Baud Rateaccording to

49AT90S23130839I–AVR–06/02• Bit 5 – ACO: Analog Comparator OutputACO is directly connected to the comparator output.• Bit 4 – ACI: Analog Comparator I

5AT90S23130839I–AVR–06/02ArchitecturalOverviewThe fast-access Register File concept contains 32 x 8-bit general purpose working reg-isters with a sing

50AT90S23130839I–AVR–06/02I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digitalI/O ports. This means that the

51AT90S23130839I–AVR–06/02The Port B Input Pins address (PINB) is not a register; this address enables access tothe physical value on each Port B pin.

52AT90S23130839I–AVR–06/02Port B Schematics Note that all port pins are synchronized. The synchronization latches are, however, notshown in the figure

53AT90S23130839I–AVR–06/02Figure 39. Port B Schematic Diagram (Pin PB3)Figure 40. Port B Schematic Diagram (Pins PB2 and PB4)PB3DDB3MOSPULL-UPRESETRQD

54AT90S23130839I–AVR–06/02Figure 41. Port B Schematic Diagram (Pin PB5)Figure 42. Port B Schematic Diagram (Pin PB6)

55AT90S23130839I–AVR–06/02Figure 43. Port B Schematic Diagram (Pin PB7)Port D Three I/O memory address locations are allocated for the Port D: one eac

56AT90S23130839I–AVR–06/02Port D Data Register – PORTDPort D Data Direction Register– DDRDPort D Input Pins Address –PINDThe Port D Input Pins address

57AT90S23130839I–AVR–06/02• INT1 – Port D, Bit 3INT1, External Interrupt Source 1. The PD3 pin can serve as an external interruptsource to the MCU. Se

58AT90S23130839I–AVR–06/02Figure 45. Port D Schematic Diagram (Pin PD1)Figure 46. Port D Schematic Diagram (Pins PD2 and PD3)DATA BUSDDQQRESETRESETCCW

59AT90S23130839I–AVR–06/02Figure 47. Port D Schematic Diagram (Pins PD4 and PD5)Figure 48. Port D Schematic Diagram (Pin PD6)DATA BUSDDQQRESETRESETCCW

6AT90S23130839I–AVR–06/02The I/O memory space contains 64 addresses for CPU peripheral functions such ascontrol registers, Timer/Counters, A/D convert

60AT90S23130839I–AVR–06/02Memory ProgrammingProgram and DataMemory Lock BitsThe AT90S2313 MCU provides two Lock bits that can be left unprogrammed (“1

61AT90S23130839I–AVR–06/02within the self-timed write instruction in the Serial Programming mode. During program-ming, the supply voltage must be in a

62AT90S23130839I–AVR–06/02Enter Programming Mode The following algorithm puts the device in Parallel Programming mode:1. Apply supply voltage accordin

63AT90S23130839I–AVR–06/025. Give WR a tWLWH_CEwide negative pulse to execute Chip Erase. See Table 26fortWLWH_CEvalue. Chip Erase does not generate a

64AT90S23130839I–AVR–06/02The loaded command and address are retained in the device during programming. Forefficient programming, the following should

65AT90S23130839I–AVR–06/02Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming theFlash” for details on c

66AT90S23130839I–AVR–06/02Reading the Fuse and LockBitsThe algorithm for reading the Fuse and Lock bits is as follows (refer to “Programmingthe Flash”

67AT90S23130839I–AVR–06/02Parallel ProgrammingCharacteristicsFigure 52. Parallel Programming TimingNotes: 1. Use tWLWH_CEforchiperaseandtWLWH_PFBfor p

68AT90S23130839I–AVR–06/02Serial Downloading Both the program and data memory arrays can be programmed using the serial SPI buswhile RESETis pulled to

69AT90S23130839I–AVR–06/02ing the third byte of the Programming Enable instruction. Whether the echo iscorrect or not, all four bytes of the instructi

7AT90S23130839I–AVR–06/02General PurposeRegister FileFigure 6 shows the structure of the 32 general purpose registers in the CPU.Figure 6. AVR CPU Gen

70AT90S23130839I–AVR–06/02Data Polling Flash When a byte is being programmed into the Flash, reading the address location beingprogrammed will give th

71AT90S23130839I–AVR–06/02Serial ProgrammingCharacteristicsFigure 55. Serial Programming TimingTable 29. Serial Programming Characteristics, TA=-40°Ct

72AT90S23130839I–AVR–06/02Electrical CharacteristicsAbsolute Maximum Ratings*Operating Temperature... -55°Cto+125°C*NOT

73AT90S23130839I–AVR–06/02Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low.2. “Min” means the lowest value where

74AT90S23130839I–AVR–06/02TypicalCharacteristicsThe following charts show typical behavior. These figures are not tested during manu-facturing. All cu

75AT90S23130839I–AVR–06/02Figure 58. Active Supply Current vs. VCCFigure 59. Idle Supply Current vs. Frequency0246810122 2.5 3 3.5 4 4.5 5 5.5 6ACTIVE

76AT90S23130839I–AVR–06/02Figure 60. Idle Supply Current vs. VCCFigure 61. Power-down Supply Current vs. VCCIDLE SUPPLY CURRENT vs. VccIcc (mA)Vcc(V)F

77AT90S23130839I–AVR–06/02Figure 62. Power-down Supply Current vs. VCCFigure 63. Analog Comparator Current vs. VCC0204060801001201401602 2.5 3 3.5 4 4

78AT90S23130839I–AVR–06/02Note: Analog Comparator offset voltage is measured as absolute offset.Figure 64. Analog Comparator Offset Voltage vs. Common

79AT90S23130839I–AVR–06/02Figure 66. Analog Comparator Input Leakage CurrentFigure 67. Watchdog Oscillator Frequency vs. VCC6050403020100-100 0.5 1.51

8AT90S23130839I–AVR–06/02In the different addressing modes these address registers have functions as fixed dis-placement, automatic increment and decr

80AT90S23130839I–AVR–06/02Note: Sink and source capabilities of I/O ports are measured on one pin at a time.Figure 68. Pull-up Resistor Current vs. In

81AT90S23130839I–AVR–06/02Figure 70. I/O Pin Sink Current vs. Output VoltageFigure 71. I/O Pin Source Current vs. Output Voltage0102030405060700 0.5 1

82AT90S23130839I–AVR–06/02Figure 72. I/O Pin Sink Current vs. Output VoltageFigure 73. I/O Pin Source Current vs. Output Voltage05101520250 0.5 1 1.5

83AT90S23130839I–AVR–06/02Figure 74. I/O Pin Input Threshold Voltage vs. VCCFigure 75. I/O Pin Input Hysteresis vs. VCC00.511.522.52.7 4.0 5.0Threshol

84AT90S23130839I–AVR–06/02Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory ad

85AT90S23130839I–AVR–06/02Instruction Set SummaryMnemonic Operands Description Operation Flags # ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add

86AT90S23130839I–AVR–06/02DATA TRANSFER INSTRUCTIONSMOV Rd, Rr Move between Registers Rd ← Rr None 1LDI Rd, K Load Immediate Rd ← K None 1LD Rd, X Loa

87AT90S23130839I–AVR–06/02Ordering InformationSpeed (MHz) Power Supply Ordering Code Package Operation Range4 2.7 - 6.0V AT90S2313-4PCAT90S2313-4SC20P

88AT90S23130839I–AVR–06/02Packaging Information20P3 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 20P3, 20-lead (0.300"/7.62 m

89AT90S23130839I–AVR–06/0220S7.60 (0.2992)7.40 (0.2914)0.51(0.020)0.33(0.013)10.65 (0.419)10.00 (0.394)PIN 1 ID1.27 (0.050) BSC13.00 (0.5118)12.60 (0.

9AT90S23130839I–AVR–06/02SRAM Data Memory Figure 8 shows how the AT90S2313 data memory is organized.Figure 8. SRAM OrganizationThe 224 data memory loc

iAT90S23130839I–AVR–06/02Table of ContentsFeatures... 1P

iiAT90S23130839I–AVR–06/02Parallel Programming ....... 61Parallel Pr

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