Rainbow-electronics ATmega8HVD User Manual

Features• High Performance, Low Power AVR® 8-bit Microcontroller• Advanced RISC Architecture– 124 Powerful Instructions - Most Single Clock Cycle Exec

108052B–AVR–09/08ATmega4HVD/8HVDFigure 6-3. The X-, Y-, and Z-registersIn the different addressing modes these address registers have functions as fix

1008052B–AVR–09/08ATmega4HVD/8HVD19. Voltage Regulator19.1 Features• Linear regulation giving a fixed output voltage (VREG) of 2.2V for VFET > VFOR

1018052B–AVR–09/08ATmega4HVD/8HVD19.3 Battery Pack Short modeThe Voltage Regulator has a separate Short-Circuit Detection mode (RSCD) that can beenabl

1028052B–AVR–09/08ATmega4HVD/8HVDVDROP depends on actual current drawn from VREG.Figure 19-2. Regulator Short-circuit Detection Example19.5 Register D

1038052B–AVR–09/08ATmega4HVD/8HVDThis bit enables the interrupt caused by the ROCWIF Flag.

1048052B–AVR–09/08ATmega4HVD/8HVD20. Battery Protection20.1 Features• Short-circuit Protection• Discharge Over-current Protection• Charge Over-current

1058052B–AVR–09/08ATmega4HVD/8HVDThe Current Battery Protection (CBP) monitors the cell current by sampling the shunt resistorvoltage (RSENSE) connect

1068052B–AVR–09/08ATmega4HVD/8HVD20.6 External Protection InputThe External Protection Input disables both FETs (Charge FET and Discharge FET) immedi-

1078052B–AVR–09/08ATmega4HVD/8HVDFigure 20-1. Example in External protection InputNote: 1. To ensure that the FET switch ON time is as expected, the c

1088052B–AVR–09/08ATmega4HVD/8HVD20.7 Battery Protection CPU InterfaceThe Battery Protection CPU Interface is illustrated in Figure 20-2.Figure 20-2.

1098052B–AVR–09/08ATmega4HVD/8HVD• Bit 1 – BPPLE: Battery Protection Parameter Lock Enable• Bit 0 – BPPL: Battery Protection Parameter LockThe BPCR, B

118052B–AVR–09/08ATmega4HVD/8HVD6.6 Instruction Execution TimingThis section describes the general access timing concepts for instruction execution. T

1108052B–AVR–09/08ATmega4HVD/8HVD20.8.3 BPSCTR – Battery Protection Short-current Timing Register• Bit 7 – Res: Reserved BitsThis bit is reserved and

1118052B–AVR–09/08ATmega4HVD/8HVDNotes: 1. The actual value depends on the actual frequency of the ”Ultra Low Power RC Oscillator” on page 24. See ”El

1128052B–AVR–09/08ATmega4HVD/8HVD20.8.6 BPDOCD – Battery Protection Discharge-Over-current Detection Level Register• Bits 7:0 – DOCDL7:0: Discharge Ov

1138052B–AVR–09/08ATmega4HVD/8HVD20.8.8 BPIMSK – Battery Protection Interrupt Mask Register• Bit 7:5 – Res: Reserved BitsThese bits are reserved and w

1148052B–AVR–09/08ATmega4HVD/8HVD21. FET Control21.1 OverviewThe FET control is used to enable and disable the Charge FET and Discharge FET. Normally,

1158052B–AVR–09/08ATmega4HVD/8HVD21.2 FET Driver21.2.1 Features•Charge-pump for generating suitable gate drive for N-Channel FET switch on high side•

1168052B–AVR–09/08ATmega4HVD/8HVDFigure 21-3. Switching NFET on and off during NORMAL operation-1.00.01.02.03.04.05.06.07.08.09.010.011.012.0Voltage (

1178052B–AVR–09/08ATmega4HVD/8HVD21.3 DUVR – Deep Under-Voltage Recovery Mode operationThe purpose of DUVR mode is to control the Charge FET so that t

1188052B–AVR–09/08ATmega4HVD/8HVD• Bit 1 – DFE: Discharge FET EnableWhen the DFE bit is cleared (zero), the Discharge FET will be disabled regardless

1198052B–AVR–09/08ATmega4HVD/8HVD22. debugWIRE On-chip Debug System22.1 Features• Complete Program Flow Control• Emulates All On-chip Functions, both

128052B–AVR–09/08ATmega4HVD/8HVDWhen an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-abled. The user soft

1208052B–AVR–09/08ATmega4HVD/8HVD• Capacitors connected to the RESET pin must be disconnected when using debugWire.• All external reset sources must b

1218052B–AVR–09/08ATmega4HVD/8HVD23. Self-Programming the Flash23.1 OverviewIn ATmega4HVD/8HVD, there is no Read-While-Write support, and no separate

1228052B–AVR–09/08ATmega4HVD/8HVD23.4 Performing a Page WriteTo execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR an

1238052B–AVR–09/08ATmega4HVD/8HVD23.5.1 EEPROM Write Prevents Writing to SPMCSRNote that an EEPROM write operation will block all software programming

1248052B–AVR–09/08ATmega4HVD/8HVDondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executinginstructions is too lo

1258052B–AVR–09/08ATmega4HVD/8HVDNotes: 1. Default FOSCCAL value after reset.2. FOSCCAL setting used to smooth the transition from one segment to the

1268052B–AVR–09/08ATmega4HVD/8HVDTable 23-3. Explanation of different variables used in Figure 23-1 and the mapping to the Z-pointer for ATmega4HVDVar

1278052B–AVR–09/08ATmega4HVD/8HVD23.6 Register Description23.6.1 SPMCSR – Store Program Memory Control and Status RegisterThe Store Program Memory Con

1288052B–AVR–09/08ATmega4HVD/8HVDThis bit enables the SPM instruction for the next four clock cycles. If written to one togetherwith either CTPB, RFLB

1298052B–AVR–09/08ATmega4HVD/8HVD24. Memory Programming24.1 Program And Data Memory Lock BitsThe ATmega4HVD/8HVD provides two Lock bits which can be l

138052B–AVR–09/08ATmega4HVD/8HVDWhen using the SEI instruction to enable interrupts, the instruction following SEI will be exe-cuted before any pendin

1308052B–AVR–09/08ATmega4HVD/8HVDNote: 1. The default OSCSEL1:0 setting should not be changed. OSCSEL1:0 = ‘00’ is reserved for test purposes. Other v

1318052B–AVR–09/08ATmega4HVD/8HVD24.4 Calibration BytesThe ATmega4HVD/8HVD has a calibration byte for the Fast RC Oscillator. This byte resides ina hi

1328052B–AVR–09/08ATmega4HVD/8HVDThe minimum low and high periods for the serial clock (SCK) input are defined as follows:Low: > 2.2 CPU clock cycl

1338052B–AVR–09/08ATmega4HVD/8HVDaddress. When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction is alt

1348052B–AVR–09/08ATmega4HVD/8HVDNotes: 1. Not all instructions are applicable for all parts.2. a = address.3. Bits are programmed ‘0’, unprogrammed ‘

1358052B–AVR–09/08ATmega4HVD/8HVDFigure 24-2. Serial Programming Instruction example24.7 High-voltage Serial ProgrammingThis section describes how to

1368052B–AVR–09/08ATmega4HVD/8HVD24.8 High-voltage Serial Programming AlgorithmTo program and verify the ATmega4HVD/8HVD in the High-voltage Serial Pr

1378052B–AVR–09/08ATmega4HVD/8HVD24.8.3 Chip EraseThe Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bitsare not rese

1388052B–AVR–09/08ATmega4HVD/8HVDFigure 24-4. High-voltage Serial Programming Waveforms24.8.5 Programming the EEPROMThe EEPROM is organized in pages,

1398052B–AVR–09/08ATmega4HVD/8HVDTable 24-14. High-voltage Serial Programming Instruction Set for ATmega4HVD/8HVDInstructionInstruction FormatOperatio

148052B–AVR–09/08ATmega4HVD/8HVD7. AVR Memories7.1 OverviewThis section describes the different memories in the ATmega4HVD/8HVD. The AVR architec-ture

1408052B–AVR–09/08ATmega4HVD/8HVDNote: a = address high bits, b = address low bits, d = data in high bits, e = data in low bits, p = data out high bit

1418052B–AVR–09/08ATmega4HVD/8HVD25. Operating CircuitFigure 25-1. Operating Circuit DiagramNotes: 1. Optional. The chip can operate without Charge FE

1428052B–AVR–09/08ATmega4HVD/8HVD26. Electrical CharacteristicsAbsolute Maximum Ratings*26.1 DC CharacteristicsOperating Temperature...

1438052B–AVR–09/08ATmega4HVD/8HVDNotes: 1. All Electrical Characteristics contained in this data sheet are based on initial characterization of actual

1448052B–AVR–09/08ATmega4HVD/8HVD26.3 System and Reset CharacteristicsNotes: 1. Values are guidelines only. Actual values are TBD.2. Not tested in pro

1458052B–AVR–09/08ATmega4HVD/8HVD26.5 General I/O Lines CharacteristicsNotes: 1. Applicable for all except PC0/PC1.2. “Min” means the lowest value whe

1468052B–AVR–09/08ATmega4HVD/8HVDNotes: 1. All DC Characteristics contained in this data sheet are based on simulation and characterization of other A

1478052B–AVR–09/08ATmega4HVD/8HVDADC CharacteristicsNotes: 1. Values are guidelines only.2. All characteristics contained in this data sheet are based

1488052B–AVR–09/08ATmega4HVD/8HVD26.6 Programming Characteristics26.6.1 Serial ProgrammingFigure 26-1. Serial Programming WaveformsFigure 26-2. Serial

1498052B–AVR–09/08ATmega4HVD/8HVD26.6.2 High-voltage Serial ProgrammingFigure 26-3. High-voltage Serial Programming TimingTable 26-9. High-voltage Ser

158052B–AVR–09/08ATmega4HVD/8HVD7.3 SRAM Data MemoryFigure 7-2 shows how the ATmega4HVD/8HVD SRAM Memory is organized.The ATmega4HVD/8HVD is a complex

1508052B–AVR–09/08ATmega4HVD/8HVD27. Typical Characteristics – TBDThe following charts show typical behavior. These figures are not tested during manu

1518052B–AVR–09/08ATmega4HVD/8HVD28. Register SummaryAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page(0xFF) Reserved – – – – – – – –(

1528052B–AVR–09/08ATmega4HVD/8HVD(0xBF) Reserved – – – – – – – –(0xBE) Reserved – – – – – – – –(0xBD) Reserved – – – – – – – –(0xBC) Reserved – – – –

1538052B–AVR–09/08ATmega4HVD/8HVD(0x7D) Reserved – – – – – – – –(0x7C) Reserved – – – – – – – –(0x7B) Reserved – – – – – – – –(0x7A) ADCSRA ADEN ADSC

1548052B–AVR–09/08ATmega4HVD/8HVDNotes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O me

1558052B–AVR–09/08ATmega4HVD/8HVD29. Instruction Set SummaryMnemonics Operands Description Operation Flags #ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD

1568052B–AVR–09/08ATmega4HVD/8HVDBRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2BRIE k Branch if Interrupt Enable

1578052B–AVR–09/08ATmega4HVD/8HVDPUSH Rr Push Register on Stack STACK ← Rr None 2POP Rd Pop Register from Stack Rd ← STACK None 2MCU CONTROL INSTRUCTI

1588052B–AVR–09/08ATmega4HVD/8HVD30. Ordering Information30.1 ATmega4HVDNote: This device can also be supplied in wafer form. Please contact your loca

1598052B–AVR–09/08ATmega4HVD/8HVD30.2 ATmega8HVDNote: This device can also be supplied in wafer form. Please contact your local Atmel sales office for

168052B–AVR–09/08ATmega4HVD/8HVDFigure 1. On-chip Data SRAM Access Cycles7.4 EEPROM Data MemoryThe ATmega4HVD/8HVD contains 256 bytes of data EEPROM

1608052B–AVR–09/08ATmega4HVD/8HVD31. Packaging Information31.1 18M1 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 18M1, 18-pad (Sta

1618052B–AVR–09/08ATmega4HVD/8HVD32. Errata32.1 ATmega4HVD32.1.1 All revisionsNo known errata.32.2 ATmega8HVD32.2.1 All revisionsNo known errata.

1628052B–AVR–09/08ATmega4HVD/8HVD33. Datasheet Revision History33.1 Rev. B - 09/0833.2 Rev. A - 09/081. Updated Table 20-2 on page 110 and Table 20-3

i8052B–AVR–09/08ATmega4HVD/8HVDTable of ContentsFeatures ...

ii8052B–AVR–09/08ATmega4HVD/8HVD8.10System Clock Prescaler ...25

iii8052B–AVR–09/08ATmega4HVD/8HVD14.4Register Description ...

iv8052B–AVR–09/08ATmega4HVD/8HVD20 Battery Protection ... 10420.1Features

v8052B–AVR–09/08ATmega4HVD/8HVD24.7High-voltage Serial Programming ...13524.8High

8052B–AVR–09/08Headquarters InternationalAtmel Corporation2325 Orchard ParkwaySan Jose, CA 95131USATel: 1(408) 441-0311Fax: 1(408) 487-2600Atmel AsiaR

178052B–AVR–09/08ATmega4HVD/8HVDtions. Refer to the instruction set section for more details. When using the I/O specificcommands IN and OUT, the I/O

188052B–AVR–09/08ATmega4HVD/8HVD7.6.3 EECR – The EEPROM Control Register• Bits 7:6 – Res: Reserved BitsThese bits are reserved bits in the ATmega4HVD/

198052B–AVR–09/08ATmega4HVD/8HVD4. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.5. Within four clock cycles after setting

28052B–AVR–09/08ATmega4HVD/8HVD1. Pin ConfigurationsFigure 1-1. Dual Row DFN/ MLF-pinout ATmega4HVD/8HVD.A8A7A6A5A4A3A2A1B1B2B3B4B5B6B7B8B9B10Bottom v

208052B–AVR–09/08ATmega4HVD/8HVDAssembly Code ExampleEEPROM_write:; Wait for completion of previous writesbic EECR,EEWErjmp EEPROM_write ; Set up a

218052B–AVR–09/08ATmega4HVD/8HVDThe next code examples show assembly and C functions for reading the EEPROM. Theexamples assume that interrupts are co

228052B–AVR–09/08ATmega4HVD/8HVD8. System Clock and Clock Options8.1 Clock Systems and their DistributionFigure 8-1 presents the principal clock syste

238052B–AVR–09/08ATmega4HVD/8HVDADC. The dedicated ADC clock allows halting the CPU and I/O clocks in order to reduce noisegenerated by digital circui

248052B–AVR–09/08ATmega4HVD/8HVD8.4 Slow RC OscillatorThe Slow RC Oscillator provides a 131 kHz clock (typical value, refer to section "Electrica

258052B–AVR–09/08ATmega4HVD/8HVD8-1 on page 23. The number of Ultra Low Power RC Oscillator cycles used for each time-out isshown in Table 8-2.Note: 1

268052B–AVR–09/08ATmega4HVD/8HVDInterrupts must be disabled when changing prescaler setting to make sure the write procedureis not interrupted.8.11 AD

278052B–AVR–09/08ATmega4HVD/8HVD8.12 OSI – Oscillator Sampling Interface8.12.1 Features•Runtime selectable oscillator input (Slow RC or ULP RC Oscilla

288052B–AVR–09/08ATmega4HVD/8HVD8.12.3 UsageThe Slow RC oscillator represents a highly predictable and accurate clock source over theentire temperatur

298052B–AVR–09/08ATmega4HVD/8HVD8.13 Register Description8.13.1 FOSCCAL – Fast RC Oscillator Calibration Register• Bits 7:0 – FCAL7:0: Fast RC Oscilla

38052B–AVR–09/08ATmega4HVD/8HVD1.1 Pin Descriptions1.1.1 VFETInput to the internal voltage regulator.1.1.2 VCCPin for connection of external decouplin

308052B–AVR–09/08ATmega4HVD/8HVD• Bit 7 – CLKPCE: Clock Prescaler Change EnableThe CLKPCE bit must be written to logic one to enable change of the CLK

318052B–AVR–09/08ATmega4HVD/8HVD• Bit 0 – OSIEN: Oscillator Sampling Interface EnableSetting this bit enables the Oscillator Sampling Interface. When

328052B–AVR–09/08ATmega4HVD/8HVD9. Power Management and Sleep ModesSleep modes enable the application to shut down unused modules in the MCU, thereby

338052B–AVR–09/08ATmega4HVD/8HVDFigure 9-1. Sleep Mode State DiagramNote: 1. For details on BLOD Power-off refer to ”Black-out Detection” on page 40.T

348052B–AVR–09/08ATmega4HVD/8HVDNotes: 1. Discharge FET must be switched off for Charger Detect to be enabled.2. RCOSC_FAST runs in Power-save mode if

358052B–AVR–09/08ATmega4HVD/8HVD9.5 Power-off ModeWhen the SM2:0 bits are written to 100 and the SE bit is set, the SLEEP instruction makes theCPU shu

368052B–AVR–09/08ATmega4HVD/8HVD9.7.3 On-chip Debug SystemA programmed DWEN Fuse enables some parts of the clock system to be running in all sleepmode

378052B–AVR–09/08ATmega4HVD/8HVD• Bit 0 – SE: Sleep EnableThe SE bit must be written to logic one to make the MCU enter the sleep mode when theSLEEP i

388052B–AVR–09/08ATmega4HVD/8HVD10. System Control and Reset10.1 Resetting the AVRDuring reset, all I/O Registers are set to their initial values, and

398052B–AVR–09/08ATmega4HVD/8HVDFigure 10-1. Reset LogicMCU StatusRegister (MCUSR)Reset CircuitDelay CountersCKTIMEOUTWDRFEXTRFPORFDATA BUSClockGenera

48052B–AVR–09/08ATmega4HVD/8HVD2. OverviewThe ATmega4HVD/8HVD is a monitoring and protection circuit for 1-cell Li-ion applicationswith focus on high

408052B–AVR–09/08ATmega4HVD/8HVD10.3 External ResetAn External Reset is generated by a low level on the RESET pin. Reset pulses longer than theminimum

418052B–AVR–09/08ATmega4HVD/8HVDguaranteed and the chip should be forced into Power-off mode. The algorithm used for switch-ing between the two VBLOT

428052B–AVR–09/08ATmega4HVD/8HVDFigure 10-7. Black-out Reset with high current consumption at VREG10.6 ATmega4HVD/8HVD Start-up SequenceThe Voltage Re

438052B–AVR–09/08ATmega4HVD/8HVDchip is powered and an internal Power-on Reset (POR) is generated. During the initial start-upwhen a valid reference f

448052B–AVR–09/08ATmega4HVD/8HVDFigure 10-9. Powering up ATmega4HVD/8HVD (2-FET example)During the initial start-up when a valid reference for the vol

458052B–AVR–09/08ATmega4HVD/8HVD10.7 Watchdog Timer10.7.1 Features•Clocked from Slow RC Oscillator• 3 Operating modes–Interrupt– System Reset– Interru

468052B–AVR–09/08ATmega4HVD/8HVD1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be writ

478052B–AVR–09/08ATmega4HVD/8HVDNote: If the Watchdog is accidentally enabled, for example by a runaway pointer or Black-outcondition, the device will

488052B–AVR–09/08ATmega4HVD/8HVD10.8 Register Description10.8.1 MCUSR – MCU Status RegisterThe MCU Status Register provides information on which reset

498052B–AVR–09/08ATmega4HVD/8HVDIf WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first timeout inthe Watchdog Timer will s

58052B–AVR–09/08ATmega4HVD/8HVDtains a high-voltage tolerant, open-drain IO pin that supports serial communication.Programming can be done in-system u

508052B–AVR–09/08ATmega4HVD/8HVDTable 10-2. Watchdog Timer Prescale Select (Typical Timeout at VCC = 2.2V)WDP3 WDP2 WDP1 WDP0Number of WDT Oscillator

518052B–AVR–09/08ATmega4HVD/8HVD11. InterruptsThis section describes the specifics of the interrupt handling as performed inATmega4HVD/8HVD. For a gen

528052B–AVR–09/08ATmega4HVD/8HVDAddress Labels Code Comments0x0000 rjmp RESET ; Reset Handler0x0001 rjmp BPINT ; Battery Protection Interrupt Handler0

538052B–AVR–09/08ATmega4HVD/8HVD12. External InterruptThe External Interrupts are triggered by the INT1:0 pins. Observe that, if enabled, the interrup

548052B–AVR–09/08ATmega4HVD/8HVDbe changed. Finally, the INTn interrupt flags should be cleared by writing a logical one to itsInterrupt Flag bit (INT

558052B–AVR–09/08ATmega4HVD/8HVDinterrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.This flag is alwa

568052B–AVR–09/08ATmega4HVD/8HVD13. High Voltage I/O PortsAll high voltage AVR ports have true Read-Modify-Write functionality when used as generaldig

578052B–AVR–09/08ATmega4HVD/8HVD13.1 High Voltage Ports as General Digital OutputsThe high voltage ports are high voltage tolerant open collector outp

588052B–AVR–09/08ATmega4HVD/8HVDFigure 13-3. High Voltage Digital I/O(1)Note: 1. WRx, RRx and RPx are common to all pins within the same port. clkI/O

598052B–AVR–09/08ATmega4HVD/8HVD13.2.1 Alternate Functions of Port CThe Port C pins with alternate functions are shown in Table 13-2.The alternate pin

68052B–AVR–09/08ATmega4HVD/8HVD6. AVR CPU Core6.1 OverviewThis section discusses the AVR core architecture in general. The main function of the CPU co

608052B–AVR–09/08ATmega4HVD/8HVD13.3 Register Description13.3.1 PORTC – Port C Data Register13.3.2 PINC – Port C Input Pins AddressBit 76543210––––––P

618052B–AVR–09/08ATmega4HVD/8HVD14. Low Voltage I/O-Ports14.1 OverviewAll low voltage AVR ports have true Read-Modify-Write functionality when used as

628052B–AVR–09/08ATmega4HVD/8HVDNote that enabling the alternate function of some of the port pins does not affect the use of theother pins in the por

638052B–AVR–09/08ATmega4HVD/8HVDIf PORTxn is written logic one when the pin is configured as an output pin, the port pin isdriven high (one). If PORTx

648052B–AVR–09/08ATmega4HVD/8HVDFigure 14-3. Synchronization when Reading an Externally Applied Pin valueConsider the clock period starting shortly af

658052B–AVR–09/08ATmega4HVD/8HVDNote: 1. For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins

668052B–AVR–09/08ATmega4HVD/8HVD14.2.6 Unconnected PinsIf some pins are unused, it is recommended to ensure that these pins have a defined level.Even

678052B–AVR–09/08ATmega4HVD/8HVDFigure 14-5. Alternate Port Functions(1)Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the sa

688052B–AVR–09/08ATmega4HVD/8HVDThe following subsections shortly describe the alternate functions for each port, and relate theoverriding signals to

698052B–AVR–09/08ATmega4HVD/8HVD14.3.1 Alternate Functions of Port BThe Port B pins with alternate functions are shown in Table 14-3.The alternate pin

78052B–AVR–09/08ATmega4HVD/8HVDSix of the 32 registers can be used as three 16-bit indirect address register pointers for DataSpace addressing – enabl

708052B–AVR–09/08ATmega4HVD/8HVD14.4 Register Description14.4.1 MCUCR – MCU Control Register• Bit 4 – PUD: Pull-up DisableWhen this bit is written to

718052B–AVR–09/08ATmega4HVD/8HVD15. Timer/Counter0 and Timer/Counter1 Prescalers15.1 OverviewTimer/Counter1 and Timer/Counter0 share the same prescale

728052B–AVR–09/08ATmega4HVD/8HVD15.4 External Clock SourceAn external clock source applied to the Tn pin can be used as Timer/Counter clock (clkTn). T

738052B–AVR–09/08ATmega4HVD/8HVDIf external pin modes are used for the Timer/Counter n, transitions on the Tn pin will clock thecounter even if the pi

748052B–AVR–09/08ATmega4HVD/8HVD16. Timer/Counter(T/C0,T/C1)16.1 Features• Clear Timer on Compare Match (Auto Reload)• Input Capture unit• Four Indepe

758052B–AVR–09/08ATmega4HVD/8HVD16.2.1 RegistersThe Timer/Counter Low Byte Register (TCNTnL) and Output Compare Registers (OCRnA andOCRnB) are 8-bit r

768052B–AVR–09/08ATmega4HVD/8HVDFigure 16-2. Counter Unit Block DiagramSignal description (internal signals):count Increment or decrement TCNTn by 1.c

778052B–AVR–09/08ATmega4HVD/8HVD16.5.1 Normal 8-bit ModeIn the normal mode, the counter (TCNTnL) is incrementing until it overruns when it passes itsm

788052B–AVR–09/08ATmega4HVD/8HVDare no special cases to consider in the Normal mode, a new counter value can be written any-time. The Output Compare U

798052B–AVR–09/08ATmega4HVD/8HVDFigure 16-4. Input Capture Unit Block DiagramThe Output Compare Register OCRnA is a dual-purpose register that is also

88052B–AVR–09/08ATmega4HVD/8HVD6.3.1 SREG – AVR Status Register• Bit 7 – I: Global Interrupt EnableThe Global Interrupt Enable bit must be set for the

808052B–AVR–09/08ATmega4HVD/8HVD16.6.2 Noise CancelerThe noise canceler improves noise immunity by using a simple digital filtering scheme. Thenoise c

818052B–AVR–09/08ATmega4HVD/8HVDOCFnA as there is only one Output Compare Unit. If the corresponding interrupt is enabled,the Output Compare Flag gene

828052B–AVR–09/08ATmega4HVD/8HVDFigure 16-7. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)Figure 16-8 on page 82 shows the setting of OCFn

838052B–AVR–09/08ATmega4HVD/8HVDThere is one exception in the temporary register usage. In the Output Compare mode the 16-bit Output Compare Register

848052B–AVR–09/08ATmega4HVD/8HVDThe following code examples show how to do an atomic read of the TCNTn register contents.Reading any of the OCRn regis

858052B–AVR–09/08ATmega4HVD/8HVDThe following code examples show how to do an atomic write of the TCNTnH/L register con-tents. Writing any of the OCRn

868052B–AVR–09/08ATmega4HVD/8HVD16.10 Register Description16.10.1 TCCRnA – Timer/Counter n Control Register A• Bit 7– TCWn: Timer/Counter WidthWhen th

878052B–AVR–09/08ATmega4HVD/8HVD16.10.2 TCNTnL – Timer/Counter n Register Low ByteThe Timer/Counter Register TCNTnL gives direct access, both for read

888052B–AVR–09/08ATmega4HVD/8HVDIn 16-bit mode the OCRnB register contains the high byte of the 16-bit Output Compare Reg-ister. To ensure that both t

898052B–AVR–09/08ATmega4HVD/8HVD• Bit 2 – OCFnB: Output Compare Flag n BThe OCFnB bit is set when a Compare Match occurs between the Timer/Counter and

98052B–AVR–09/08ATmega4HVD/8HVD6.4 General Purpose Register FileThe Register File is optimized for the AVR Enhanced RISC instruction set. In order to

908052B–AVR–09/08ATmega4HVD/8HVD17. ADC - Analog-to-Digital Converter17.1 Features• 10-bit Resolution• 78 µs Conversion Time @ clkADC = 167 kHz• Up to

918052B–AVR–09/08ATmega4HVD/8HVD17.2 OperationThe ADC converts an analog input voltage to a 10-bit digital value through successive approx-imation. Fo

928052B–AVR–09/08ATmega4HVD/8HVDFigure 17-2. ADC Timing Diagram, First Conversion (Single Conversion Mode)Figure 17-3. ADC Timing Diagram, Single Conv

938052B–AVR–09/08ATmega4HVD/8HVDanother interrupt wakes up the CPU before the ADC conversion is complete, that inter-rupt will be executed, and an ADC

948052B–AVR–09/08ATmega4HVD/8HVD17.6.3 ADC Accuracy DefinitionsAn n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps(

958052B–AVR–09/08ATmega4HVD/8HVDFigure 17-7. Integral Non-linearity (INL)• Differential Non-linearity (DNL): The maximum deviation of the actual code

968052B–AVR–09/08ATmega4HVD/8HVD17.7 ADC Conversion ResultAfter the conversion is complete (ADIF is high), the conversion result can be found in the A

978052B–AVR–09/08ATmega4HVD/8HVD17.8 Register Description17.8.1 ADCSRA – ADC Control and Status Register A• Bit 7 – ADEN: ADC EnableWriting this bit t

988052B–AVR–09/08ATmega4HVD/8HVD17.8.2 ADCL and ADCH – The ADC Data RegisterWhen an ADC conversion is complete, the result is found in these two regis

998052B–AVR–09/08ATmega4HVD/8HVD18. Voltage Reference ATmega4HVD/8HVD features an internal bandgap reference. This reference is an input refer-ence to