Rainbow-electronics AT45DB161D User Manual

Features• Single 2.5V - 3.6V or 2.7V - 3.6V Supply• RapidS™Serial Interface: 66MHz Maximum Clock Frequency– SPI Compatible Modes 0 and 3• User Configu

103500O–DFLASH–11/2012AT45DB161Dtake place in a maximum time of tSE. During this time, the status register and the RDY/BUSY pin will indicate thatthe

113500O–DFLASH–11/2012AT45DB161D7.8 Main Memory Page Program Through BufferThis operation is a combination of the Buffer Write and Buffer to Main Memo

123500O–DFLASH–11/2012AT45DB161D8.1.2 Disable Sector Protection CommandTo disable the sector protection using the software controlled method, theCS pi

133500O–DFLASH–11/2012AT45DB161DThe table below details the sector protection status for various scenarios of the WP pin, the Enable SectorProtection

143500O–DFLASH–11/2012AT45DB161D9.1.1 Erase Sector Protection Register CommandIn order to modify and change the values of the Sector Protection Regist

153500O–DFLASH–11/2012AT45DB161Dguaranteed. Furthermore, if more than 16-bytes of data is clocked into the device, then the data will wrap backaround

163500O–DFLASH–11/2012AT45DB161D9.1.4 Various Aspects About the Sector Protection RegisterThe Sector Protection Register is subject to a limit of 10,0

173500O–DFLASH–11/2012AT45DB161D10.1.1 Sector Lockdown RegisterSector Lockdown Register is a nonvolatile register that contains 16-bytes of data, as s

183500O–DFLASH–11/2012AT45DB161D10.2 Security RegisterThe device contains a specialized Security Register that can be used for purposes such as unique

193500O–DFLASH–11/2012AT45DB161D10.2.2 Reading the Security RegisterThe Security Register can be read by first asserting theCS pin and then clocking i

23500O–DFLASH–11/2012AT45DB161Doperation. Unlike conventional Flash memories that are accessed randomly with multiple address lines and aparallel inte

203500O–DFLASH–11/2012AT45DB161D11.3 Auto Page RewriteThis mode is only needed if multiple bytes within a page or multiple pages of data are modified

213500O–DFLASH–11/2012AT45DB161DThe device density is indicated using bits five, four, three, and two of the status register. For the AT45DB161D, thef

223500O–DFLASH–11/2012AT45DB161DFigure 12-2. Resume from Deep Power-Down13. “Power of 2” Binary Page Size Option“Power of 2” binary page size Configur

233500O–DFLASH–11/2012AT45DB161D14. Manufacturer and Device ID ReadIdentification information can be read from the device to enable systems to electro

243500O–DFLASH–11/2012AT45DB161D14.2 Operation Mode SummaryThe commands described previously can be grouped into four different categories to better d

253500O–DFLASH–11/2012AT45DB161D15. Command TablesTable 15-1. Read CommandsTable 15-2. Program and Erase CommandsTable 15-3. Protection and Security C

263500O–DFLASH–11/2012AT45DB161DTable 15-4. Additional CommandsTable 15-5. Legacy Commands(1)Notes: 1. These legacy commands are not recommended for n

273500O–DFLASH–11/2012AT45DB161DTable 15-6. Detailed Bit-level Addressing Sequence for Binary Page Size (512-Bytes)Notes: x = Don’t CarePage Size = 51

283500O–DFLASH–11/2012AT45DB161DTable 15-7. Detailed Bit-level Addressing Sequence for Standard DataFlash Page Size (528-Bytes)Notes: P = Page Address

293500O–DFLASH–11/2012AT45DB161D16. Power-on/Reset StateWhen power is first applied to the device, or when recovering from a reset condition, the devi

33500O–DFLASH–11/2012AT45DB161DTable 2-1. Pin ConfigurationsSymbol Name and FunctionAsserted State TypeCSChip Select: Asserting theCS pin selects the

303500O–DFLASH–11/2012AT45DB161D18. Electrical SpecificationsTable 18-1. Absolute Maximum Ratings*Table 18-2. DC and AC Operating RangeTable 18-3. DC

313500O–DFLASH–11/2012AT45DB161DTable 18-4. AC Characteristics – RapidS/Serial InterfaceNote: 1. Values are based on device characterization, not 100%

323500O–DFLASH–11/2012AT45DB161D19. Input Test Waveforms and Measurement LevelstR,tF< 2ns (10% to 90%)20. Output Test Load21. AC WaveformsSix diffe

333500O–DFLASH–11/2012AT45DB161D21.2 Waveform 2 – SPI Mode 3 Compatible (for frequencies up to 66MHz)21.3 Waveform 3 – RapidS Mode 0 (FMAX= 66MHz)21.4

343500O–DFLASH–11/2012AT45DB161DFigure 21-1. RapidS Mode21.6 Reset TimingNote: The CS signal should be in the high state before the RESET signal is de

353500O–DFLASH–11/2012AT45DB161D21.7 Command Sequence for Read/Write Operations for Page Size 512-Bytes (Except StatusRegister Read, Manufacturer and

363500O–DFLASH–11/2012AT45DB161D22.1 Buffer Write22.2 Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)23. Read Operati

373500O–DFLASH–11/2012AT45DB161D23.1 Main Memory Page Read23.2 Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)23.3 Buffer

383500O–DFLASH–11/2012AT45DB161D24. Detailed Bit-level Read Waveform –RapidS Serial Interface Mode 0/Mode 324.1 Continuous Array Read (Legacy Opcode E

393500O–DFLASH–11/2012AT45DB161D24.4 Main Memory Page Read (Opcode: D2H)24.5 Buffer Read (Opcode D4H or D6H)24.6 Buffer Read (Low Frequency: Opcode D1

43500O–DFLASH–11/2012AT45DB161D3. Block Diagram4. Memory ArrayTo provide optimal flexibility, the memory array of the AT45DB161D is divided into three

403500O–DFLASH–11/2012AT45DB161D24.7 Read Sector Protection Register (Opcode 32H)24.8 Read Sector Lockdown Register (Opcode 35H)24.9 Read Security Reg

413500O–DFLASH–11/2012AT45DB161D24.10 Status Register Read (Opcode D7H)24.11 Manufacturer and Device Read (Opcode 9FH)SCKCSSISOMSB23101101011167541011

423500O–DFLASH–11/2012AT45DB161D25. Auto Page Rewrite FlowchartFigure 25-1. Algorithm for Programming or Reprogramming of the Entire Array Sequentiall

433500O–DFLASH–11/2012AT45DB161DFigure 25-2. Algorithm for Randomly Modifying DataNotes: 1. To preserve data integrity, each page of an DataFlash sect

443500O–DFLASH–11/2012AT45DB161D26. Ordering Information26.1 Ordering Code Detail26.2 Green Package Options (Pb/Halide-free/RoHS Compliant)Notes: 1. T

453500O–DFLASH–11/2012AT45DB161D27. Packaging Information27.1 8M1-A – MLF (VDFN)TITLE DRAWING NO. GPC REV. Package Drawing Contact:contact@adestotech.

463500O–DFLASH–11/2012AT45DB161D27.2 8S2 – EIAJ SOICTITLEDRAWING NO. GPCREV.Package Drawing Contact:[email protected] STN F 8S2, 8-lead, 0.

473500O–DFLASH–11/2012AT45DB161D27.3 28T – TSOP, Type 1TITLEDRAWING NO.REV. Package Drawing Contact:[email protected], 28-lead (8 x 13.4mm) P

483500O–DFLASH–11/2012AT45DB161D27.4 24C1 - Ball Grid ArrayTITLEDRAWING NO.REV. Package Drawing Contact:[email protected], 24-ball (5 x 5 Ar

493500O–DFLASH–11/2012AT45DB161D28. Revision HistoryDoc. Rev. Date Comments3500O 11/2012 Update to Adesto Technologies.3500N 05/2010Changed tSE(Typ) 1

53500O–DFLASH–11/2012AT45DB161D5. Device OperationThe device operation is controlled by instructions from the host processor. The list of instructions

503500O–DFLASH–11/2012AT45DB161D29. Errata29.1 No Errata Conditions

Corporate OfficeCalifornia | USAAdesto Headquarters1250 Borregas AvenueSunnyvale, CA 94089 Phone: (+1) 408.400.0578Email: [email protected]© 2012

63500O–DFLASH–11/2012AT45DB161DA low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). Themaximum

73500O–DFLASH–11/2012AT45DB161D6.4 Main Memory Page ReadA main memory page read allows the user to read data directly from any one of the 4,096 pages

83500O–DFLASH–11/2012AT45DB161D7. Program and Erase Commands7.1 Buffer WriteData can be clocked in from the input pin (SI) into either buffer 1 or buf

93500O–DFLASH–11/2012AT45DB161Dpage address bits (A20 - A9) that specify the page in the main memory to be erased and nine don’t care bits. Whena low-