Rainbow-electronics AT45DQ161 User Manual

8790A–DFLASH–11/2012Features Single 2.3V - 3.6V or 2.5V - 3.6V supply Serial Peripheral Interface (SPI) compatible Supports SPI modes 0 and 3 Sup

10AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of

11AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/20125.8 Dual-output Read ArrayThe Dual-output Read Array command is similar to the Continuous Array Re

12AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012The CS pin must remain low during the loading of the opcode, the address bytes, the dummy byte, an

13AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012To load data into a buffer using the binary buffer size (512 bytes), an opcode of 44h for Buffer 1

14AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/20126.6 Main Memory Page Program through Buffer with Built-In EraseThe Main Memory Page Program throug

15AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012The CS pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, the operati

16AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Table 6-1. Block Erase Addressing6.10 Sector EraseThe Sector Erase command can be used to individu

17AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Table 6-2. Sector Erase Addressing6.11 Chip EraseThe Chip Erase command allows the entire main mem

18AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/20126.12 Program/Erase SuspendIn some code and data storage applications, it may not be possible for t

19AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Table 6-4. Operations Allowed and Not Allowed During SuspendCommandOperation During Program Suspen

2AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012DescriptionThe AT45DQ161 is a 2.3V or 2.5V minimum, serial-interface sequential access Flash memory

20AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/20126.13 Program/Erase ResumeThe Program/Erase Resume command allows a suspended program or erase oper

21AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/20127. Sector ProtectionTwo protection methods, hardware and software controlled, are provided for pro

22AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/20127.1.2 Disable Sector Protection To disable the sector protection, a 4-byte command sequence of 3Dh

23AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Figure 7-3. WP Pin and Protection StatusTable 7-3.WP Pin and Protection Status7.3 Sector Protectio

24AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/20127.3.1 Erase Sector Protection Register In order to modify and change the values of the Sector Prot

25AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012clocked into a byte location of the Sector Protection Register, then the protection status of the

26AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/20127.3.4 About the Sector Protection RegisterThe Sector Protection Register is subject to a limit of

27AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/20128. Security Features8.1 Sector LockdownThe device incorporates a sector lockdown mechanism that al

28AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Table 8-3. Sector 0 (0a and 0b) Sector Lockdown Register Byte ValueTable 8-4. Read Sector Lockdown

29AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/20128.2 Security RegisterThe device contains a specialized Security Register that can be used for purp

3AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Table 1-1. Pin Configurations Symbol Name and FunctionAsserted StateTypeCSChip Select: Asserting t

30AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/20128.2.2 Reading the Security RegisterTo read the Security Register, an opcode of 77h and three dummy

31AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/20129. Additional Commands9.1 Main Memory Page to Buffer TransferA page of data can be transferred fro

32AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012program the data from the buffer back into same page of main memory. The operation is internally s

33AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Table 9-2. Status Register Format – Byte 2Note: 1. R = Readable only9.4.1 RDY/BUSY BitThe RDY/BUSY

34AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/20129.4.6 EPE Bit The EPE bit indicates whether the last erase or program operation completed successf

35AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Figure 9-1. Configuration Register FormatNote: 1. Only bit seven of the Configuration Register wil

36AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/20129.6 Write Configuration RegisterThe Write Configuration Register commands are used to modify the Q

37AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/20129.6.2 Quad Disable CommandThe Quad Disable command is used to program the QE bit of the non-volati

38AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201210. Deep Power-DownDuring normal operation, the device will be placed in the standby mode to consu

39AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201210.1 Resume from Deep Power-DownIn order to exit the Deep Power-Down mode and resume normal device

4AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012WP (I/O2)Write Protect (I/O2): When the WP pin is asserted, all sectors specified for protection by

40AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201210.2 Ultra-Deep Power-DownThe Ultra-Deep Power-Down mode allows the device to consume far less pow

41AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201210.2.1 Exit Ultra-Deep Power-DownTo exit from the Ultra-Deep Power-Down mode, the CS pin must simp

42AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201211. Buffer and Page Size ConfigurationThe memory array of DataFlash devices is actually larger tha

43AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201212. Manufacturer and Device ID ReadIdentification information can be read from the device to enabl

44AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Figure 12-1. Read Manufacturer and Device IDTable 12-3. EDI DataByte Number Bit 7 Bit 6 Bit 5 Bit

45AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201213. Software ResetIn some applications, it may be necessary to prematurely terminate a program or

46AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201214. Operation Mode SummaryThe commands described previously can be grouped into four different cat

47AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201215. Command TablesTable 15-1. Read CommandsTable 15-2. Program and Erase CommandsCommand OpcodeMai

48AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Table 15-3. Protection and Security CommandsTable 15-4. Additional CommandsCommand OpcodeEnable Se

49AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Table 15-5. Detailed Bit-level Addressing Sequence for Binary Page Size (512 bytes)Note: X = Dummy

5AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/20122. Block DiagramFigure 2-1. Block DiagramFlash Memory ArrayI/O InterfaceSCKCSRESET VCCGNDW

50AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Table 15-6. Detailed Bit-level Addressing Sequence for Standard DataFlash Page Size (528 bytes)Not

51AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201216. Power-On/Reset StateWhen power is first applied to the device, or when recovering from a reset

52AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201217. System ConsiderationsThe serial interface is controlled by the Serial Clock (SCK), Serial Inpu

53AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201218. Electrical Specifications18.1 Absolute Maximum Ratings*18.2 DC and AC Operating RangeTemperatu

54AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201218.3 DC Characteristics Notes: 1. Typical values measured at 3.0V at 25C.2. ICC2 during a Buffer

55AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201218.4 AC CharacteristicsNote: 1. Values are based on device characterization, not 100% tested in pr

56AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201218.5 Program and Erase CharacteristicsNotes: 1. Values are based on device characterization, not 1

57AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201221. Utilizing the RapidS FunctionTo take advantage of the RapidS function's ability to operat

58AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Figure 21-2. Command Sequence for Read/Write Operations for Page Size 512 bytes (Except Status Reg

59AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201222. AC WaveformsFour different timing waveforms are shown in <blue>Figure 22-1 through <b

6AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/20123. Memory ArrayTo provide optimal flexibility, the AT45DQ161 memory array is divided into three lev

60AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Figure 22-3. Waveform 3 = RapidS Mode 0Figure 22-4. Waveform 4 = RapidS Mode 3CSSCKSISOtCSSValid I

61AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201223. Write OperationsThe following block diagram and waveforms illustrate the various write sequenc

62AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Figure 23-4. Quad-input Buffer WriteFigure 23-5. Buffer to Main Memory Page ProgramI/O0(SI)SCKI/O1

63AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201224. Read OperationsThe following block diagram and waveforms illustrate the various read sequences

64AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Figure 24-3. Main Memory Page to Buffer TransferData From the selected Flash Page is read into eit

65AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201225. Detailed Bit-level Read Waveforms: RapidS Mode 0/Mode 3Figure 25-1. Continuous Array Read (Leg

66AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Figure 25-4. Main Memory Page Read (Opcode D2h)Figure 25-5. Dual-output Read Array (Opcode 3Bh)SCK

67AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Figure 25-6. Quad-output Read Array (Opcode 6Bh)Figure 25-7. Buffer Read (Opcode D4h or D6h)SCKCS

68AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Figure 25-8. Buffer Read – Low Frequency (Opcode D1h or D3h)Figure 25-9. Read Sector Protection Re

69AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Figure 25-11.Read Security Register (Opcode 77h)Figure 25-12. Status Register Read (Opcode D7h)Fig

7AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/20124. Device OperationThe device operation is controlled by instructions from the host processor. The

70AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Figure 25-14.Reset TimingNote: 1. The CS signal should be in the high state before the RESET signa

71AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201226. Auto Page Rewrite FlowchartFigure 26-1. Algorithm for Programming or Re-programming of the Ent

72AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/2012Figure 26-2. Algorithm for Programming or Re-programming of the Entire Array RandomlyNotes: 1. To

73AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201227. Ordering Information27.1 Ordering DetailDevice GradeH = Green, NiPdAu lead finish, Indust

74AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201227.2 Ordering CodesNotes: 1. The shipping carrier suffix is not marked on the device.2. Not recomm

75AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201227.3 Ordering Codes (Binary Page Mode)Notes: 1. The shipping carrier suffix is not marked on the d

76AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201228. Packaging Information28.1 8S1 – 8-lead JEDEC SOICDRAWING NO. REV. TITLE GPCCOMMON DIMENSIONS(

77AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201228.2 8S2 – 8-lead EIAJ SOICTITLEDRAWING NO. GPCREV.Package Drawing Contact:[email protected]

78AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201228.3 8MA1 – 8-pad UDFNTITLEDRAWING NO.GPCREV.Package Drawing Contact:[email protected] YF

79AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201228.4 9CC1 – 9-ball UBGADRAWING NO. REV. GPCTITLEPackage Drawing Contact:[email protected]

8AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/20125. Read CommandsBy specifying the appropriate opcode, data can be read from the main memory or from

80AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/201229. Revision HistoryDoc. Rev. Date Comments8790A 11/2012 Initial document release.

Corporate OfficeCalifornia | USAAdesto Headquarters1250 Borregas AvenueSunnyvale, CA 94089 Phone: (+1) 408.400.0578Email: [email protected]© 2012

9AT45DQ161 [ADVANCE DATASHEET]8790A–DFLASH–11/20125.3 Continuous Array Read (High Frequency Mode: 0Bh Opcode)This command can be used to read the mai