Rainbow-electronics W49F020 User Manual

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Preliminary W49F020
256K
×
8 CMOS FLASH MEMORY
Publication Release Date: October 1999
- 1 - Revision A1
GENERAL DESCRIPTION
The W49F020 is a 2-megabit, 5-volt only CMOS flash memory organized as 256K × 8 bits. The device
can be programmed and erased in-system with a standard 5V power supply. A 12-volt V
PP is not
required. The unique cell architecture of the W49F020 results in fast program/erase operations with
extremely low current consumption (compared to other comparable 5-volt flash memory products). The
device can also be programmed and erased using standard EPROM programmers.
FEATURES
Single 5-volt operations:
5-volt Read
5-volt Erase
5-volt Program
Fast Program operation:
Byte-by-Byte programming: 50 µS (max.)
Fast Erase operation: 100 mS (typ.)
Fast Read access time: 70/90 nS
Endurance: 1K/10K cycles (typ.)
Twenty-year data retention
Hardware data protection
One 8K byte Boot Block with Lockout
protection
Low power consumption
Active current: 25 mA (typ.)
Standby current: 20 µA (typ.)
Automatic program and erase timing with
internal V
PP generation
End of program or erase detection
Toggle bit
Data polling
Latched address and data
TTL compatible I/O
JEDEC standard byte-wide pinouts
Available packages: 32-pin DIP and 32-pin
TSOP and 32-pin-PLCC
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Summary of Contents

Page 1 - 8 CMOS FLASH MEMORY

Preliminary W49F020 256K × 8 CMOS FLASH MEMORY Publication Release Date: October 1999 - 1 - Revision A1 GENERAL DESCRIPTION The W49F020 is a 2-m

Page 2

Preliminary W49F020 - 10 - DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT Power Supply Voltage to Vss Potential -0.5 to +7.0 V

Page 3

Preliminary W49F020 Publication Release Date: October 1999 - 11 - Revision A1 Power-up Timing PARAMETER SYMBOL TYPICAL UNIT Power-up to Rea

Page 4

Preliminary W49F020 - 12 - AC Characteristics, continued Read Cycle Timing Parameters (VCC = 5.0V ±10%, VCC = 0V, TA = 0 to 70° C) PARAMETER SYM.

Page 5

Preliminary W49F020 Publication Release Date: October 1999 - 13 - Revision A1 AC Characteristics, continued Data Polling and Toggle Bit Timi

Page 6

Preliminary W49F020 - 14 - Timing Waveforms, continued WE Controlled Command Write Cycle Timing Diagram Address A17-0DQ7-0Data ValidCEOEWETASTCSTO

Page 7

Preliminary W49F020 Publication Release Date: October 1999 - 15 - Revision A1 Timing Waveforms, continued Program Cycle Timing Diagram Addr

Page 8

Preliminary W49F020 - 16 - Timing Waveforms, continued Toggle Bit Timing Diagram Address A17-0DQ6 CEOEWETOEHTOESTBP orTEC Boot Block Lockout Enabl

Page 9

Preliminary W49F020 Publication Release Date: October 1999 - 17 - Revision A1 Timing Waveforms, continued Chip Erase Timing Diagram SB2SB1 S

Page 10

Preliminary W49F020 - 18 - ORDERING INFORMATION PART NO. ACCESS TIME (nS) POWER SUPPLY CURRENT MAX. (mA) STANDBY VDD CURRENT MAX. (µA) PACK

Page 11

Preliminary W49F020 Publication Release Date: October 1999 - 19 - Revision A1 PACKAGE DIMENSIONS 32-pin P-DIP 1.Dimensions D Max. & S in

Page 12

Preliminary W49F020 - 2 - PIN CONFIGURATIONS 1234567891011121314151632313029282726252423222120191817DQ0DQ1DQ2GNDA7A6A5A4A3A2A1A0A16A15A12VWEA14A13A

Page 13

Preliminary W49F020 - 20 - Package Dimensions, continued 32-pin TSOP AAA21LL1YcEHDDbeM0.10(0.004)θMin. Nom.Max.Min. Nom.Max.SymbolAAbcDEeLLY112AHD

Page 14

Preliminary W49F020 Publication Release Date: October 1999 - 21 - Revision A1 VERSION HISTORY VERSION DATE PAGE DESCRIPTION A1 Oct. 1999

Page 15

Preliminary W49F020 Publication Release Date: October 1999 - 3 - Revision A1 FUNCTIONAL DESCRIPTION Read Mode The read operation of the W49F02

Page 16

Preliminary W49F020 - 4 - TBP) when completing programming and return to normal read mode. Data polling and/or Toggle Bits can be used to detect en

Page 17

Preliminary W49F020 Publication Release Date: October 1999 - 5 - Revision A1 TABLE OF OPERATING MODES Operating Mode Selection (VHH = 12V ±

Page 18

Preliminary W49F020 - 6 - Command Codes for Byte Program WORD SEQUENCE ADDRESS DATA 0 Write 5555H AAH 1 Write 2AAAH 55H 2 Write 5555H A0H 3 W

Page 19

Preliminary W49F020 Publication Release Date: October 1999 - 7 - Revision A1 Command Codes for Chip Erase BYTE SEQUENCE ADDRESS DATA 1 Wr

Page 20

Preliminary W49F020 - 8 - Command Codes for Product Identification and Boot Block Lockout Detection BYTE SEQUENCE ALTERNATE PRODUCT (6) IDENTIFICAT

Page 21

Preliminary W49F020 Publication Release Date: October 1999 - 9 - Revision A1 Command Codes for Boot Block Lockout Enable BYTE SEQUENCE BOOT

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