Preliminary W24L257 32K × 8 CMOS STATIC RAM Publication Release Date: May 2000 - 1 - Revision A1 GENERAL DESCRIPTION The W24L257 is a normal-spe
Preliminary W24L257 - 10 - VERSION HISTORY VERSION DATE PAGE DESCRIPTION A1 May 2000 - Initial Issued HeadquartersNo. 4, C
Preliminary W24L257 - 2 - TRUTH TABLE CS OE WE MODE I/O1−I/O8 VDD CURRENT H X X Not Selected High Z ISB, ISB1 L H H Output Disable High Z IDD
Preliminary W24L257 Publication Release Date: May 2000 - 3 - Revision A1 Operating Characteristics, continued PARAMETER SYM. TEST CONDITIONS MI
Preliminary W24L257 - 4 - AC Characteristics, continued (VDD = 3.0V to 3.6 V; VSS = 0V; TA (°C) = 0 to 70 for LL, -20 to 85 for LE) Read Cycle PARAME
Preliminary W24L257 Publication Release Date: May 2000 - 5 - Revision A1 TIMING WAVEFORMS Read Cycle 1 (Address Controlled) AddressTRCTAATOHTOHD
Preliminary W24L257 - 6 - Timing Waveforms, continued Write Cycle 1 AddressOETWCTWRWEDOUTDINTWPTASTOHZ(1, 4)TDWTDHTAWCSTCW Write Cycle 2 (OE = VIL Fi
Preliminary W24L257 Publication Release Date: May 2000 - 7 - Revision A1 DATA RETENTION CHARACTERISTICS (TA (°C) = 0 to 70 for LL, -20 to 85 for
Preliminary W24L257 - 8 - BONDING PAD DIAGRAM23XYA14A12A7A6A5A3822A2A10OEBA11A9A8WEBVDDVDD7A4A131234529242526276302811 121315 16 17 18A0I/O0 I/O1I/O2
Preliminary W24L257 Publication Release Date: May 2000 - 9 - Revision A1 PACKAGE DIMENSIONS 28-pin SOP Wide Body 21A2815141eSEHbSeating PlaneAAy
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