W9825G6CH 4M ×× 4 BANKS ×× 16 BIT SDRAM Publication Release Date: Oct 2004 - 1 - Revision A2 GENERAL DESCRIPTION W9825G6CH is a high-speed synchro
W9825G6CH - 10 - OPERATION MODE Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the trut
W9825G6CH Publication Release Date: Oct. 2004 - 11 - Revision A2 FUNCTIONAL DESCRIPTION Power Up and Initialization The default power up state of
W9825G6CH - 12 - Burst Read Command The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at th
W9825G6CH Publication Release Date: Oct. 2004 - 13 - Revision A2 Addressing Sequence of Sequential Mode A column access is performed by increasing
W9825G6CH - 14 - Auto-precharge Command If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered.
W9825G6CH Publication Release Date: Oct. 2004 - 15 - Revision A2 The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Oper
W9825G6CH - 16 - TIMING WAVEFORMS Command Input Timing CLKA0-A12BS0, 1VIHVILtCMH tCMStCHtCLtT tTtCKStCKHtCKHtCKStCKStCKHCommand Input TimingCSRASCASW
W9825G6CH Publication Release Date: Oct. 2004 - 17 - Revision A2 Timing Waveforms, continued Read Timing Read CAS LatencytACtLZtACtOHtHZtOHBurst L
W9825G6CH - 18 - Timing Waveforms, continued Control Timing of Input/Output Data tCMHtCMStCMHtCMStDStDHtDStDHtDStDHtDStDHValidData-OutValidData-OutVa
W9825G6CH Publication Release Date: Oct. 2004 - 19 - Revision A2 Timing Waveforms, continued Mode Register Set Cycle A0A1A2A3A4A5A6Burst LengthAdd
W9825G6CH - 2 - PIN CONFIGURATION VSSDQ15VSSQDQ14DQ13VCCQDQ12DQ11VSSQDQ10DQ9VCCQDQ8VSSNCUDQMCLKCKEA12A11A9A8A7A6A5A4VSS545352515049484746454443424140
W9825G6CH - 20 - OPERATING TIMING EXAMPLE Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) 01 2 3 4 56 7 8 9 10 11 12 13 14 15 16 17 18 19 2
W9825G6CH Publication Release Date: Oct. 2004 - 21 - Revision A2 Operating Timing Example, continued Interleaved Bank Read (Burst Length = 4, CAS
W9825G6CH - 22 - Operating Timing Example, continued Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) 01 2 3 4 56 7 8 9 10 11 12 13 14 15 16
W9825G6CH Publication Release Date: Oct. 2004 - 23 - Revision A2 Operating Timing Example, continued Interleaved Bank Read (Burst Length = 8, CAS
W9825G6CH - 24 - Operating Timing Example, continued Interleaved Bank Write (Burst Length = 8) 01 2 3 4 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
W9825G6CH Publication Release Date: Oct. 2004 - 25 - Revision A2 Operating Timing Example, continued Interleaved Bank Write (Burst Length = 8, Aut
W9825G6CH - 26 - Operating Timing Example, continued Page Mode Read (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1
W9825G6CH Publication Release Date: Oct. 2004 - 27 - Revision A2 Operating Timing Example, continued Page Mode Read/Write (Burst Length = 8, CAS L
W9825G6CH - 28 - Operating Timing Example, continued Auto Precharge Read (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
W9825G6CH Publication Release Date: Oct. 2004 - 29 - Revision A2 Operating Timing Example, continued Auto Precharge Write (Burst Length = 4) 0 1 2
W9825G6CH Publication Release Date: Oct. 2004 - 3 - Revision A2 PIN DESCRIPTION PIN NO. PIN NAME FUNCTION DESCRIPTION 23−26, 22, 29−36 A0−A12 Ad
W9825G6CH - 30 - Operating Timing Example, continued Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23(CLK = 100 MHz)A
W9825G6CH Publication Release Date: Oct. 2004 - 31 - Revision A2 Operating Timing Example, continued Self Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11
W9825G6CH - 32 - Operating Timing Example, continued Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13
W9825G6CH Publication Release Date: Oct. 2004 - 33 - Revision A2 Operating Timing Example, continued PowerDown Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 1
W9825G6CH - 34 - Operating Timing Example, continued Autoprecharge Timing (Read Cycle) Read AP0 1110987654321Q0Q0Read AP ActQ1Read AP ActQ1 Q2AP ActR
W9825G6CH Publication Release Date: Oct. 2004 - 35 - Revision A2 Operating Timing Example, continued Autoprecharge Timing (Write Cycle) Act0 1 32(
W9825G6CH - 36 - Operating Timing Example, continued Timing Chart of Read to Write Cycle Note: The Output data must be masked by DQM to avoid I/O con
W9825G6CH Publication Release Date: Oct. 2004 - 37 - Revision A2 Timing Chart of Burst Stop Cycle (Burst Stop Command) Read BST0 1110987654321DQQ0
W9825G6CH - 38 - 0 1 111098765432(1) Read cycle(a) CAS latency =2 CommandQ0 Q1 Q2 Q3 Q4PRCGRead(b) CAS latency =3
W9825G6CH Publication Release Date: Oct. 2004 - 39 - Revision A2 Operating Timing Example, continued CKE/DQM Input Timing (Write Cycle) 7654321CKE
W9825G6CH - 4 - BLOCK DIAGRAM DQ0DQ15LDQMUDQMCLKCKECSRASCASWEA10A0A9A11A12BS0BS1CLOCKBUFFERCOMMANDDECODERADDRESSBUFFERREFRESHCOUNTERCOLUMNCOUNTERCONT
W9825G6CH - 40 - Operating Timing Example, continued CKE/DQM Input Timing (Read Cycle) 7654321( 1 )Q1Q6Q4Q3Q2CLK cycle No.ExternalInternalCKEDQMDQOpe
W9825G6CH Publication Release Date: Oct. 2004 - 41 - Revision A2 Operating Timing Example, continued Self Refresh/Power Down Mode Exit Timing Asyn
W9825G6CH - 42 - PACKAGE DIMENSION 54L TSOP (II)-400 mil SEATING PLANEEDA2A1AebZD1 2754 28HEYLCL1ZD0.71 0.0280.0020.009MAX.MIN. NOM.A2bAA10.241.000.0
W9825G6CH Publication Release Date: Oct. 2004 - 43 - Revision A2 11. REVERSION HISTORY REVERSION DATE PAGE DESCRIPTION March, 2003 - Preliminar
W9825G6CH Publication Release Date: Oct. 2004 - 5 - Revision A2 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTES Input, Output Volt
W9825G6CH - 6 - AC CHARACTERISTICS AND OPERATING CONDITION (Vcc = 3.3V ± 0.3V, Ta = 0 to 70°C for –6/-7/-75/75L, Ta=-40 to 85°C for 75I ; Notes: 5, 6
W9825G6CH Publication Release Date: Oct. 2004 - 7 - Revision A2 PARAMETER SYM. -6 UNIT MIN. MAX. Ref/Active to Ref/Active Command Period
W9825G6CH - 8 - DC CHARACTERISTICS (VCC = 3.3V ± 0.3V, Ta = 0 to 70°C for –6/-7/-75/75L, Ta=-40 to 85°C for 75I) PARAMETER SYM. -6 -7 -75/75L/7
W9825G6CH Publication Release Date: Oct. 2004 - 9 - Revision A2 Notes: 1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanen
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