Rainbow-electronics AT86RF211 User Manual

1Features• Multiband Transceiver: 400 MHz to 950 MHz• Monochip RF Solution: Transmitter-Receiver-Synthesizer• Integrated PLL and VCO: No External Coil

10AT86RF2111942C–WIRE–06/02Overview and Choice ofIntermediate FrequenciesFor selectivity and flexibility purpose, a classical and robust 2 IF superhet

11AT86RF2111942C–WIRE–06/02Figure 10. TEM FilterSuch a filter also provides an out-of-band interference rejection greater than 20dB,40MHzawayfrom433MH

12AT86RF2111942C–WIRE–06/02Figure 11. Schematic Input of the LNAFigure 12. Schematic Output of the MixerThe first mixer translates the input RF signal

13AT86RF2111942C–WIRE–06/02Figure 13. IF1 FilteringFigure 14. Schematic Input of IF1 AmplifierFigure 15. Schematic Output of the Second MixerIF2 Filte

14AT86RF2111942C–WIRE–06/02Figure 16. LC Band-pass Filter• 10 nF capacitors cut DC response forward and backward.• The first network has the low cut-o

15AT86RF2111942C–WIRE–06/02RSSI Output The RSSI value can be read as a 6 bits word in the STATUS register. Its value is linearin dB as plotted below:F

16AT86RF2111942C–WIRE–06/02Figure 19. ADC Converter Input SelectionNote: For voltage measurement, the LSB weighs 85 mV and the reference voltage is 1.

17AT86RF2111942C–WIRE–06/02The input RBW resistor controls the discriminator bandwidth. This bandwidth is selectedby CTRL1[6]. The default value is &q

18AT86RF2111942C–WIRE–06/02To operate this way, the user must make sure that the "0" and "1" level at the output ofthe discriminat

19AT86RF2111942C–WIRE–06/02Transmitter DescriptionFigure 23. Typical Expected Currents in Tx ModeSupply Current - Tx Mode15.0020.0025.0030.0035.0040.0

2AT86RF2111942C–WIRE–06/02General OverviewGeneral Overview ofFunctioningThe AT86RF211 is a microcontroller RF peripheral: all the user has to do is to

20AT86RF2111942C–WIRE–06/02Power Amplification The Power Amplifier has been built to deliver more than +10 dBm, i.e. 10 mW in thethree popular frequen

21AT86RF2111942C–WIRE–06/02An automatic level control loop (ALC) is integrated, in order to minimize the sensitivity ofthe PA to the temperature, proc

22AT86RF2111942C–WIRE–06/02Figure 28. RPOWERInput SchematicNote: Keeping the PA output matched guarantees maximum power efficiency.Software Control Th

23AT86RF2111942C–WIRE–06/02• Register Interface FormatA message is made of 3 fields:– address A[3:0]: 4 bits (MSB first)– R/W: read/write selection– d

24AT86RF2111942C–WIRE–06/02Only the 2 MSBs are updated on the rising edge of SLE; other register bits areunchanged.•READ Mode (R/W = 0)The address and

25AT86RF2111942C–WIRE–06/02Figure 33. Chronogram with TimingNote: For the timing specification, please refer to the timing table “Digital CMOS DC Char

26AT86RF2111942C–WIRE–06/02Reset Register (RESET)Writing in this register (0 or 1) triggers an asynchronous reset. This register can only bewritten.Al

27AT86RF2111942C–WIRE–06/02Table 6. CTRL1 Detailed Description(1)(2)(4)(3)NameNumberof Bits CommentsPDN 1 General power-down0: power down mode; only t

28AT86RF2111942C–WIRE–06/02Notes: 1. The same ADC is used to measure RSSI or VCCvoltage. When the VCCvoltage is measured, the RSSI measurement isstopp

29AT86RF2111942C–WIRE–06/02Control Register (CTRL2)Register reset value = (00000057)16• Clock Recovery FunctionThe clock recovery function is activate

3AT86RF2111942C–WIRE–06/02Figure 1. Reception and Transmit ModeF = Frequency oftransmitted signalAT86RF211 acts like a "pipe"(data is transm

30AT86RF2111942C–WIRE–06/02If the tolerance is too high, the rate value is reached earlier, and the rate value could beunstable (too big step).If the

31AT86RF2111942C–WIRE–06/02• Datatol ProgrammingThe tolerance for the extraction of DATA rate must be nearly 2% of the RATE. The toler-ance represents

32AT86RF2111942C–WIRE–06/02Frequency RegistersNote: 1. F0, F1, F2 and F3 registers must be programmed before using the device.• Frequency Registers Se

33AT86RF2111942C–WIRE–06/02In reception mode, only one frequency needs to be programmed. In transmission mode,two different registers (F0 & F1), o

34AT86RF2111942C–WIRE–06/02DTR Register The DTR register allows the user to precisely adjust the offset of the data slicer input.Register reset value

35AT86RF2111942C–WIRE–06/02Wake-up Control RegisterRegister reset value = (7f8be110)16Table 13. DTR Detailed DescriptionNameNumberof bits CommentsDSOF

36AT86RF2111942C–WIRE–06/02• WPER ProgrammingWPER can be set from 10 ms to 328 sec with an accuracy of ±20%. A 10 ms periodclock is used for this peri

37AT86RF2111942C–WIRE–06/02• WL1 ProgrammingWL1 can be set from 1 ms to 1.024 sec. A 1 ms period clock is used for this delaygeneration.Bit 6 gives a

38AT86RF2111942C–WIRE–06/02• WL2 programmingWL2 can be set as a multiple of WL1 from 0 to 31 WL1.Wake-upDataRateRegister(WUR)Table 18. WL2 Programming

39AT86RF2111942C–WIRE–06/02The data rate (in bps) and the decimal value to be coded in the register are related bythe equation:The following table giv

4AT86RF2111942C–WIRE–06/02Figure 2. Wake-up OverviewFigure 3. Periodical ScanHeader + AddressStep 3: If a correct header is received (mandatory)and ad

40AT86RF2111942C–WIRE–06/02Wake-upDataRegister(WUD)Note: To use this mode, please refer to the corresponding application note.Table 23. WUD OverviewNa

41AT86RF2111942C–WIRE–06/02ElectricalSpecificationESD sensitive device: storage or handling of the device must be carried outaccording to usual protec

42AT86RF2111942C–WIRE–06/02Digital CMOS DCCharacteristicsUnless otherwise specified, data is given for T = 25°C, VSUPPLY=2.7VNote: 1. For digital CMOS

43AT86RF2111942C–WIRE–06/02SynthesizerSpecificationUnless otherwise specified, data is given for T = 25°C, VSUPPLY=2.7ViiNotes: 1. Crystal frequency c

44AT86RF2111942C–WIRE–06/02Transmitter Specification Unless otherwise specified, data is given for T = 25°C, VSUPPLY=2.7V,RPOWER=18kΩ.Notes: 1. Output

45AT86RF2111942C–WIRE–06/02Typical ApplicationImplementationNote: Accurate information about parts and values of components to be used around AT86RF21

46AT86RF2111942C–WIRE–06/02LayoutReference Design Top LayerReference Design BottomLayerEach unused area must be filledwith copper and connected to the

47AT86RF2111942C–WIRE–06/02PackagingInformation48 lead TQFPOrdering informationDimension Nominal Value (mm) Tolerance Dimension Nominal Value (inch) T

Printed on recycled paper.© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than those expressly contain

5AT86RF2111942C–WIRE–06/02Block DiagramFigure 4. AT86RF211 Block DiagramSYNTHESIZERFREQUENCYCTRLCONTROL LOGICWAKE-UPDATA SLICERBANDWIDTH CTRLRSSI LEVE

6AT86RF2111942C–WIRE–06/02Pin DescriptionNotes: 1. All VCCpins must be connected in each functional mode (Tx, Rx, wake-up, PDN)2. To be connected:Rxmo

7AT86RF2111942C–WIRE–06/02Detailed DescriptionFrequency SynthesisCrystal Reference Oscillator The reference clock is based on a classical Colpitts arc

8AT86RF2111942C–WIRE–06/02Figure 7. Synthesizer Loop Filter SchematicNote: The PLL loop filter can be designed to optimize the phase noise around the

9AT86RF2111942C–WIRE–06/02Receiver DescriptionFigure 8. Typical Expected Currents in Rx ModeSupply Current - Rx Mode26.0028.0030.0032.002.25 2.50 2.75