Rainbow-electronics AT89C5132 User Manual

Rev. 4173A–8051–08/02Features• Programmable Audio Output for Interfacing with Common Audio DAC – PCM Format Compatible–I2S Format Compatible• 8-bit MC

10AT8xC51324173A–8051–08/02Table 13. System Signal DescriptionSignal Name Type DescriptionAlternate FunctionRST IReset InputHolding this pin high fo

100AT8xC51324173A–8051–08/02Table 97. MMSTA RegisterMMSTA (S:DEh Read Only) – MMC Control and Status RegisterReset Value = 0000 0000b76543210- - CBUS

101AT8xC51324173A–8051–08/02Table 98. MMINT RegisterMMINT (S:E7h Read Only) – MMC Interrupt RegisterReset Value = 0000 0011b76543210MCBI EORI EOCI EO

102AT8xC51324173A–8051–08/02Table 99. MMMSK Register MMMSK (S:DFh) – MMC Interrupt Mask RegisterReset Value = 1111 1111bTable 100. MMCMD RegisterMMC

103AT8xC51324173A–8051–08/02Table 101. MMDAT Register MMDAT (S:DCh) – MMC Data RegisterReset Value = 1111 1111bTable 102. MMCLK RegisterMMCLK (S:EDh

104AT8xC51324173A–8051–08/02IDE/ATAPI Interface The AT8xC5132 provide an IDE/ATAPI interface allowing connection of devices such asCD-ROM reader, Comp

105AT8xC51324173A–8051–08/02Figure 73. IDE Write WaveformsNotes: 1. WR signal may be stretched using M0 bit in AUXR register.2. When executing MOVX @

106AT8xC51324173A–8051–08/02Table 103. External Data Memory Interface SignalsRegisters Table 104. DAT16H RegisterDAT16H (S:F9h) – Data 16 High Order

107AT8xC51324173A–8051–08/02Serial I/O Port The serial I/O port in the AT8xC5132 provides both synchronous and asynchronouscommunication modes. It ope

108AT8xC51324173A–8051–08/02Internal Baud Rate Generator When using the Internal Baud Rate Generator, the Baud Rate is derived from the over-flow of t

109AT8xC51324173A–8051–08/02Figure 79. Transmission Waveforms (Mode 0)Reception (Mode 0) To start a reception in mode 0, write to SCON register clear

11AT8xC51324173A–8051–08/02Internal Pin StructureNotes: 1. For information on resistors value, input/output levels, and drive capability, refer to the

110AT8xC51324173A–8051–08/02Asynchronous Modes (Modes 1, 2 and 3)The Serial Port has one 8-bit and two 9-bit asynchronous modes of operation. Figure 8

111AT8xC51324173A–8051–08/02Framing Error Detection (Modes 1, 2 and 3)Framing error detection is provided for the three asynchronous modes. To enable

112AT8xC51324173A–8051–08/02Notes: 1. These frequencies are achieved in X1 mode, FPER = FOSC ÷ 2.2. These frequencies are achieved in X2 mode, FPER =

113AT8xC51324173A–8051–08/02Multiprocessor Communication (Modes 2 and 3)Modes 2 and 3 provide a ninth-bit mode to facilitate multiprocessor communicat

114AT8xC51324173A–8051–08/02The SADEN byte is selected so that each slave may be addressed separately.For slave A, bit 0 (the LSB) is a don’t care bit

115AT8xC51324173A–8051–08/02Interrupt The Serial I/O Port handles two interrupt sources that are the “end of reception” (RI inSCON) and “end of transm

116AT8xC51324173A–8051–08/02Registers Table 107. SCON RegisterSCON (S:98h) – Serial Control Register Reset Value = 0000 0000b76543210FE/SM0 OVR/SM1 S

117AT8xC51324173A–8051–08/02Table 108. SBUF RegisterSBUF (S:99h) – Serial Buffer RegisterReset value = XXXX XXXXbTable 109. SADDR RegisterSADDR (S:A

118AT8xC51324173A–8051–08/02Table 111. BDRCON RegisterBDRCON (S:92h) – Baud Rate Generator Control RegisterReset Value = XXX0 0000bTable 112. BRL Re

119AT8xC51324173A–8051–08/02Synchronous Peripheral InterfaceThe AT8xC5132 implement a Synchronous Peripheral Interface with master and slavemodes capa

12AT8xC51324173A–8051–08/02Clock Controller The AT8xC5132 clock controller is based on an on-chip oscillator feeding an on-chipPhase Lock Loop (PLL).

120AT8xC51324173A–8051–08/02Description The SPI controller interfaces with the C51 core through three special function registers:SPCON, the SPI contro

121AT8xC51324173A–8051–08/02Figure 96. SPI Slave Mode Block DiagramNote: MSTR bit in SPCON is cleared to select slave mode.Bit Rate The bit rate can

122AT8xC51324173A–8051–08/02Figure 97. Data Transmission Format (CPHA = 0)Figure 98. Data Transmission Format (CPHA = 1)SS Management Figure 97 show

123AT8xC51324173A–8051–08/02Figure 99. SS# Timing DiagramError Conditions The following flags signal the SPI error conditions:• MODF in SPSTA signals

124AT8xC51324173A–8051–08/02Configuration The SPI configuration is made through SPCON.Master Configuration The SPI operates in master mode when the MS

125AT8xC51324173A–8051–08/02Master Mode with Interrupt PolicyFigure 102 shows the initialization phase and the transfer phase flows using the inter-ru

126AT8xC51324173A–8051–08/02Slave Mode with Polling PolicyFigure 103 shows the initialization phase and the transfer phase flows using the pollingpoli

127AT8xC51324173A–8051–08/02Slave Mode with Interrupt PolicyFigure 102 shows the initialization phase and the transfer phase flows using the inter-rup

128AT8xC51324173A–8051–08/02Reset Value = 0001 0100bNote: 1. When the SPI is disabled, SCK outputs high level.Table 115. SPSTA Register SPSTA (S:C4h)

129AT8xC51324173A–8051–08/02Analog-to-Digital ConverterThe AT8xC5132 implement a 2-channel 10-bit (8 true Bits) analog-to-digital converter(ADC). The

13AT8xC51324173A–8051–08/02Figure 7. Mode Switching WaveformsNote: In order to prevent any incorrect operation while operating in X2 mode, the user m

130AT8xC51324173A–8051–08/02Clock Generation The ADC clock is generated by division of the peripheral clock (see details inSection “X2 Feature”, page

131AT8xC51324173A–8051–08/02Figure 108. ADC Configuration FlowConversion Launching The conversion is launched by setting the ADSST bit in ADCON regis

132AT8xC51324173A–8051–08/02Registers Table 118. ADCON RegisterADCON (S:F3h) – ADC Control RegisterReset Value = 0000 0000bTable 119. ADCLK Register

133AT8xC51324173A–8051–08/02Table 120. ADDH RegisterADDH (S:F5h Read Only) – ADC Data High Byte RegisterReset Value = 0000 0000bTable 121. ADDL Regi

134AT8xC51324173A–8051–08/02Keyboard Interface The AT8xC5132 implement a keyboard interface allowing the connection of a 4 x nmatrix keyboard. It is b

135AT8xC51324173A–8051–08/02Registers Table 122. KBCON RegisterKBCON (S:A3h) – Keyboard Control RegisterReset Value = 0000 1111bTable 123. KBSTA Reg

136AT8xC51324173A–8051–08/02Electrical CharacteristicsAbsolute Maximum RatingsDC CharacteristicsDigital LogicStorage Temperature...

137AT8xC51324173A–8051–08/02Note: 1. Typical values are obtained using VDD = 3V and TA = 25°C. They are not tested andthere is no guarantee on these v

138AT8xC51324173A–8051–08/02IDD, IDL and IPD Test Conditions Figure 113. IDD Test Condition, Active ModeFigure 114. IDL Test Condition, Idle ModeFig

139AT8xC51324173A–8051–08/02A-to-D Converter Table 125. A-to-D Converter DC Characteristics VDD = 2.7 to 3.3V , TA = -40°C to+85°COscillator and Crys

14AT8xC51324173A–8051–08/02Figure 9. PLL Filter ConnectionPLL Programming The PLL is programmed using the flow shown in Figure 10. As soon as clock g

140AT8xC51324173A–8051–08/02Phase Lock LoopSchematic Figure 117. PLL Filter ConnectionParameters Table 127. PLL Filter CharacteristicsVDD = 2.7 to 3

141AT8xC51324173A–8051–08/02AC CharacteristicsExternal 8-bit Bus CyclesDefinition of Symbols Table 129. External 8-bit Bus Cycles Timing Symbol Defin

142AT8xC51324173A–8051–08/02Table 131. External 8-bit Bus Cycle – Data Write AC TimingsVDD = 2.7 to 3.3V, TA = -40° to +85°CWaveforms Figure 119. Ex

143AT8xC51324173A–8051–08/02Figure 120. External 8-bit Bus Cycle – Data Write WaveformsExternal IDE 16-bit Bus CyclesDefinition of Symbols Table 132.

144AT8xC51324173A–8051–08/02Table 133. External IDE 16-bit Bus Cycle – Data Read AC TimingsVDD = 2.7 to 3.3V, TA = -40° to +85°CTable 134. External

145AT8xC51324173A–8051–08/02Waveforms Figure 121. External IDE 16-bit Bus Cycle – Data Read WaveformsNote: D15:8 is written in DAT16H SFR.Figure 122.

146AT8xC51324173A–8051–08/02Timings Table 136. SPI Interface Master AC TimingVDD = 2.7 to 3.3V, TA = -40° to +85°CNotes: 1. Value of this parameter d

147AT8xC51324173A–8051–08/02WaveformsFigure 123. SPI Slave Waveforms (SSCPHA = 0)Note: Not Defined but generally the MSB of the character that has ju

148AT8xC51324173A–8051–08/02Figure 125. SPI Master Waveforms (SSCPHA = 0)Note: SS handled by software using general purpose port pin.Figure 126. SPI

149AT8xC51324173A–8051–08/02Specific Controller To be defined.MMC InterfaceDefinition of Symbols Table 137. MMC Interface Timing Symbol DefinitionsTi

15AT8xC51324173A–8051–08/02Registers Table 16. CKCON RegisterCKCON (S:8Fh) – Clock Control RegisterReset Value = 0000 000Xb76543210- WDX2 - - - T1X2

150AT8xC51324173A–8051–08/02Audio InterfaceDefinition of Symbols Table 139. Audio Interface Timing Symbol DefinitionsTimings Table 140. Audio Interf

151AT8xC51324173A–8051–08/02Analog to Digital ConverterDefinition of Symbols Table 141. Analog to Digital Converter Timing Symbol DefinitionsCharacte

152AT8xC51324173A–8051–08/02Figure 130. Analog-to-Digital Converter CharacteristicsFlash MemoryDefinition of Symbols Table 143. Flash Memory Timing

153AT8xC51324173A–8051–08/02Waveforms Figure 131. Flash Memory – ISP WaveformsNote: ISP must be driven through a pull-down resistor (see Section “In-

154AT8xC51324173A–8051–08/02Figure 134. AC Testing Input/Output WaveformsNotes: 1. During AC testing, all inputs are driven at VDD -0.5V for a logic

155AT8xC51324173A–8051–08/02Ordering InformationNotes: 1. Refers to ROM code. Check for availability.2. PLCC84 package only available for development

156AT8xC51324173A–8051–08/02Package InformationTQFP80

157AT8xC51324173A–8051–08/02PLCC84

158AT8xC51324173A–8051–08/02TQFP64

159 AT8xC51324173A–8051–08/02Table of ContentsFeatures ...

16AT8xC51324173A–8051–08/02Table 17. PLLCON RegisterPLLCON (S:E9h) – PLL Control RegisterReset Value = 0000 1000bTable 18. PLLNDIV Register PLLNDIV

160 AT8xC51324173A–8051–08/02Power-down Mode... 47Register

161 AT8xC51324173A–8051–08/02Serial I/O Port ... 107Mode Selection..

Printed on recycled paper.Atmel®, is a registered trademark of Atmel. MultiMedia Card® is a registered trademark of MultiMediaCorporation. SmartMedia

17AT8xC51324173A–8051–08/02Table 19. PLLRDIV Register PLLRDIV (S:EFh) – PLL R Divider RegisterReset Value = 0000 0000b76543210R9 R8 R7 R6 R5 R4 R3 R2

18AT8xC51324173A–8051–08/02Program/Code MemoryThe AT89C5132 and AT83C5132 implement 64K Bytes of on-chip program/code mem-ory. Figure 11 shows the spl

19AT8xC51324173A–8051–08/02User Space This space is composed of a 64K Bytes ROM memory programmed during the manu-facturing process. It contains the u

2AT8xC51324173A–8051–08/02Block DiagramFigure 1. AT8xC5132 Block DiagramNotes: 1. Alternate function of Port 32. Alternate function of Port 48-BIT IN

20AT8xC51324173A–8051–08/02Extra Row Space This space is composed of two Bytes:• The Software Boot Vector (SBV see Table 22).This byte is used by the

21AT8xC51324173A–8051–08/02Figure 14. Hardware Boot Process AlgorithmThe software process (bootloader) is detailed in the section “In-System and In-A

22AT8xC51324173A–8051–08/02Registers Table 20. AUXR1 Register AUXR1 (S:A2h) – Auxiliary Register 1Reset Value = XXXX 00X0b76543210- - ENBOOT - GF3 0

23AT8xC51324173A–8051–08/02Hardware Bytes Table 21. HSB Byte – Hardware Security ByteReset Value = XXUU UXXX, UUUU UUUU after an hardware full chip

24AT8xC51324173A–8051–08/02Data Memory The AT8xC5132 provides data memory access in two different spaces:1. The internal space mapped in three separat

25AT8xC51324173A–8051–08/02Figure 16. Lower 128 Bytes Internal RAM OrganizationUpper 128 Bytes RAM The upper 128 Bytes of RAM are accessible from add

26AT8xC51324173A–8051–08/02External SpaceMemory Interface The external memory interface comprises the external bus (port 0 and port 2) as well asthe b

27AT8xC51324173A–8051–08/02External Bus Cycles This section describes the bus cycles that AT8xC5132 execute to read (see Figure 18),and write data (se

28AT8xC51324173A–8051–08/02Dual Data PointerDescription The AT8xC5132 implement a second data pointer for speeding up code execution andreducing code

29AT8xC51324173A–8051–08/02Registers Table 27. PSW Register PSW (S:8Eh) – Program Status Word RegisterReset Value = 0000 0000b76543210CY AC F0 RS1 RS

3AT8xC51324173A–8051–08/02Pin ConfigurationFigure 2. AT8xC5132 80-pin TQFP PackageTQFP80P0.3/AD3P0.4/AD4P0.5/AD5VSSVDDP0.6/AD6P0.7/AD7P2.0/A8P2.1/A9P

30AT8xC51324173A–8051–08/02Table 28. AUXR Register AUXR (S:8Eh) – Auxiliary Control RegisterReset Value = X000 1101bTable 29. AUXR1 Register AUXR1 (

31AT8xC51324173A–8051–08/02Special Function RegistersThe Special Function Registers (SFRs) of the AT8xC5132 derivatives fall into the cate-gories deta

32AT8xC51324173A–8051–08/02Table 34. Port SFRsMnemonicAddName 76543210P0 80h 8-bit Port 0 ––––––––P1 90h 8-bit Port 1 ––––––––P2 A0h 8-bit Port 2 –––

33AT8xC51324173A–8051–08/02Table 38. USB Controller SFRsMnemonic Add Name 7 6 5 4 3 2 1 0USBCON BCh USB Global Control USBE SUSPCLK SDRMWUP–UPRSM RMW

34AT8xC51324173A–8051–08/02Table 41. Serial I/O Port SFRsMnemonicAddName 76543210SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RISBUF 99h Ser

35AT8xC51324173A–8051–08/02ReservedNotes: 1. SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable.2. NVERS reset va

36AT8xC51324173A–8051–08/02Interrupt System The AT8xC5132, like other control-oriented computer architectures, employ a programinterrupt method. This

37AT8xC51324173A–8051–08/02Table 48. Priority LevelsA low-priority interrupt is always interrupted by a higher priority interrupt but not byanother i

38AT8xC51324173A–8051–08/02Figure 21. Interrupt Control SystemEI2CIEN1.1EUSBIEN1.6ESPIIEN1.2EX0IEN0.000011011ExternalInterrupt 0INT0EAIEN0.7EX1IEN0.2

39AT8xC51324173A–8051–08/02External InterruptsINT1:0# Inputs External interrupts INT0 and INT1 (INTn, n = 0 or 1) pins may each be programmed tobe lev

4AT8xC51324173A–8051–08/02Figure 3. AT8xC5132 64-pin TQFP17 18 22212019 252423 26 27 62 61 60 59 58 63 57 56 55 54 5312 3 4 56 78 9 10 114847

40AT8xC51324173A–8051–08/02Registers Table 50. IEN0 Register IEN0 (S:A8h) – Interrupt Enable Register 0Reset Value = 0000 0000b76543210EA EAUD – ES E

41AT8xC51324173A–8051–08/02Table 51. IEN1 RegisterIEN1 (S:B1h) – Interrupt Enable Register 1Reset Value = 0000 0000b76543210-EUSB– EKB EADC ESPI EI2C

42AT8xC51324173A–8051–08/02Table 52. IPH0 Register IPH0 (S:B7h) – Interrupt Priority High Register 0Reset Value = X000 0000b76543210- IPHAUD – IPHS I

43AT8xC51324173A–8051–08/02Table 53. IPH1 Register IPH1 (S:B3h) – Interrupt Priority High Register 1Reset Value = 0000 0000b76543210- IPHUSB – IPHKB

44AT8xC51324173A–8051–08/02Table 54. IPL0 RegisterIPL0 (S:B8h) – Interrupt Priority Low Register 0Reset Value = X000 0000b76543210- IPLAUD – IPLS IPL

45AT8xC51324173A–8051–08/02Table 55. IPL1 Register IPL1 (S:B2h) – Interrupt Priority Low Register 1Reset Value = 0000 0000b76543210- IPLUSB - IPLKB I

46AT8xC51324173A–8051–08/02Power Management Two power reduction modes are implemented in the AT8xC5132: the Idle mode and thePower-down mode. In addit

47AT8xC51324173A–8051–08/02Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode,program execution halts. Idl

48AT8xC51324173A–8051–08/02Exiting Power-down Mode If VDD was reduced during the Power-down mode, do not exit Power-down mode untilVDD is restored to

49AT8xC51324173A–8051–08/02reset algorithm takes control. Reset initializes the AT8xC5132 and vectors the CPU to address 0000h.Notes: 1. During the ti

5AT8xC51324173A–8051–08/02Figure 4. AT8xC5132 84-pin PLCC Package(1)Note: 1. For development board only.PLCC84P0.3/AD3P0.4/AD4P0.5/AD5VSSVDDP0.6/AD6P

50AT8xC51324173A–8051–08/02Timers/Counters The AT8xC5132 implement two general-purpose, 16-bit Timers/Counters. They areidentified as Timer 0 and Time

51AT8xC51324173A–8051–08/02Figure 27. Timer 0 and Timer 1 Clock Controller and SymbolsTimer 0 Timer 0 functions as either a Timer or event Counter in

52AT8xC51324173A–8051–08/02Mode 1 (16-bit Timer) Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected incascade (see Figur

53AT8xC51324173A–8051–08/02Figure 34. Timer/Counter 0 in Mode 3: Two 8-bit CountersFigure 35. Mode 3 Overflow Period FormulaTimer 1 Timer 1 is ident

54AT8xC51324173A–8051–08/02Mode 1 (16-bit Timer) Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected incascade (see Figur

55AT8xC51324173A–8051–08/02Registers Table 58. TCON RegisterTCON (S:88h) – Timer/Counter Control RegisterReset Value = 0000 0000b76543210TF1 TR1 TF0

56AT8xC51324173A–8051–08/02Table 59. TMOD RegisterTMOD (89:h) - Timer/Counter 0 and 1 ModesReset Value = 0000 0000bNotes: 1. Reloaded from TH1 at ove

57AT8xC51324173A–8051–08/02Table 61. TL0 RegisterTL0 (S:8Ah) – Timer 0 Low Byte RegisterReset Value = 0000 0000bTable 62. TH1 RegisterTH1 (S:8Dh) –

58AT8xC51324173A–8051–08/02Watchdog Timer The AT8xC5132 implement a hardware Watchdog Timer (WDT) that automaticallyresets the chip if it is allowed t

59AT8xC51324173A–8051–08/02Watchdog Operation After reset, the WDT is disabled. The WDT is enabled by writing the sequence 1Eh andE1h into the WDTRST

6AT8xC51324173A–8051–08/02Pin Description All AT8xC5132 signals are detailed by functionality in Table 1 to Table 14.Table 1. Ports Signal Descriptio

60AT8xC51324173A–8051–08/02Registers Table 64. WDTRST RegisterWDTRST (S:A6h Write only) – Watchdog Timer Reset RegisterReset Value = XXXX XXXXbTable

61AT8xC51324173A–8051–08/02Audio Output InterfaceThe AT8xC5132 implement an audio output interface allowing the audio bitstream to beoutput in various

62AT8xC51324173A–8051–08/02Clock Generator The audio interface clock is generated by division of the PLL clock. The division factor isgiven by AUCD4:0

63AT8xC51324173A–8051–08/02Figure 43. Audio Output FormatThe data converter receives its audio stream from two sources selected by the SRC bitin AUDC

64AT8xC51324173A–8051–08/02Table 66. Sample Duplication FactorInterrupt Request The audio interrupt request can be generated by two sources when in C

65AT8xC51324173A–8051–08/02Figure 45. Voice or Sound Mode Audio FlowsNote: 1. An under-run occurrence signifies that the C51 core did not respond to

66AT8xC51324173A–8051–08/02Registers Table 67. AUDCON0 RegisterAUDCON0 (S:9Ah) – Audio Interface Control Register 0Reset Value = 0000 1000bTable 68.

67AT8xC51324173A–8051–08/02Table 69. AUDSTA RegisterAUDSTA (S:9Ch Read Only) – Audio Interface Status RegisterReset Value = 1100 0000bTable 70. AUDD

68AT8xC51324173A–8051–08/02Universal Serial Bus The AT8xC5132 implement a USB device controller supporting Full-speed data transfer.In addition to the

69AT8xC51324173A–8051–08/02Description The USB device controller provides the hardware that the AT8xC5132 need to interfacea USB link to data flow sto

7AT8xC51324173A–8051–08/02Table 3. Timer 0 and Timer 1 Signal Description Signal Name Type DescriptionAlternate FunctionINT0# ITimer 0 Gate InputINT0

70AT8xC51324173A–8051–08/02Serial Interface Engine (SIE) The SIE performs the following functions:• NRZI data encoding and decoding• Bit stuffing and

71AT8xC51324173A–8051–08/02Figure 49. UFI Block DiagramFigure 50. USB Typical Transaction LoadUSB Interrupt System As shown in Figure 51, the USB co

72AT8xC51324173A–8051–08/02Endpoint Interrupt Sources Each endpoint supports four interrupt sources reported in UEPSTAX and combinedtogether to appear

73AT8xC51324173A–8051–08/02Registers Table 72. USBCON RegisterUSBCON (S:BCh) – USB Global Control RegisterReset Value = 0000 0000b7 6 5 4 3 210USBE S

74AT8xC51324173A–8051–08/02Table 73. USBADDR RegisterUSBADDR (S:C6h) – USB Address RegisterReset Value = 0000 0000bTable 74. USBINT RegisterUSBINT (

75AT8xC51324173A–8051–08/02Table 75. USBIEN RegisterUSBIEN (S:BEh) – USB Global Interrupt Enable RegisterReset Value = 0001 0000bTable 76. UEPNUM Re

76AT8xC51324173A–8051–08/02Table 77. UEPCONX RegisterUEPCONX (S:D4h) – USB Endpoint X Control Register (X = EPNUM set in UEPNUM)Reset Value = 0000 00

77AT8xC51324173A–8051–08/02Table 78. UEPSTAX Register UEPSTAX (Soh) – USB Endpoint X Status and Control Register (X = EPNUM set in UEPNUM)Reset Value

78AT8xC51324173A–8051–08/02Table 79. UEPRST RegisterUEPRST (S:D5h) – USB Endpoint FIFO Reset RegisterReset Value = 0000 0000bTable 80. UEPINT Regist

79AT8xC51324173A–8051–08/02Table 81. UEPIEN RegisterUEPIEN (S:C2h) – USB Endpoint Interrupt Enable RegisterReset Value = 0000 0000bTable 82. UEPDATX

8AT8xC51324173A–8051–08/02Table 6. MutiMediaCard Interface Signal DescriptionSignal Name Type DescriptionAlternate FunctionMCLK OMMC Clock outputData

80AT8xC51324173A–8051–08/02Table 83. UBYCTLX RegisterUBYCTX (S:E2h) – USB Endpoint X Byte Count Register (X = EPNUM set in UEPNUM)Reset Value = 0000

81AT8xC51324173A–8051–08/02Table 85. UFNUMH RegisterUFNUMH (S:BBh, Read-only) – USB Frame Number High RegisterReset Value = 00hTable 86. USBCLK Regi

82AT8xC51324173A–8051–08/02MultiMedia Card ControllerThe AT8xC5132 implements a MultiMedia Card (MMC) controller. The MMC is used tostore files in rem

83AT8xC51324173A–8051–08/02Bus Lines The MultiMedia Card bus architecture requires all cards to be connected to the same setof lines. No card has an i

84AT8xC51324173A–8051–08/02Figure 53. (Multiple) Block Read OperationAs shown in Figure 54 and Figure 55 the data write operation uses a simple busy

85AT8xC51324173A–8051–08/02Table 87. Command Token FormatResponse Token Format There are five types of response tokens (R1 to R5). As shown in Figure

86AT8xC51324173A–8051–08/02Table 90. R3 Response Format (OCR Register)Table 91. R4 Response Format (Fast I/O)Table 92. R5 Response FormatData Packe

87AT8xC51324173A–8051–08/02Clock Control The MMC bus clock signal can be used by the host to turn the cards into energy savingmode or to control the d

88AT8xC51324173A–8051–08/02Clock Generator The MMC clock is generated by division of the oscillator clock (FOSC) issued from theClock Controller block

89AT8xC51324173A–8051–08/02Command Line ControllerAs shown in Figure 63, the command line controller is divided in two channels: the com-mand transmit

9AT8xC51324173A–8051–08/02Table 10. A/D Converter Signal DescriptionSignal Name Type DescriptionAlternate FunctionAIN1:0 I A/D Converter Analog Input

90AT8xC51324173A–8051–08/02The user may abort command loading by setting and clearing the CTPTR bit inMMCON0 register which resets the write pointer t

91AT8xC51324173A–8051–08/02Data Line Controller The data line controller is based on a 16-byte FIFO used both by the data transmitterchannel and by th

92AT8xC51324173A–8051–08/02Figure 66. Data Controller Configuration FlowsData TransmitterConfiguration For transmitting data to the card, user must f

93AT8xC51324173A–8051–08/02Figure 67. Data Stream Transmission FlowsSendSTOP CommandData Stream TransmissionStart TransmissionDATEN = 1DATEN = 0FIFO

94AT8xC51324173A–8051–08/02Figure 68. Data Block Transmission FlowsData ReceiverConfiguration To receive data from the card, the user must first conf

95AT8xC51324173A–8051–08/02This time-out may be disarmed after receiving 8 data (F1FI flag set) or after receivingend of frame (EOFI flag set) in case

96AT8xC51324173A–8051–08/02Figure 70. Data Block Reception FlowsFlow Control To allow transfer at high speed without taking care of CPU oscillator fr

97AT8xC51324173A–8051–08/02InterruptDescription As shown in Figure 71, the MMC controller implements eight interrupt sources reportedin MCBI, EORI, EO

98AT8xC51324173A–8051–08/02Registers Table 94. MMCON0 RegisterMMCON0 (S:E4h) – MMC Control Register 0Reset Value = 0000 0000b76543210DRPTR DTPTR CRPT

99AT8xC51324173A–8051–08/02Table 95. MMCON1 RegisterMMCON1 (S:E5h) – MMC Control Register 1Reset Value = 0000 0000bTable 96. MMCON2 RegisterMMCON2 (