Rainbow-electronics AT24C512 User Manual

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1
Features
Low-voltage and Standard-voltage Operation
–2.7(V
CC
=2.7Vto5.5V)
–1.8(V
CC
=1.8Vto3.6V)
Internally Organized 65,536 x 8
2-wire Serial Interface
Schmitt Triggers, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility
Write Protect Pin for Hardware and Software Data Protection
128-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5 ms Typical)
High Reliability
Endurance: 100,000 Write Cycles
Data Retention: 40 Years
Automotive Grade and Extended Temperature Devices Available
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead LAP and 8-ball dBGA
TM
Packages
Description
The AT24C512 provides 524,288 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’s
cascadable feature allows up to 4 devices to share a common 2-wire bus. The device
is optimized for use in many industrial and commercial applications where low-power
and low-voltage operation are essential. The devices are available in space-saving
8-pin PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead Leadless Array (LAP) and 8-
ball dBGA packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V)
and 1.8V (1.8V to 3.6V) versions.
Rev. 1116H–SEEPR–08/02
2-wire Serial
EEPROM
512K (65,536 x 8)
AT24C512
Pin Configurations
Pin Name Function
A0 - A1 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
NC No Connect
8-lead PDIP
1
2
3
4
8
7
6
5
A0
A1
NC
GND
VCC
WP
SCL
SDA
8-lead Leadless Array
Bottom View
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
NC
GND
8-lead TSSOP
1
2
3
4
8
7
6
5
A0
A1
NC
GND
VCC
WP
SCL
SDA
8-ball dBGA
Bottom View
VCC
WP
SCL
SDA
A0
A1
NC
GND
1
2
3
4
8
7
6
5
8-lead SOIC
1
2
3
4
8
7
6
5
A0
A1
NC
GND
VCC
WP
SCL
SDA
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Summary of Contents

Page 1 - AT24C512

1Features• Low-voltage and Standard-voltage Operation–2.7(VCC=2.7Vto5.5V)–1.8(VCC=1.8Vto3.6V)• Internally Organized 65,536 x 8• 2-wire Serial Interfac

Page 2

10AT24C5121116H–SEEPR–08/02Read Operations Read operations are initiated the same way as write operations with the exception thatthe read/write select

Page 3

11AT24C5121116H–SEEPR–08/02Figure 2. Byte WriteFigure 3. Page WriteFigure 4. Current Address Read

Page 4

12AT24C5121116H–SEEPR–08/02Figure 5. Random ReadFigure 6. Sequential Read

Page 5

13AT24C5121116H–SEEPR–08/02Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics

Page 6

14AT24C5121116H–SEEPR–08/02Packaging Information8CN1 – LAP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 8CN1, 8-lead (8 x 5 x 1.04

Page 7

15AT24C5121116H–SEEPR–08/028P3 – PDIP2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In

Page 8

16AT24C5121116H–SEEPR–08/028S1 – JEDEC SOIC 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. Note:10/10/018S1, 8-lead (0.150" Wid

Page 9

17AT24C5121116H–SEEPR–08/028A2 – TSSOP2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 5/30/02COMMON DIMENSIONS(Unit of Measure = mm)SYMB

Page 10

18AT24C5121116H–SEEPR–08/028U2 – dBGA1150 E. Cheyenne Mtn. Blvd.Colorado Springs, CO 80906TITLEDRAWING NO.RREV. 8U2, 8-ball 0.75 pitch, Die Ball Gri

Page 11

Printed on recycled paper.1116H–SEEPR–08/02 xM© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than tho

Page 12

2AT24C5121116H–SEEPR–08/02Block DiagramAbsolute Maximum Ratings*Operating Temperature ... -55°Cto+125°C*NOTICE: Stresse

Page 13

3AT24C5121116H–SEEPR–08/02Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into eachEEPROM device and negative ed

Page 14

4AT24C5121116H–SEEPR–08/02Note: 1. This parameter is characterized and is not 100% tested.Note: 1. VILmin and VIHmax are reference only and are not te

Page 15

5AT24C5121116H–SEEPR–08/02Notes: 1. This parameter is characterized and is not 100% tested.2. AC measurement conditions:RL(connects to VCC): 1.3 kΩ (2

Page 16

6AT24C5121116H–SEEPR–08/02Device Operation CLOCK and DATA TRANSITIONS: TheSDApinisnormallypulledhighwithanexter-nal device. Data on the SDA pin may ch

Page 17

7AT24C5121116H–SEEPR–08/02Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)Note: 1. The

Page 18

8AT24C5121116H–SEEPR–08/02Data ValidityStart and Stop DefinitionOutput Acknowledge

Page 19 - 1116H–SEEPR–08/02 xM

9AT24C5121116H–SEEPR–08/02Device Addressing The 512K EEPROM requires an 8-bit device address word following a start condition toenable the chip for a

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