Rainbow-electronics AT25DL161 User Manual

8795E–DFLASH–12/2012Features Single 1.65V – 1.95V supply Serial Peripheral Interface (SPI) compatible Supports SPI Modes 0 and 3 Supports RapidS™

10AT25DL161 [DATASHEET]8795E–DFLASH–12/2012Figure 7-1. Read Array – 1Bh OpcodeFigure 7-2. Read Array – 0Bh OpcodeFigure 7-3. Read Array – 03h OpcodeS

11AT25DL161 [DATASHEET]8795E–DFLASH–12/20127.2 Dual-Output Read ArrayThe Dual-Output Read Array command is similar to the standard Read Array command

12AT25DL161 [DATASHEET]8795E–DFLASH–12/20128. Program and Erase Commands8.1 Byte/Page ProgramThe Byte/Page program command allows anywhere from a sin

13AT25DL161 [DATASHEET]8795E–DFLASH–12/2012Figure 8-1. Byte ProgramFigure 8-2. Page ProgramSCKCSSISOMSB MSB231000000010675410119812 3937 3833 3635343

14AT25DL161 [DATASHEET]8795E–DFLASH–12/20128.2 Dual-Input Byte/Page ProgramThe Dual-Input Byte/Page Program command is similar to the standard Byte/P

15AT25DL161 [DATASHEET]8795E–DFLASH–12/2012Figure 8-3. Dual-Input Byte ProgramFigure 8-4. Dual-Input Page ProgramSCKCSSI (SIO)SO (SOI)MSB MSB23101010

16AT25DL161 [DATASHEET]8795E–DFLASH–12/20128.3 Block EraseA block of 4, 32, or 64KB can be erased (all bits set to the Logical 1 state) in a single o

17AT25DL161 [DATASHEET]8795E–DFLASH–12/20128.4 Chip EraseThe entire memory array can be erased in a single operation by using the Chip Erase command.

18AT25DL161 [DATASHEET]8795E–DFLASH–12/20128.5 Program/Erase SuspendIn some code-plus-data storage applications, it is often necessary to process cer

19AT25DL161 [DATASHEET]8795E–DFLASH–12/2012.Figure 8-7. Program/Erase SuspendTable 8-1. Operations Allowed and Not Allowed During a Program/Erase Sus

2AT25DL161 [DATASHEET]8795E–DFLASH–12/20121. DescriptionThe AT25DL161 is a serial interface Flash memory device designed for use in a wide variety of

20AT25DL161 [DATASHEET]8795E–DFLASH–12/20128.6 Program/Erase ResumeThe Program/Erase Resume command allows a suspended program or erase operation to

21AT25DL161 [DATASHEET]8795E–DFLASH–12/20129. Protection Commands and Features9.1 Write EnableThe Write Enable command is used to set the Write Enabl

22AT25DL161 [DATASHEET]8795E–DFLASH–12/20129.2 Write DisableThe Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status

23AT25DL161 [DATASHEET]8795E–DFLASH–12/20129.3 Protect SectorEvery physical 64KB sector of the device has a corresponding single-bit Sector Protectio

24AT25DL161 [DATASHEET]8795E–DFLASH–12/20129.4 Unprotect SectorIssuing the Unprotect Sector command to a particular sector address will reset the cor

25AT25DL161 [DATASHEET]8795E–DFLASH–12/20129.5 Global Protect/UnprotectThe Global Protect and Global Unprotect features can work in conjunction with

26AT25DL161 [DATASHEET]8795E–DFLASH–12/2012Table 9-2. Valid SPRL and Global Protect/Unprotect ConditionsWPStateCurrentSPRLValueNew Write StatusRegist

27AT25DL161 [DATASHEET]8795E–DFLASH–12/20129.6 Read Sector Protection RegistersThe Sector Protection Registers can be read to determine the current s

28AT25DL161 [DATASHEET]8795E–DFLASH–12/20129.7 Protected States and the Write Protect (WP) PinThe WP pin is not linked to the memory array itself and

29AT25DL161 [DATASHEET]8795E–DFLASH–12/201210. Security Commands10.1 Sector LockdownCertain applications require that portions of the Flash memory ar

3AT25DL161 [DATASHEET]8795E–DFLASH–12/20122. Pin Descriptions and PinoutsTable 2-1. Pin Descriptions Symbol Name and FunctionAssertedStateTypeCSChip

30AT25DL161 [DATASHEET]8795E–DFLASH–12/2012Figure 10-1. Sector Lockdown10.2 Freeze Sector Lockdown StateThe current sector lockdown state can be perm

31AT25DL161 [DATASHEET]8795E–DFLASH–12/201210.3 Read Sector Lockdown RegistersThe Sector Lockdown Registers can be read to determine the current lock

32AT25DL161 [DATASHEET]8795E–DFLASH–12/201210.4 Program OTP Security RegisterThe device contains a specialized OTP (One-Time Programmable) Security R

33AT25DL161 [DATASHEET]8795E–DFLASH–12/2012The three address bytes and at least one complete byte of data must be clocked into the device before the

34AT25DL161 [DATASHEET]8795E–DFLASH–12/201210.5 Read OTP Security RegisterThe OTP Security Register can be sequentially read in a similar fashion to

35AT25DL161 [DATASHEET]8795E–DFLASH–12/201211. Status Register Commands11.1 Read Status RegisterThe two-byte Status Register can be read to determine

36AT25DL161 [DATASHEET]8795E–DFLASH–12/2012Notes: 1. Only bits 4 and 3 of Status Register Byte 2 will be modified when using the Write Status Registe

37AT25DL161 [DATASHEET]8795E–DFLASH–12/201211.1.2 EPE BitThe EPE bit indicates whether the last erase or program operation completed successfully or

38AT25DL161 [DATASHEET]8795E–DFLASH–12/201211.1.6 RSTE BitThe RSTE bit is used to enable or disable the Reset command. When the RSTE bit is in the Lo

39AT25DL161 [DATASHEET]8795E–DFLASH–12/201211.2 Write Status Register Byte 1The Write Status Register Byte 1 command is used to modify the SPRL bit o

4AT25DL161 [DATASHEET]8795E–DFLASH–12/2012HOLDHold: The HOLD pin is used to temporarily pause serial communication without deselecting or resetting

40AT25DL161 [DATASHEET]8795E–DFLASH–12/201211.3 Write Status Register Byte 2The Write Status Register Byte 2 command is used to modify the RSTE and S

41AT25DL161 [DATASHEET]8795E–DFLASH–12/201212. Other Commands and Functions12.1 ResetIn some applications, it may be necessary to prematurely termina

42AT25DL161 [DATASHEET]8795E–DFLASH–12/201212.2 Read Manufacturer and Device IDIdentification information can be read from the device to enable syste

43AT25DL161 [DATASHEET]8795E–DFLASH–12/2012Figure 12-2. Read Manufacturer and Device IDSCKCSSISO609Fh87 46Opcode1Fh 03h 01h 00hManufacturer ID Device

44AT25DL161 [DATASHEET]8795E–DFLASH–12/201212.3 Deep Power-DownDuring normal operation, the device will be placed in the standby mode to consume less

45AT25DL161 [DATASHEET]8795E–DFLASH–12/201212.4 Resume from Deep Power-DownIn order to exit the Deep Power-Down mode and resume normal device operati

46AT25DL161 [DATASHEET]8795E–DFLASH–12/201212.5 HoldThe HOLD pin is used to pause the serial communication with the device without having to stop or

47AT25DL161 [DATASHEET]8795E–DFLASH–12/201213. RapidS ImplementationTo implement RapidS and operate at clock frequencies higher than what can be achi

48AT25DL161 [DATASHEET]8795E–DFLASH–12/201214. Electrical Specifications14.1 Absolute Maximum Ratings* 14.2 DC and AC Operating Range14.3 DC Characte

49AT25DL161 [DATASHEET]8795E–DFLASH–12/201214.4 AC Characteristics – Maximum Clock Frequencies14.5 AC Characteristics – All Other ParametersNotes: 1.

5AT25DL161 [DATASHEET]8795E–DFLASH–12/20123. Block DiagramFigure 3-1. Block DiagramFlashMemoryArrayY-GatingCSSCKNote: SIO and SOI pin naming conven

50AT25DL161 [DATASHEET]8795E–DFLASH–12/201214.6 Program and Erase CharacteristicsNotes: 1. Maximum values indicate worst-case performance after 100,0

51AT25DL161 [DATASHEET]8795E–DFLASH–12/201215. AC WaveformsFigure 15-1. Serial Input TimingFigure 15-2. Serial Output TimingFigure 15-3.WP Timing for

52AT25DL161 [DATASHEET]8795E–DFLASH–12/2012Figure 15-4. HOLD Timing – Serial InputFigure 15-5.HOLD Timing – Serial OutputCSSISCKSOtHHHtHLStHLHtHHSHOL

53AT25DL161 [DATASHEET]8795E–DFLASH–12/201216. Ordering Information16.1 Ordering Code Detail16.2 Green Package Options (Pb/halide-free/RoHS-compliant

54AT25DL161 [DATASHEET]8795E–DFLASH–12/201217. Packaging Information17.1 8S1 — 8-lead JEDEC SOICDRAWING NO. REV. TITLE GPCCOMMON DIMENSIONS(Unit of

55AT25DL161 [DATASHEET]8795E–DFLASH–12/201217.2 8MA1 — 8-pad UDFNTITLEDRAWING NO.GPCREV.Package Drawing Contact:[email protected] YFG D 8M

56AT25DL161 [DATASHEET]8795E–DFLASH–12/201217.3 8U-4 — 8-ball WLCSPDRAWING NO. REV. GPCTITLE8U-4 B3/22/12GFB8U-4, 8-ball, (4x2 Array) Wafer Level Ch

57AT25DL161 [DATASHEET]8795E–DFLASH–12/201218. Revision HistoryDoc. Rev. Date Comments8795E 12/2012 Add labels to pins in dBGA package8795D 12/2012 U

Corporate OfficeCalifornia | USAAdesto Headquarters1250 Borregas AvenueSunnyvale, CA 94089 Phone: (+1) 408.400.0578Email: [email protected]© 2012

6AT25DL161 [DATASHEET]8795E–DFLASH–12/20124. Memory ArrayTo provide the greatest flexibility, the AT25DL161 memory array can be erased in four levels

7AT25DL161 [DATASHEET]8795E–DFLASH–12/20125. Device OperationThe AT25DL161 is controlled by a set of instructions that are sent from a host controlle

8AT25DL161 [DATASHEET]8795E–DFLASH–12/2012Table 6-1. Command Listing CommandClockFrequencyAddressBytesDummyBytesDataBytesRead CommandsRead Array1Bh 0

9AT25DL161 [DATASHEET]8795E–DFLASH–12/20127. Read Commands7.1 Read ArrayThe Read Array command can be used to sequentially read a continuous stream o